pfc-r8a7778.c - cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	cachepc-linux Fork of AMDESE/linux with modifications for CachePC side-channel attack
	git clone https://git.sinitax.com/sinitax/cachepc-linux
	Log \| Files \| Refs \| README \| LICENSE \| sfeed.txt
pfc-r8a7778.c (105186B)
      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * r8a7778 processor support - PFC hardware block
      4 *
      5 * Copyright (C) 2013  Renesas Solutions Corp.
      6 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
      7 * Copyright (C) 2013  Cogent Embedded, Inc.
      8 * Copyright (C) 2015  Ulrich Hecht
      9 *
     10 * based on
     11 * Copyright (C) 2011  Renesas Solutions Corp.
     12 * Copyright (C) 2011  Magnus Damm
     13 */
     14
     15#include <linux/io.h>
     16#include <linux/kernel.h>
     17#include <linux/pinctrl/pinconf-generic.h>
     18
     19#include "sh_pfc.h"
     20
     21#define CPU_ALL_GP(fn, sfx)		\
     22	PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     23	PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     24	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     25	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     26	PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
     27
     28#define CPU_ALL_NOGP(fn)		\
     29	PIN_NOGP(CLKOUT, "B25", fn),	\
     30	PIN_NOGP(CS0, "A20", fn),	\
     31	PIN_NOGP(CS1_A26, "C20", fn)
     32
     33enum {
     34	PINMUX_RESERVED = 0,
     35
     36	PINMUX_DATA_BEGIN,
     37	GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
     38	PINMUX_DATA_END,
     39
     40	PINMUX_FUNCTION_BEGIN,
     41	GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
     42
     43	/* GPSR0 */
     44	FN_IP0_1_0,	FN_PENC0,	FN_PENC1,	FN_IP0_4_2,
     45	FN_IP0_7_5,	FN_IP0_11_8,	FN_IP0_14_12,	FN_A1,
     46	FN_A2,		FN_A3,		FN_IP0_15,	FN_IP0_16,
     47	FN_IP0_17,	FN_IP0_18,	FN_IP0_19,	FN_IP0_20,
     48	FN_IP0_21,	FN_IP0_22,	FN_IP0_23,	FN_IP0_24,
     49	FN_IP0_25,	FN_IP0_26,	FN_IP0_27,	FN_IP0_28,
     50	FN_IP0_29,	FN_IP0_30,	FN_IP1_0,	FN_IP1_1,
     51	FN_IP1_4_2,	FN_IP1_7_5,	FN_IP1_10_8,	FN_IP1_14_11,
     52
     53	/* GPSR1 */
     54	FN_IP1_23_21,	FN_WE0,		FN_IP1_24,	FN_IP1_27_25,
     55	FN_IP1_29_28,	FN_IP2_2_0,	FN_IP2_5_3,	FN_IP2_8_6,
     56	FN_IP2_11_9,	FN_IP2_13_12,	FN_IP2_16_14,	FN_IP2_17,
     57	FN_IP2_30,	FN_IP2_31,	FN_IP3_1_0,	FN_IP3_4_2,
     58	FN_IP3_7_5,	FN_IP3_9_8,	FN_IP3_12_10,	FN_IP3_15_13,
     59	FN_IP3_18_16,	FN_IP3_20_19,	FN_IP3_23_21,	FN_IP3_26_24,
     60	FN_IP3_27,	FN_IP3_28,	FN_IP3_29,	FN_IP3_30,
     61	FN_IP3_31,	FN_IP4_0,	FN_IP4_3_1,	FN_IP4_6_4,
     62
     63	/* GPSR2 */
     64	FN_IP4_7,	FN_IP4_8,	FN_IP4_10_9,	FN_IP4_12_11,
     65	FN_IP4_14_13,	FN_IP4_16_15,	FN_IP4_20_17,	FN_IP4_24_21,
     66	FN_IP4_26_25,	FN_IP4_28_27,	FN_IP4_30_29,	FN_IP5_1_0,
     67	FN_IP5_3_2,	FN_IP5_5_4,	FN_IP5_6,	FN_IP5_7,
     68	FN_IP5_9_8,	FN_IP5_11_10,	FN_IP5_12,	FN_IP5_14_13,
     69	FN_IP5_17_15,	FN_IP5_20_18,	FN_AUDIO_CLKA,	FN_AUDIO_CLKB,
     70	FN_IP5_22_21,	FN_IP5_25_23,	FN_IP5_28_26,	FN_IP5_30_29,
     71	FN_IP6_1_0,	FN_IP6_4_2,	FN_IP6_6_5,	FN_IP6_7,
     72
     73	/* GPSR3 */
     74	FN_IP6_8,	FN_IP6_9,	FN_SSI_SCK34,	FN_IP6_10,
     75	FN_IP6_12_11,	FN_IP6_13,	FN_IP6_15_14,	FN_IP6_16,
     76	FN_IP6_18_17,	FN_IP6_20_19,	FN_IP6_21,	FN_IP6_23_22,
     77	FN_IP6_25_24,	FN_IP6_27_26,	FN_IP6_29_28,	FN_IP6_31_30,
     78	FN_IP7_1_0,	FN_IP7_3_2,	FN_IP7_5_4,	FN_IP7_8_6,
     79	FN_IP7_11_9,	FN_IP7_14_12,	FN_IP7_17_15,	FN_IP7_20_18,
     80	FN_IP7_21,	FN_IP7_24_22,	FN_IP7_28_25,	FN_IP7_31_29,
     81	FN_IP8_2_0,	FN_IP8_5_3,	FN_IP8_8_6,	FN_IP8_10_9,
     82
     83	/* GPSR4 */
     84	FN_IP8_13_11,	FN_IP8_15_14,	FN_IP8_18_16,	FN_IP8_21_19,
     85	FN_IP8_23_22,	FN_IP8_26_24,	FN_IP8_29_27,	FN_IP9_2_0,
     86	FN_IP9_5_3,	FN_IP9_8_6,	FN_IP9_11_9,	FN_IP9_14_12,
     87	FN_IP9_17_15,	FN_IP9_20_18,	FN_IP9_23_21,	FN_IP9_26_24,
     88	FN_IP9_29_27,	FN_IP10_2_0,	FN_IP10_5_3,	FN_IP10_8_6,
     89	FN_IP10_12_9,	FN_IP10_15_13,	FN_IP10_18_16,	FN_IP10_21_19,
     90	FN_IP10_24_22,	FN_AVS1,	FN_AVS2,
     91
     92	/* IPSR0 */
     93	FN_PRESETOUT,	FN_PWM1,	FN_AUDATA0,	FN_ARM_TRACEDATA_0,
     94	FN_GPSCLK_C,	FN_USB_OVC0,	FN_TX2_E,	FN_SDA2_B,
     95	FN_AUDATA1,	FN_ARM_TRACEDATA_1,		FN_GPSIN_C,
     96	FN_USB_OVC1,	FN_RX2_E,	FN_SCL2_B,	FN_SD1_DAT2_A,
     97	FN_MMC_D2,	FN_BS,		FN_ATADIR0_A,	FN_SDSELF_A,
     98	FN_PWM4_B,	FN_SD1_DAT3_A,	FN_MMC_D3,	FN_A0,
     99	FN_ATAG0_A,	FN_REMOCON_B,	FN_A4,		FN_A5,
    100	FN_A6,		FN_A7,		FN_A8,		FN_A9,
    101	FN_A10,		FN_A11,		FN_A12,		FN_A13,
    102	FN_A14,		FN_A15,		FN_A16,		FN_A17,
    103	FN_A18,		FN_A19,
    104
    105	/* IPSR1 */
    106	FN_A20,		FN_HSPI_CS1_B,	FN_A21,		FN_HSPI_CLK1_B,
    107	FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
    108	FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
    109	FN_TS_SDEN0_A,	FN_SD1_CD_A,	FN_MMC_D6,	FN_A24,
    110	FN_DREQ1_A,	FN_HRX0_B,	FN_TS_SPSYNC0_A,
    111	FN_SD1_WP_A,	FN_MMC_D7,	FN_A25,	FN_DACK1_A,
    112	FN_HCTS0_B,	FN_RX3_C,	FN_TS_SDAT0_A,	FN_CLKOUT,
    113	FN_HSPI_TX1_B,	FN_PWM0_B,	FN_CS0,		FN_HSPI_RX1_B,
    114	FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
    115	FN_SCK2_B,	FN_MMC_D5,	FN_ATADIR0_B,	FN_RD_WR,
    116	FN_WE1,		FN_ATAWR0_B,	FN_SSI_WS1_B,	FN_EX_CS0,
    117	FN_SCL2_A,	FN_TX3_C,	FN_TS_SCK0_A,	FN_EX_CS1,
    118	FN_MMC_D4,
    119
    120	/* IPSR2 */
    121	FN_SD1_CLK_A,	FN_MMC_CLK,	FN_ATACS00,	FN_EX_CS2,
    122	FN_SD1_CMD_A,	FN_MMC_CMD,	FN_ATACS10,	FN_EX_CS3,
    123	FN_SD1_DAT0_A,	FN_MMC_D0,	FN_ATARD0,	FN_EX_CS4,
    124	FN_EX_WAIT1_A,	FN_SD1_DAT1_A,	FN_MMC_D1,	FN_ATAWR0_A,
    125	FN_EX_CS5,	FN_EX_WAIT2_A,	FN_DREQ0_A,	FN_RX3_A,
    126	FN_DACK0,	FN_TX3_A,	FN_DRACK0,	FN_EX_WAIT0,
    127	FN_PWM0_C,	FN_D0,		FN_D1,		FN_D2,
    128	FN_D3,		FN_D4,		FN_D5,		FN_D6,
    129	FN_D7,		FN_D8,		FN_D9,		FN_D10,
    130	FN_D11,		FN_RD_WR_B,	FN_IRQ0,	FN_MLB_CLK,
    131	FN_IRQ1_A,
    132
    133	/* IPSR3 */
    134	FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
    135	FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
    136	FN_SDSELF_B,	FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,
    137	FN_CAN_CLK_B,	FN_SDA3_B,	FN_SD1_CLK_B,	FN_HTX0_A,
    138	FN_TX0_A,	FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,
    139	FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
    140	FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	FN_SD1_DAT3_B,
    141	FN_HRTS0_A,	FN_RTS0,	FN_SSI_SCK4,	FN_DU0_DR0,
    142	FN_LCDOUT0,	FN_AUDATA2,	FN_ARM_TRACEDATA_2,
    143	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,	FN_SSI_WS4,
    144	FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,	FN_ARM_TRACEDATA_3,
    145	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
    146	FN_DU0_DR2,	FN_LCDOUT2,	FN_DU0_DR3,	FN_LCDOUT3,
    147	FN_DU0_DR4,	FN_LCDOUT4,	FN_DU0_DR5,	FN_LCDOUT5,
    148	FN_DU0_DR6,	FN_LCDOUT6,
    149
    150	/* IPSR4 */
    151	FN_DU0_DR7,	FN_LCDOUT7,	FN_DU0_DG0,	FN_LCDOUT8,
    152	FN_AUDATA4,	FN_ARM_TRACEDATA_4,		FN_TX1_D,
    153	FN_CAN0_TX_A,	FN_ADICHS0,	FN_DU0_DG1,	FN_LCDOUT9,
    154	FN_AUDATA5,	FN_ARM_TRACEDATA_5,		FN_RX1_D,
    155	FN_CAN0_RX_A,	FN_ADIDATA,	FN_DU0_DG2,	FN_LCDOUT10,
    156	FN_DU0_DG3,	FN_LCDOUT11,	FN_DU0_DG4,	FN_LCDOUT12,
    157	FN_RX0_B,	FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,
    158	FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	FN_DU0_DG7,
    159	FN_LCDOUT15,	FN_TX4_A,	FN_SSI_SCK2_B,	FN_VI0_R0_B,
    160	FN_DU0_DB0,	FN_LCDOUT16,	FN_AUDATA6,	FN_ARM_TRACEDATA_6,
    161	FN_GPSCLK_A,	FN_PWM0_A,	FN_ADICLK,	FN_TS_SDAT0_B,
    162	FN_AUDIO_CLKC,	FN_VI0_R1_B,	FN_DU0_DB1,	FN_LCDOUT17,
    163	FN_AUDATA7,	FN_ARM_TRACEDATA_7,		FN_GPSIN_A,
    164	FN_ADICS_SAMP,	FN_TS_SCK0_B,	FN_VI0_R2_B,	FN_DU0_DB2,
    165	FN_LCDOUT18,	FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,
    166	FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,
    167
    168	/* IPSR5 */
    169	FN_VI0_R5_B,	FN_DU0_DB5,	FN_LCDOUT21,	FN_VI1_DATA10_B,
    170	FN_DU0_DB6,	FN_LCDOUT22,	FN_VI1_DATA11_B,
    171	FN_DU0_DB7,	FN_LCDOUT23,	FN_DU0_DOTCLKIN,
    172	FN_QSTVA_QVS,	FN_DU0_DOTCLKO_UT0,		FN_QCLK,
    173	FN_DU0_DOTCLKO_UT1,		FN_QSTVB_QVE,	FN_AUDIO_CLKOUT_A,
    174	FN_REMOCON_C,	FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
    175	FN_QSTH_QHS,	FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
    176	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
    177	FN_QCPV_QDE,	FN_FMCLK_D,	FN_SSI_SCK1_A,	FN_DU0_DISP,
    178	FN_QPOLA,	FN_AUDCK,	FN_ARM_TRACECLK,
    179	FN_BPFCLK_D,	FN_SSI_WS1_A,	FN_DU0_CDE,	FN_QPOLB,
    180	FN_AUDSYNC,	FN_ARM_TRACECTL,		FN_FMIN_D,
    181	FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
    182	FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
    183	FN_CAN_CLK_D,	FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,
    184	FN_TX2_A,	FN_CAN0_TX_B,	FN_SSI_SDATA7,	FN_HSPI_TX0_B,
    185	FN_RX2_A,	FN_CAN0_RX_B,
    186
    187	/* IPSR6 */
    188	FN_SSI_SCK6,	FN_HSPI_RX2_A,	FN_FMCLK_B,	FN_CAN1_TX_B,
    189	FN_SSI_WS6,	FN_HSPI_CLK2_A,	FN_BPFCLK_B,	FN_CAN1_RX_B,
    190	FN_SSI_SDATA6,	FN_HSPI_TX2_A,	FN_FMIN_B,	FN_SSI_SCK5,
    191	FN_RX4_C,	FN_SSI_WS5,	FN_TX4_C,	FN_SSI_SDATA5,
    192	FN_RX0_D,	FN_SSI_WS34,	FN_ARM_TRACEDATA_8,
    193	FN_SSI_SDATA4,	FN_SSI_WS2_A,	FN_ARM_TRACEDATA_9,
    194	FN_SSI_SDATA3,	FN_ARM_TRACEDATA_10,
    195	FN_SSI_SCK012,	FN_ARM_TRACEDATA_11,
    196	FN_TX0_D,	FN_SSI_WS012,	FN_ARM_TRACEDATA_12,
    197	FN_SSI_SDATA2,	FN_HSPI_CS2_A,	FN_ARM_TRACEDATA_13,
    198	FN_SDA1_A,	FN_SSI_SDATA1,	FN_ARM_TRACEDATA_14,
    199	FN_SCL1_A,	FN_SCK2_A,	FN_SSI_SDATA0,
    200	FN_ARM_TRACEDATA_15,
    201	FN_SD0_CLK,	FN_SUB_TDO,	FN_SD0_CMD,	FN_SUB_TRST,
    202	FN_SD0_DAT0,	FN_SUB_TMS,	FN_SD0_DAT1,	FN_SUB_TCK,
    203	FN_SD0_DAT2,	FN_SUB_TDI,
    204
    205	/* IPSR7 */
    206	FN_SD0_DAT3,	FN_IRQ1_B,	FN_SD0_CD,	FN_TX5_A,
    207	FN_SD0_WP,	FN_RX5_A,	FN_VI1_CLKENB,	FN_HSPI_CLK0_A,
    208	FN_HTX1_A,	FN_RTS1_C,	FN_VI1_FIELD,	FN_HSPI_CS0_A,
    209	FN_HRX1_A,	FN_SCK1_C,	FN_VI1_HSYNC,	FN_HSPI_RX0_A,
    210	FN_HRTS1_A,	FN_FMCLK_A,	FN_RX1_C,	FN_VI1_VSYNC,
    211	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,	FN_TX1_C,
    212	FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	FN_IRQ2_C,
    213	FN_CTS1_C,	FN_SPEEDIN,	FN_VI0_CLK,	FN_CAN_CLK_A,
    214	FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
    215	FN_HSPI_RX1_A,	FN_RX4_B,	FN_VI0_FIELD,	FN_SD2_DAT3_B,
    216	FN_VI0_R3_C,	FN_VI1_DATA1,	FN_DU1_DG7,	FN_HSPI_CLK1_A,
    217	FN_TX4_B,	FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,
    218	FN_DU1_DR2,	FN_HSPI_CS1_A,	FN_RX3_B,
    219
    220	/* IPSR8 */
    221	FN_VI0_VSYNC,	FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
    222	FN_HSPI_TX1_A,	FN_TX3_B,	FN_VI0_DATA0_VI0_B0,
    223	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,	FN_VI0_DATA1_VI0_B1,
    224	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,	FN_VI0_DATA2_VI0_B2,
    225	FN_DU1_DG4,	FN_RX0_C,	FN_VI0_DATA3_VI0_B3,
    226	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,	FN_VI0_DATA4_VI0_B4,
    227	FN_DU1_DB2,	FN_RX1_A,	FN_VI0_DATA5_VI0_B5,
    228	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,	FN_HSCK1_B,
    229	FN_VI0_DATA6_VI0_G0,		FN_DU1_DB4,	FN_CTS1_A,
    230	FN_PWM5,	FN_VI0_DATA7_VI0_G1,		FN_DU1_DB5,
    231	FN_RTS1_A,	FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,
    232	FN_DU1_DR4,	FN_HTX1_B,	FN_VI0_G3,	FN_SD2_CMD_B,
    233	FN_VI1_DATA5,	FN_DU1_DR5,	FN_HRX1_B,
    234
    235	/* IPSR9 */
    236	FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
    237	FN_HRTS1_B,	FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,
    238	FN_DU1_DR7,	FN_HCTS1_B,	FN_VI0_R0_A,	FN_VI1_CLK,
    239	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,		FN_VI0_R1_A,
    240	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,	FN_PWM2,
    241	FN_TCLK1,	FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,
    242	FN_ETH_TXD1,	FN_PWM3,	FN_VI0_R3_A,	FN_ETH_CRS_DV,
    243	FN_IECLK,	FN_SCK2_C,	FN_VI0_R4_A,	FN_ETH_TX_EN,
    244	FN_IETX,	FN_TX2_C,	FN_VI0_R5_A,	FN_ETH_RX_ER,
    245	FN_FMCLK_C,	FN_IERX,	FN_RX2_C,	FN_VI1_DATA10_A,
    246	FN_DU1_DOTCLKOUT,		FN_ETH_RXD0,	FN_BPFCLK_C,
    247	FN_TX2_D,	FN_SDA2_C,	FN_VI1_DATA11_A,
    248	FN_DU1_EXHSYNC_DU1_HSYNC,	FN_ETH_RXD1,	FN_FMIN_C,
    249	FN_RX2_D,	FN_SCL2_C,
    250
    251	/* IPSR10 */
    252	FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,	FN_ATARD1,
    253	FN_ETH_MDC,	FN_SDA1_B,	FN_SD2_CMD_A,
    254	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,		FN_ATAWR1,
    255	FN_ETH_MDIO,	FN_SCL1_B,	FN_SD2_DAT0_A,	FN_DU1_DISP,
    256	FN_ATACS01,	FN_DREQ1_B,	FN_ETH_LINK,	FN_CAN1_RX_A,
    257	FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
    258	FN_ETH_MAGIC,	FN_CAN1_TX_A,	FN_PWM6,	FN_SD2_DAT2_A,
    259	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,	FN_HSPI_CLK2_B,
    260	FN_GPSCLK_B,	FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,
    261	FN_ATAG1,	FN_HSPI_CS2_B,	FN_GPSIN_B,	FN_SD2_CD_A,
    262	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,	FN_HSPI_RX2_B,
    263	FN_REMOCON_A,	FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,
    264	FN_DACK0_B,	FN_HSPI_TX2_B,	FN_CAN_CLK_C,
    265
    266	/* SEL */
    267	FN_SEL_SCIF5_A,	FN_SEL_SCIF5_B,
    268	FN_SEL_SCIF4_A,	FN_SEL_SCIF4_B,	FN_SEL_SCIF4_C,
    269	FN_SEL_SCIF3_A,	FN_SEL_SCIF3_B,	FN_SEL_SCIF3_C,	FN_SEL_SCIF3_D,
    270	FN_SEL_SCIF2_A,	FN_SEL_SCIF2_B,	FN_SEL_SCIF2_C,	FN_SEL_SCIF2_D,	FN_SEL_SCIF2_E,
    271	FN_SEL_SCIF1_A,	FN_SEL_SCIF1_B,	FN_SEL_SCIF1_C,	FN_SEL_SCIF1_D,
    272	FN_SEL_SCIF0_A,	FN_SEL_SCIF0_B,	FN_SEL_SCIF0_C,	FN_SEL_SCIF0_D,
    273	FN_SEL_SSI2_A,	FN_SEL_SSI2_B,
    274	FN_SEL_SSI1_A,	FN_SEL_SSI1_B,
    275	FN_SEL_VI1_A,	FN_SEL_VI1_B,
    276	FN_SEL_VI0_A,	FN_SEL_VI0_B,	FN_SEL_VI0_C,	FN_SEL_VI0_D,
    277	FN_SEL_SD2_A,	FN_SEL_SD2_B,
    278	FN_SEL_SD1_A,	FN_SEL_SD1_B,
    279	FN_SEL_IRQ3_A,	FN_SEL_IRQ3_B,
    280	FN_SEL_IRQ2_A,	FN_SEL_IRQ2_B,	FN_SEL_IRQ2_C,
    281	FN_SEL_IRQ1_A,	FN_SEL_IRQ1_B,
    282	FN_SEL_DREQ2_A,	FN_SEL_DREQ2_B,
    283	FN_SEL_DREQ1_A,	FN_SEL_DREQ1_B,
    284	FN_SEL_DREQ0_A,	FN_SEL_DREQ0_B,
    285	FN_SEL_WAIT2_A,	FN_SEL_WAIT2_B,
    286	FN_SEL_WAIT1_A,	FN_SEL_WAIT1_B,
    287	FN_SEL_CAN1_A,	FN_SEL_CAN1_B,
    288	FN_SEL_CAN0_A,	FN_SEL_CAN0_B,
    289	FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
    290	FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
    291	FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
    292	FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
    293	FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,	FN_SEL_REMOCON_C,
    294	FN_SEL_FM_A,	FN_SEL_FM_B,	FN_SEL_FM_C,	FN_SEL_FM_D,
    295	FN_SEL_GPS_A,	FN_SEL_GPS_B,	FN_SEL_GPS_C,
    296	FN_SEL_TSIF0_A,	FN_SEL_TSIF0_B,
    297	FN_SEL_HSPI2_A,	FN_SEL_HSPI2_B,
    298	FN_SEL_HSPI1_A,	FN_SEL_HSPI1_B,
    299	FN_SEL_HSPI0_A,	FN_SEL_HSPI0_B,
    300	FN_SEL_I2C3_A,	FN_SEL_I2C3_B,	FN_SEL_I2C3_C,
    301	FN_SEL_I2C2_A,	FN_SEL_I2C2_B,	FN_SEL_I2C2_C,
    302	FN_SEL_I2C1_A,	FN_SEL_I2C1_B,
    303	PINMUX_FUNCTION_END,
    304
    305	PINMUX_MARK_BEGIN,
    306
    307	/* GPSR0 */
    308	PENC0_MARK,	PENC1_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
    309
    310	/* GPSR1 */
    311	WE0_MARK,
    312
    313	/* GPSR2 */
    314	AUDIO_CLKA_MARK,
    315	AUDIO_CLKB_MARK,
    316
    317	/* GPSR3 */
    318	SSI_SCK34_MARK,
    319
    320	/* GPSR4 */
    321	AVS1_MARK,
    322	AVS2_MARK,
    323
    324	VI0_R0_C_MARK,		/* see sel_vi0 */
    325	VI0_R1_C_MARK,		/* see sel_vi0 */
    326	VI0_R2_C_MARK,		/* see sel_vi0 */
    327	/* VI0_R3_C_MARK, */
    328	VI0_R4_C_MARK,		/* see sel_vi0 */
    329	VI0_R5_C_MARK,		/* see sel_vi0 */
    330
    331	VI0_R0_D_MARK,		/* see sel_vi0 */
    332	VI0_R1_D_MARK,		/* see sel_vi0 */
    333	VI0_R2_D_MARK,		/* see sel_vi0 */
    334	VI0_R3_D_MARK,		/* see sel_vi0 */
    335	VI0_R4_D_MARK,		/* see sel_vi0 */
    336	VI0_R5_D_MARK,		/* see sel_vi0 */
    337
    338	/* IPSR0 */
    339	PRESETOUT_MARK,	PWM1_MARK,	AUDATA0_MARK,
    340	ARM_TRACEDATA_0_MARK,		GPSCLK_C_MARK,	USB_OVC0_MARK,
    341	TX2_E_MARK,	SDA2_B_MARK,	AUDATA1_MARK,	ARM_TRACEDATA_1_MARK,
    342	GPSIN_C_MARK,	USB_OVC1_MARK,	RX2_E_MARK,	SCL2_B_MARK,
    343	SD1_DAT2_A_MARK,		MMC_D2_MARK,	BS_MARK,
    344	ATADIR0_A_MARK,	SDSELF_A_MARK,	PWM4_B_MARK,	SD1_DAT3_A_MARK,
    345	MMC_D3_MARK,	A0_MARK,	ATAG0_A_MARK,	REMOCON_B_MARK,
    346	A4_MARK,	A5_MARK,	A6_MARK,	A7_MARK,
    347	A8_MARK,	A9_MARK,	A10_MARK,	A11_MARK,
    348	A12_MARK,	A13_MARK,	A14_MARK,	A15_MARK,
    349	A16_MARK,	A17_MARK,	A18_MARK,	A19_MARK,
    350
    351	/* IPSR1 */
    352	A20_MARK,	HSPI_CS1_B_MARK,		A21_MARK,
    353	HSPI_CLK1_B_MARK,		A22_MARK,	HRTS0_B_MARK,
    354	RX2_B_MARK,	DREQ2_A_MARK,	A23_MARK,	HTX0_B_MARK,
    355	TX2_B_MARK,	DACK2_A_MARK,	TS_SDEN0_A_MARK,
    356	SD1_CD_A_MARK,	MMC_D6_MARK,	A24_MARK,	DREQ1_A_MARK,
    357	HRX0_B_MARK,	TS_SPSYNC0_A_MARK,		SD1_WP_A_MARK,
    358	MMC_D7_MARK,	A25_MARK,	DACK1_A_MARK,	HCTS0_B_MARK,
    359	RX3_C_MARK,	TS_SDAT0_A_MARK,		CLKOUT_MARK,
    360	HSPI_TX1_B_MARK,		PWM0_B_MARK,	CS0_MARK,
    361	HSPI_RX1_B_MARK,		SSI_SCK1_B_MARK,
    362	ATAG0_B_MARK,	CS1_A26_MARK,	SDA2_A_MARK,	SCK2_B_MARK,
    363	MMC_D5_MARK,	ATADIR0_B_MARK,	RD_WR_MARK,	WE1_MARK,
    364	ATAWR0_B_MARK,	SSI_WS1_B_MARK,	EX_CS0_MARK,	SCL2_A_MARK,
    365	TX3_C_MARK,	TS_SCK0_A_MARK,	EX_CS1_MARK,	MMC_D4_MARK,
    366
    367	/* IPSR2 */
    368	SD1_CLK_A_MARK,	MMC_CLK_MARK,	ATACS00_MARK,	EX_CS2_MARK,
    369	SD1_CMD_A_MARK,	MMC_CMD_MARK,	ATACS10_MARK,	EX_CS3_MARK,
    370	SD1_DAT0_A_MARK,		MMC_D0_MARK,	ATARD0_MARK,
    371	EX_CS4_MARK,	EX_WAIT1_A_MARK,		SD1_DAT1_A_MARK,
    372	MMC_D1_MARK,	ATAWR0_A_MARK,	EX_CS5_MARK,	EX_WAIT2_A_MARK,
    373	DREQ0_A_MARK,	RX3_A_MARK,	DACK0_MARK,	TX3_A_MARK,
    374	DRACK0_MARK,	EX_WAIT0_MARK,	PWM0_C_MARK,	D0_MARK,
    375	D1_MARK,	D2_MARK,	D3_MARK,	D4_MARK,
    376	D5_MARK,	D6_MARK,	D7_MARK,	D8_MARK,
    377	D9_MARK,	D10_MARK,	D11_MARK,	RD_WR_B_MARK,
    378	IRQ0_MARK,	MLB_CLK_MARK,	IRQ1_A_MARK,
    379
    380	/* IPSR3 */
    381	MLB_SIG_MARK,	RX5_B_MARK,	SDA3_A_MARK,	IRQ2_A_MARK,
    382	MLB_DAT_MARK,	TX5_B_MARK,	SCL3_A_MARK,	IRQ3_A_MARK,
    383	SDSELF_B_MARK,	SD1_CMD_B_MARK,	SCIF_CLK_MARK,	AUDIO_CLKOUT_B_MARK,
    384	CAN_CLK_B_MARK,	SDA3_B_MARK,	SD1_CLK_B_MARK,	HTX0_A_MARK,
    385	TX0_A_MARK,	SD1_DAT0_B_MARK,		HRX0_A_MARK,
    386	RX0_A_MARK,	SD1_DAT1_B_MARK,		HSCK0_MARK,
    387	SCK0_MARK,	SCL3_B_MARK,	SD1_DAT2_B_MARK,
    388	HCTS0_A_MARK,	CTS0_MARK,	SD1_DAT3_B_MARK,
    389	HRTS0_A_MARK,	RTS0_MARK,	SSI_SCK4_MARK,
    390	DU0_DR0_MARK,	LCDOUT0_MARK,	AUDATA2_MARK,	ARM_TRACEDATA_2_MARK,
    391	SDA3_C_MARK,	ADICHS1_MARK,	TS_SDEN0_B_MARK,
    392	SSI_WS4_MARK,	DU0_DR1_MARK,	LCDOUT1_MARK,	AUDATA3_MARK,
    393	ARM_TRACEDATA_3_MARK,		SCL3_C_MARK,	ADICHS2_MARK,
    394	TS_SPSYNC0_B_MARK,		DU0_DR2_MARK,	LCDOUT2_MARK,
    395	DU0_DR3_MARK,	LCDOUT3_MARK,	DU0_DR4_MARK,	LCDOUT4_MARK,
    396	DU0_DR5_MARK,	LCDOUT5_MARK,	DU0_DR6_MARK,	LCDOUT6_MARK,
    397
    398	/* IPSR4 */
    399	DU0_DR7_MARK,	LCDOUT7_MARK,	DU0_DG0_MARK,	LCDOUT8_MARK,
    400	AUDATA4_MARK,	ARM_TRACEDATA_4_MARK,
    401	TX1_D_MARK,	CAN0_TX_A_MARK,	ADICHS0_MARK,	DU0_DG1_MARK,
    402	LCDOUT9_MARK,	AUDATA5_MARK,	ARM_TRACEDATA_5_MARK,
    403	RX1_D_MARK,	CAN0_RX_A_MARK,	ADIDATA_MARK,	DU0_DG2_MARK,
    404	LCDOUT10_MARK,	DU0_DG3_MARK,	LCDOUT11_MARK,	DU0_DG4_MARK,
    405	LCDOUT12_MARK,	RX0_B_MARK,	DU0_DG5_MARK,	LCDOUT13_MARK,
    406	TX0_B_MARK,	DU0_DG6_MARK,	LCDOUT14_MARK,	RX4_A_MARK,
    407	DU0_DG7_MARK,	LCDOUT15_MARK,	TX4_A_MARK,	SSI_SCK2_B_MARK,
    408	VI0_R0_B_MARK,	DU0_DB0_MARK,	LCDOUT16_MARK,	AUDATA6_MARK,
    409	ARM_TRACEDATA_6_MARK,		GPSCLK_A_MARK,	PWM0_A_MARK,
    410	ADICLK_MARK,	TS_SDAT0_B_MARK,		AUDIO_CLKC_MARK,
    411	VI0_R1_B_MARK,	DU0_DB1_MARK,	LCDOUT17_MARK,	AUDATA7_MARK,
    412	ARM_TRACEDATA_7_MARK,		GPSIN_A_MARK,	ADICS_SAMP_MARK,
    413	TS_SCK0_B_MARK,	VI0_R2_B_MARK,	DU0_DB2_MARK,	LCDOUT18_MARK,
    414	VI0_R3_B_MARK,	DU0_DB3_MARK,	LCDOUT19_MARK,	VI0_R4_B_MARK,
    415	DU0_DB4_MARK,	LCDOUT20_MARK,
    416
    417	/* IPSR5 */
    418	VI0_R5_B_MARK,	DU0_DB5_MARK,	LCDOUT21_MARK,	VI1_DATA10_B_MARK,
    419	DU0_DB6_MARK,	LCDOUT22_MARK,	VI1_DATA11_B_MARK,
    420	DU0_DB7_MARK,	LCDOUT23_MARK,	DU0_DOTCLKIN_MARK,
    421	QSTVA_QVS_MARK,	DU0_DOTCLKO_UT0_MARK,
    422	QCLK_MARK,	DU0_DOTCLKO_UT1_MARK,		QSTVB_QVE_MARK,
    423	AUDIO_CLKOUT_A_MARK,		REMOCON_C_MARK,	SSI_WS2_B_MARK,
    424	DU0_EXHSYNC_DU0_HSYNC_MARK,	QSTH_QHS_MARK,
    425	DU0_EXVSYNC_DU0_VSYNC_MARK,	QSTB_QHE_MARK,
    426	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
    427	QCPV_QDE_MARK,	FMCLK_D_MARK,	SSI_SCK1_A_MARK,
    428	DU0_DISP_MARK,	QPOLA_MARK,	AUDCK_MARK,	ARM_TRACECLK_MARK,
    429	BPFCLK_D_MARK,	SSI_WS1_A_MARK,	DU0_CDE_MARK,	QPOLB_MARK,
    430	AUDSYNC_MARK,	ARM_TRACECTL_MARK,		FMIN_D_MARK,
    431	SD1_CD_B_MARK,	SSI_SCK78_MARK,	HSPI_RX0_B_MARK,
    432	TX1_B_MARK,	SD1_WP_B_MARK,	SSI_WS78_MARK,	HSPI_CLK0_B_MARK,
    433	RX1_B_MARK,	CAN_CLK_D_MARK,	SSI_SDATA8_MARK,
    434	SSI_SCK2_A_MARK,		HSPI_CS0_B_MARK,
    435	TX2_A_MARK,	CAN0_TX_B_MARK,	SSI_SDATA7_MARK,
    436	HSPI_TX0_B_MARK,		RX2_A_MARK,	CAN0_RX_B_MARK,
    437
    438	/* IPSR6 */
    439	SSI_SCK6_MARK,	HSPI_RX2_A_MARK,		FMCLK_B_MARK,
    440	CAN1_TX_B_MARK,	SSI_WS6_MARK,	HSPI_CLK2_A_MARK,
    441	BPFCLK_B_MARK,	CAN1_RX_B_MARK,	SSI_SDATA6_MARK,
    442	HSPI_TX2_A_MARK,		FMIN_B_MARK,	SSI_SCK5_MARK,
    443	RX4_C_MARK,	SSI_WS5_MARK,	TX4_C_MARK,	SSI_SDATA5_MARK,
    444	RX0_D_MARK,	SSI_WS34_MARK,	ARM_TRACEDATA_8_MARK,
    445	SSI_SDATA4_MARK,		SSI_WS2_A_MARK,	ARM_TRACEDATA_9_MARK,
    446	SSI_SDATA3_MARK,		ARM_TRACEDATA_10_MARK,
    447	SSI_SCK012_MARK,		ARM_TRACEDATA_11_MARK,
    448	TX0_D_MARK,	SSI_WS012_MARK,	ARM_TRACEDATA_12_MARK,
    449	SSI_SDATA2_MARK,		HSPI_CS2_A_MARK,
    450	ARM_TRACEDATA_13_MARK,		SDA1_A_MARK,	SSI_SDATA1_MARK,
    451	ARM_TRACEDATA_14_MARK,		SCL1_A_MARK,	SCK2_A_MARK,
    452	SSI_SDATA0_MARK,		ARM_TRACEDATA_15_MARK,
    453	SD0_CLK_MARK,	SUB_TDO_MARK,	SD0_CMD_MARK,	SUB_TRST_MARK,
    454	SD0_DAT0_MARK,	SUB_TMS_MARK,	SD0_DAT1_MARK,	SUB_TCK_MARK,
    455	SD0_DAT2_MARK,	SUB_TDI_MARK,
    456
    457	/* IPSR7 */
    458	SD0_DAT3_MARK,	IRQ1_B_MARK,	SD0_CD_MARK,	TX5_A_MARK,
    459	SD0_WP_MARK,	RX5_A_MARK,	VI1_CLKENB_MARK,
    460	HSPI_CLK0_A_MARK,	HTX1_A_MARK,	RTS1_C_MARK,	VI1_FIELD_MARK,
    461	HSPI_CS0_A_MARK,	HRX1_A_MARK,	SCK1_C_MARK,	VI1_HSYNC_MARK,
    462	HSPI_RX0_A_MARK,	HRTS1_A_MARK,	FMCLK_A_MARK,	RX1_C_MARK,
    463	VI1_VSYNC_MARK,	HSPI_TX0_MARK,	HCTS1_A_MARK,	BPFCLK_A_MARK,
    464	TX1_C_MARK,	TCLK0_MARK,	HSCK1_A_MARK,	FMIN_A_MARK,
    465	IRQ2_C_MARK,	CTS1_C_MARK,	SPEEDIN_MARK,	VI0_CLK_MARK,
    466	CAN_CLK_A_MARK,	VI0_CLKENB_MARK,		SD2_DAT2_B_MARK,
    467	VI1_DATA0_MARK,	DU1_DG6_MARK,	HSPI_RX1_A_MARK,
    468	RX4_B_MARK,	VI0_FIELD_MARK,	SD2_DAT3_B_MARK,
    469	VI0_R3_C_MARK,	VI1_DATA1_MARK,	DU1_DG7_MARK,	HSPI_CLK1_A_MARK,
    470	TX4_B_MARK,	VI0_HSYNC_MARK,	SD2_CD_B_MARK,	VI1_DATA2_MARK,
    471	DU1_DR2_MARK,	HSPI_CS1_A_MARK,		RX3_B_MARK,
    472
    473	/* IPSR8 */
    474	VI0_VSYNC_MARK,	SD2_WP_B_MARK,	VI1_DATA3_MARK,	DU1_DR3_MARK,
    475	HSPI_TX1_A_MARK,		TX3_B_MARK,	VI0_DATA0_VI0_B0_MARK,
    476	DU1_DG2_MARK,	IRQ2_B_MARK,	RX3_D_MARK,	VI0_DATA1_VI0_B1_MARK,
    477	DU1_DG3_MARK,	IRQ3_B_MARK,	TX3_D_MARK,	VI0_DATA2_VI0_B2_MARK,
    478	DU1_DG4_MARK,	RX0_C_MARK,	VI0_DATA3_VI0_B3_MARK,
    479	DU1_DG5_MARK,	TX1_A_MARK,	TX0_C_MARK,	VI0_DATA4_VI0_B4_MARK,
    480	DU1_DB2_MARK,	RX1_A_MARK,	VI0_DATA5_VI0_B5_MARK,
    481	DU1_DB3_MARK,	SCK1_A_MARK,	PWM4_MARK,	HSCK1_B_MARK,
    482	VI0_DATA6_VI0_G0_MARK,		DU1_DB4_MARK,	CTS1_A_MARK,
    483	PWM5_MARK,	VI0_DATA7_VI0_G1_MARK,		DU1_DB5_MARK,
    484	RTS1_A_MARK,	VI0_G2_MARK,	SD2_CLK_B_MARK,	VI1_DATA4_MARK,
    485	DU1_DR4_MARK,	HTX1_B_MARK,	VI0_G3_MARK,	SD2_CMD_B_MARK,
    486	VI1_DATA5_MARK,	DU1_DR5_MARK,	HRX1_B_MARK,
    487
    488	/* IPSR9 */
    489	VI0_G4_MARK,	SD2_DAT0_B_MARK,		VI1_DATA6_MARK,
    490	DU1_DR6_MARK,	HRTS1_B_MARK,	VI0_G5_MARK,	SD2_DAT1_B_MARK,
    491	VI1_DATA7_MARK,	DU1_DR7_MARK,	HCTS1_B_MARK,	VI0_R0_A_MARK,
    492	VI1_CLK_MARK,	ETH_REF_CLK_MARK,		DU1_DOTCLKIN_MARK,
    493	VI0_R1_A_MARK,	VI1_DATA8_MARK,	DU1_DB6_MARK,	ETH_TXD0_MARK,
    494	PWM2_MARK,	TCLK1_MARK,	VI0_R2_A_MARK,	VI1_DATA9_MARK,
    495	DU1_DB7_MARK,	ETH_TXD1_MARK,	PWM3_MARK,	VI0_R3_A_MARK,
    496	ETH_CRS_DV_MARK,		IECLK_MARK,	SCK2_C_MARK,
    497	VI0_R4_A_MARK,			ETH_TX_EN_MARK,	IETX_MARK,
    498	TX2_C_MARK,	VI0_R5_A_MARK,	ETH_RX_ER_MARK,	FMCLK_C_MARK,
    499	IERX_MARK,	RX2_C_MARK,	VI1_DATA10_A_MARK,
    500	DU1_DOTCLKOUT_MARK,		ETH_RXD0_MARK,
    501	BPFCLK_C_MARK,	TX2_D_MARK,	SDA2_C_MARK,	VI1_DATA11_A_MARK,
    502	DU1_EXHSYNC_DU1_HSYNC_MARK,	ETH_RXD1_MARK,	FMIN_C_MARK,
    503	RX2_D_MARK,	SCL2_C_MARK,
    504
    505	/* IPSR10 */
    506	SD2_CLK_A_MARK,	DU1_EXVSYNC_DU1_VSYNC_MARK,	ATARD1_MARK,
    507	ETH_MDC_MARK,	SDA1_B_MARK,	SD2_CMD_A_MARK,
    508	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,		ATAWR1_MARK,
    509	ETH_MDIO_MARK,	SCL1_B_MARK,	SD2_DAT0_A_MARK,
    510	DU1_DISP_MARK,	ATACS01_MARK,	DREQ1_B_MARK,	ETH_LINK_MARK,
    511	CAN1_RX_A_MARK,	SD2_DAT1_A_MARK,		DU1_CDE_MARK,
    512	ATACS11_MARK,	DACK1_B_MARK,	ETH_MAGIC_MARK,	CAN1_TX_A_MARK,
    513	PWM6_MARK,	SD2_DAT2_A_MARK,		VI1_DATA12_MARK,
    514	DREQ2_B_MARK,	ATADIR1_MARK,	HSPI_CLK2_B_MARK,
    515	GPSCLK_B_MARK,	SD2_DAT3_A_MARK,		VI1_DATA13_MARK,
    516	DACK2_B_MARK,	ATAG1_MARK,	HSPI_CS2_B_MARK,
    517	GPSIN_B_MARK,	SD2_CD_A_MARK,	VI1_DATA14_MARK,
    518	EX_WAIT1_B_MARK,		DREQ0_B_MARK,	HSPI_RX2_B_MARK,
    519	REMOCON_A_MARK,	SD2_WP_A_MARK,	VI1_DATA15_MARK,
    520	EX_WAIT2_B_MARK,		DACK0_B_MARK,
    521	HSPI_TX2_B_MARK,		CAN_CLK_C_MARK,
    522
    523	PINMUX_MARK_END,
    524};
    525
    526static const u16 pinmux_data[] = {
    527	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
    528
    529	PINMUX_SINGLE(PENC0),
    530	PINMUX_SINGLE(PENC1),
    531	PINMUX_SINGLE(A1),
    532	PINMUX_SINGLE(A2),
    533	PINMUX_SINGLE(A3),
    534	PINMUX_SINGLE(WE0),
    535	PINMUX_SINGLE(AUDIO_CLKA),
    536	PINMUX_SINGLE(AUDIO_CLKB),
    537	PINMUX_SINGLE(SSI_SCK34),
    538	PINMUX_SINGLE(AVS1),
    539	PINMUX_SINGLE(AVS2),
    540
    541	/* IPSR0 */
    542	PINMUX_IPSR_GPSR(IP0_1_0,	PRESETOUT),
    543	PINMUX_IPSR_GPSR(IP0_1_0,	PWM1),
    544
    545	PINMUX_IPSR_GPSR(IP0_4_2,	AUDATA0),
    546	PINMUX_IPSR_GPSR(IP0_4_2,	ARM_TRACEDATA_0),
    547	PINMUX_IPSR_MSEL(IP0_4_2,	GPSCLK_C,	SEL_GPS_C),
    548	PINMUX_IPSR_GPSR(IP0_4_2,	USB_OVC0),
    549	PINMUX_IPSR_GPSR(IP0_4_2,	TX2_E),
    550	PINMUX_IPSR_MSEL(IP0_4_2,	SDA2_B,		SEL_I2C2_B),
    551
    552	PINMUX_IPSR_GPSR(IP0_7_5,	AUDATA1),
    553	PINMUX_IPSR_GPSR(IP0_7_5,	ARM_TRACEDATA_1),
    554	PINMUX_IPSR_MSEL(IP0_7_5,	GPSIN_C,	SEL_GPS_C),
    555	PINMUX_IPSR_GPSR(IP0_7_5,	USB_OVC1),
    556	PINMUX_IPSR_MSEL(IP0_7_5,	RX2_E,		SEL_SCIF2_E),
    557	PINMUX_IPSR_MSEL(IP0_7_5,	SCL2_B,		SEL_I2C2_B),
    558
    559	PINMUX_IPSR_MSEL(IP0_11_8,	SD1_DAT2_A,	SEL_SD1_A),
    560	PINMUX_IPSR_GPSR(IP0_11_8,	MMC_D2),
    561	PINMUX_IPSR_GPSR(IP0_11_8,	BS),
    562	PINMUX_IPSR_GPSR(IP0_11_8,	ATADIR0_A),
    563	PINMUX_IPSR_GPSR(IP0_11_8,	SDSELF_A),
    564	PINMUX_IPSR_GPSR(IP0_11_8,	PWM4_B),
    565
    566	PINMUX_IPSR_MSEL(IP0_14_12,	SD1_DAT3_A,	SEL_SD1_A),
    567	PINMUX_IPSR_GPSR(IP0_14_12,	MMC_D3),
    568	PINMUX_IPSR_GPSR(IP0_14_12,	A0),
    569	PINMUX_IPSR_GPSR(IP0_14_12,	ATAG0_A),
    570	PINMUX_IPSR_MSEL(IP0_14_12,	REMOCON_B,	SEL_REMOCON_B),
    571
    572	PINMUX_IPSR_GPSR(IP0_15,	A4),
    573	PINMUX_IPSR_GPSR(IP0_16,	A5),
    574	PINMUX_IPSR_GPSR(IP0_17,	A6),
    575	PINMUX_IPSR_GPSR(IP0_18,	A7),
    576	PINMUX_IPSR_GPSR(IP0_19,	A8),
    577	PINMUX_IPSR_GPSR(IP0_20,	A9),
    578	PINMUX_IPSR_GPSR(IP0_21,	A10),
    579	PINMUX_IPSR_GPSR(IP0_22,	A11),
    580	PINMUX_IPSR_GPSR(IP0_23,	A12),
    581	PINMUX_IPSR_GPSR(IP0_24,	A13),
    582	PINMUX_IPSR_GPSR(IP0_25,	A14),
    583	PINMUX_IPSR_GPSR(IP0_26,	A15),
    584	PINMUX_IPSR_GPSR(IP0_27,	A16),
    585	PINMUX_IPSR_GPSR(IP0_28,	A17),
    586	PINMUX_IPSR_GPSR(IP0_29,	A18),
    587	PINMUX_IPSR_GPSR(IP0_30,	A19),
    588
    589	/* IPSR1 */
    590	PINMUX_IPSR_GPSR(IP1_0,		A20),
    591	PINMUX_IPSR_MSEL(IP1_0,		HSPI_CS1_B,	SEL_HSPI1_B),
    592
    593	PINMUX_IPSR_GPSR(IP1_1,		A21),
    594	PINMUX_IPSR_MSEL(IP1_1,		HSPI_CLK1_B,	SEL_HSPI1_B),
    595
    596	PINMUX_IPSR_GPSR(IP1_4_2,	A22),
    597	PINMUX_IPSR_MSEL(IP1_4_2,	HRTS0_B,	SEL_HSCIF0_B),
    598	PINMUX_IPSR_MSEL(IP1_4_2,	RX2_B,		SEL_SCIF2_B),
    599	PINMUX_IPSR_MSEL(IP1_4_2,	DREQ2_A,	SEL_DREQ2_A),
    600
    601	PINMUX_IPSR_GPSR(IP1_7_5,	A23),
    602	PINMUX_IPSR_GPSR(IP1_7_5,	HTX0_B),
    603	PINMUX_IPSR_GPSR(IP1_7_5,	TX2_B),
    604	PINMUX_IPSR_GPSR(IP1_7_5,	DACK2_A),
    605	PINMUX_IPSR_MSEL(IP1_7_5,	TS_SDEN0_A,	SEL_TSIF0_A),
    606
    607	PINMUX_IPSR_MSEL(IP1_10_8,	SD1_CD_A,	SEL_SD1_A),
    608	PINMUX_IPSR_GPSR(IP1_10_8,	MMC_D6),
    609	PINMUX_IPSR_GPSR(IP1_10_8,	A24),
    610	PINMUX_IPSR_MSEL(IP1_10_8,	DREQ1_A,	SEL_DREQ1_A),
    611	PINMUX_IPSR_MSEL(IP1_10_8,	HRX0_B,		SEL_HSCIF0_B),
    612	PINMUX_IPSR_MSEL(IP1_10_8,	TS_SPSYNC0_A,	SEL_TSIF0_A),
    613
    614	PINMUX_IPSR_MSEL(IP1_14_11,	SD1_WP_A,	SEL_SD1_A),
    615	PINMUX_IPSR_GPSR(IP1_14_11,	MMC_D7),
    616	PINMUX_IPSR_GPSR(IP1_14_11,	A25),
    617	PINMUX_IPSR_GPSR(IP1_14_11,	DACK1_A),
    618	PINMUX_IPSR_MSEL(IP1_14_11,	HCTS0_B,	SEL_HSCIF0_B),
    619	PINMUX_IPSR_MSEL(IP1_14_11,	RX3_C,		SEL_SCIF3_C),
    620	PINMUX_IPSR_MSEL(IP1_14_11,	TS_SDAT0_A,	SEL_TSIF0_A),
    621
    622	PINMUX_IPSR_NOGP(IP1_16_15,	CLKOUT),
    623	PINMUX_IPSR_NOGP(IP1_16_15,	HSPI_TX1_B),
    624	PINMUX_IPSR_NOGP(IP1_16_15,	PWM0_B),
    625
    626	PINMUX_IPSR_NOGP(IP1_17,	CS0),
    627	PINMUX_IPSR_NOGM(IP1_17,	HSPI_RX1_B,	SEL_HSPI1_B),
    628
    629	PINMUX_IPSR_NOGM(IP1_20_18,	SSI_SCK1_B,	SEL_SSI1_B),
    630	PINMUX_IPSR_NOGP(IP1_20_18,	ATAG0_B),
    631	PINMUX_IPSR_NOGP(IP1_20_18,	CS1_A26),
    632	PINMUX_IPSR_NOGM(IP1_20_18,	SDA2_A,		SEL_I2C2_A),
    633	PINMUX_IPSR_NOGM(IP1_20_18,	SCK2_B,		SEL_SCIF2_B),
    634
    635	PINMUX_IPSR_GPSR(IP1_23_21,	MMC_D5),
    636	PINMUX_IPSR_GPSR(IP1_23_21,	ATADIR0_B),
    637	PINMUX_IPSR_GPSR(IP1_23_21,	RD_WR),
    638
    639	PINMUX_IPSR_GPSR(IP1_24,	WE1),
    640	PINMUX_IPSR_GPSR(IP1_24,	ATAWR0_B),
    641
    642	PINMUX_IPSR_MSEL(IP1_27_25,	SSI_WS1_B,	SEL_SSI1_B),
    643	PINMUX_IPSR_GPSR(IP1_27_25,	EX_CS0),
    644	PINMUX_IPSR_MSEL(IP1_27_25,	SCL2_A,		SEL_I2C2_A),
    645	PINMUX_IPSR_GPSR(IP1_27_25,	TX3_C),
    646	PINMUX_IPSR_MSEL(IP1_27_25,	TS_SCK0_A,	SEL_TSIF0_A),
    647
    648	PINMUX_IPSR_GPSR(IP1_29_28,	EX_CS1),
    649	PINMUX_IPSR_GPSR(IP1_29_28,	MMC_D4),
    650
    651	/* IPSR2 */
    652	PINMUX_IPSR_GPSR(IP2_2_0,	SD1_CLK_A),
    653	PINMUX_IPSR_GPSR(IP2_2_0,	MMC_CLK),
    654	PINMUX_IPSR_GPSR(IP2_2_0,	ATACS00),
    655	PINMUX_IPSR_GPSR(IP2_2_0,	EX_CS2),
    656
    657	PINMUX_IPSR_MSEL(IP2_5_3,	SD1_CMD_A,	SEL_SD1_A),
    658	PINMUX_IPSR_GPSR(IP2_5_3,	MMC_CMD),
    659	PINMUX_IPSR_GPSR(IP2_5_3,	ATACS10),
    660	PINMUX_IPSR_GPSR(IP2_5_3,	EX_CS3),
    661
    662	PINMUX_IPSR_MSEL(IP2_8_6,	SD1_DAT0_A,	SEL_SD1_A),
    663	PINMUX_IPSR_GPSR(IP2_8_6,	MMC_D0),
    664	PINMUX_IPSR_GPSR(IP2_8_6,	ATARD0),
    665	PINMUX_IPSR_GPSR(IP2_8_6,	EX_CS4),
    666	PINMUX_IPSR_MSEL(IP2_8_6,	EX_WAIT1_A,	SEL_WAIT1_A),
    667
    668	PINMUX_IPSR_MSEL(IP2_11_9,	SD1_DAT1_A,	SEL_SD1_A),
    669	PINMUX_IPSR_GPSR(IP2_11_9,	MMC_D1),
    670	PINMUX_IPSR_GPSR(IP2_11_9,	ATAWR0_A),
    671	PINMUX_IPSR_GPSR(IP2_11_9,	EX_CS5),
    672	PINMUX_IPSR_MSEL(IP2_11_9,	EX_WAIT2_A,	SEL_WAIT2_A),
    673
    674	PINMUX_IPSR_MSEL(IP2_13_12,	DREQ0_A,	SEL_DREQ0_A),
    675	PINMUX_IPSR_MSEL(IP2_13_12,	RX3_A,		SEL_SCIF3_A),
    676
    677	PINMUX_IPSR_GPSR(IP2_16_14,	DACK0),
    678	PINMUX_IPSR_GPSR(IP2_16_14,	TX3_A),
    679	PINMUX_IPSR_GPSR(IP2_16_14,	DRACK0),
    680
    681	PINMUX_IPSR_GPSR(IP2_17,	EX_WAIT0),
    682	PINMUX_IPSR_GPSR(IP2_17,	PWM0_C),
    683
    684	PINMUX_IPSR_NOGP(IP2_18,	D0),
    685	PINMUX_IPSR_NOGP(IP2_19,	D1),
    686	PINMUX_IPSR_NOGP(IP2_20,	D2),
    687	PINMUX_IPSR_NOGP(IP2_21,	D3),
    688	PINMUX_IPSR_NOGP(IP2_22,	D4),
    689	PINMUX_IPSR_NOGP(IP2_23,	D5),
    690	PINMUX_IPSR_NOGP(IP2_24,	D6),
    691	PINMUX_IPSR_NOGP(IP2_25,	D7),
    692	PINMUX_IPSR_NOGP(IP2_26,	D8),
    693	PINMUX_IPSR_NOGP(IP2_27,	D9),
    694	PINMUX_IPSR_NOGP(IP2_28,	D10),
    695	PINMUX_IPSR_NOGP(IP2_29,	D11),
    696
    697	PINMUX_IPSR_GPSR(IP2_30,	RD_WR_B),
    698	PINMUX_IPSR_GPSR(IP2_30,	IRQ0),
    699
    700	PINMUX_IPSR_GPSR(IP2_31,	MLB_CLK),
    701	PINMUX_IPSR_MSEL(IP2_31,	IRQ1_A,		SEL_IRQ1_A),
    702
    703	/* IPSR3 */
    704	PINMUX_IPSR_GPSR(IP3_1_0,	MLB_SIG),
    705	PINMUX_IPSR_MSEL(IP3_1_0,	RX5_B,		SEL_SCIF5_B),
    706	PINMUX_IPSR_MSEL(IP3_1_0,	SDA3_A,		SEL_I2C3_A),
    707	PINMUX_IPSR_MSEL(IP3_1_0,	IRQ2_A,		SEL_IRQ2_A),
    708
    709	PINMUX_IPSR_GPSR(IP3_4_2,	MLB_DAT),
    710	PINMUX_IPSR_GPSR(IP3_4_2,	TX5_B),
    711	PINMUX_IPSR_MSEL(IP3_4_2,	SCL3_A,		SEL_I2C3_A),
    712	PINMUX_IPSR_MSEL(IP3_4_2,	IRQ3_A,		SEL_IRQ3_A),
    713	PINMUX_IPSR_GPSR(IP3_4_2,	SDSELF_B),
    714
    715	PINMUX_IPSR_MSEL(IP3_7_5,	SD1_CMD_B,	SEL_SD1_B),
    716	PINMUX_IPSR_GPSR(IP3_7_5,	SCIF_CLK),
    717	PINMUX_IPSR_GPSR(IP3_7_5,	AUDIO_CLKOUT_B),
    718	PINMUX_IPSR_MSEL(IP3_7_5,	CAN_CLK_B,	SEL_CANCLK_B),
    719	PINMUX_IPSR_MSEL(IP3_7_5,	SDA3_B,		SEL_I2C3_B),
    720
    721	PINMUX_IPSR_GPSR(IP3_9_8,	SD1_CLK_B),
    722	PINMUX_IPSR_GPSR(IP3_9_8,	HTX0_A),
    723	PINMUX_IPSR_GPSR(IP3_9_8,	TX0_A),
    724
    725	PINMUX_IPSR_MSEL(IP3_12_10,	SD1_DAT0_B,	SEL_SD1_B),
    726	PINMUX_IPSR_MSEL(IP3_12_10,	HRX0_A,		SEL_HSCIF0_A),
    727	PINMUX_IPSR_MSEL(IP3_12_10,	RX0_A,		SEL_SCIF0_A),
    728
    729	PINMUX_IPSR_MSEL(IP3_15_13,	SD1_DAT1_B,	SEL_SD1_B),
    730	PINMUX_IPSR_MSEL(IP3_15_13,	HSCK0,		SEL_HSCIF0_A),
    731	PINMUX_IPSR_GPSR(IP3_15_13,	SCK0),
    732	PINMUX_IPSR_MSEL(IP3_15_13,	SCL3_B,		SEL_I2C3_B),
    733
    734	PINMUX_IPSR_MSEL(IP3_18_16,	SD1_DAT2_B,	SEL_SD1_B),
    735	PINMUX_IPSR_MSEL(IP3_18_16,	HCTS0_A,	SEL_HSCIF0_A),
    736	PINMUX_IPSR_GPSR(IP3_18_16,	CTS0),
    737
    738	PINMUX_IPSR_MSEL(IP3_20_19,	SD1_DAT3_B,	SEL_SD1_B),
    739	PINMUX_IPSR_MSEL(IP3_20_19,	HRTS0_A,	SEL_HSCIF0_A),
    740	PINMUX_IPSR_GPSR(IP3_20_19,	RTS0),
    741
    742	PINMUX_IPSR_GPSR(IP3_23_21,	SSI_SCK4),
    743	PINMUX_IPSR_GPSR(IP3_23_21,	DU0_DR0),
    744	PINMUX_IPSR_GPSR(IP3_23_21,	LCDOUT0),
    745	PINMUX_IPSR_GPSR(IP3_23_21,	AUDATA2),
    746	PINMUX_IPSR_GPSR(IP3_23_21,	ARM_TRACEDATA_2),
    747	PINMUX_IPSR_MSEL(IP3_23_21,	SDA3_C,		SEL_I2C3_C),
    748	PINMUX_IPSR_GPSR(IP3_23_21,	ADICHS1),
    749	PINMUX_IPSR_MSEL(IP3_23_21,	TS_SDEN0_B,	SEL_TSIF0_B),
    750
    751	PINMUX_IPSR_GPSR(IP3_26_24,	SSI_WS4),
    752	PINMUX_IPSR_GPSR(IP3_26_24,	DU0_DR1),
    753	PINMUX_IPSR_GPSR(IP3_26_24,	LCDOUT1),
    754	PINMUX_IPSR_GPSR(IP3_26_24,	AUDATA3),
    755	PINMUX_IPSR_GPSR(IP3_26_24,	ARM_TRACEDATA_3),
    756	PINMUX_IPSR_MSEL(IP3_26_24,	SCL3_C,		SEL_I2C3_C),
    757	PINMUX_IPSR_GPSR(IP3_26_24,	ADICHS2),
    758	PINMUX_IPSR_MSEL(IP3_26_24,	TS_SPSYNC0_B,	SEL_TSIF0_B),
    759
    760	PINMUX_IPSR_GPSR(IP3_27,	DU0_DR2),
    761	PINMUX_IPSR_GPSR(IP3_27,	LCDOUT2),
    762
    763	PINMUX_IPSR_GPSR(IP3_28,	DU0_DR3),
    764	PINMUX_IPSR_GPSR(IP3_28,	LCDOUT3),
    765
    766	PINMUX_IPSR_GPSR(IP3_29,	DU0_DR4),
    767	PINMUX_IPSR_GPSR(IP3_29,	LCDOUT4),
    768
    769	PINMUX_IPSR_GPSR(IP3_30,	DU0_DR5),
    770	PINMUX_IPSR_GPSR(IP3_30,	LCDOUT5),
    771
    772	PINMUX_IPSR_GPSR(IP3_31,	DU0_DR6),
    773	PINMUX_IPSR_GPSR(IP3_31,	LCDOUT6),
    774
    775	/* IPSR4 */
    776	PINMUX_IPSR_GPSR(IP4_0,		DU0_DR7),
    777	PINMUX_IPSR_GPSR(IP4_0,		LCDOUT7),
    778
    779	PINMUX_IPSR_GPSR(IP4_3_1,	DU0_DG0),
    780	PINMUX_IPSR_GPSR(IP4_3_1,	LCDOUT8),
    781	PINMUX_IPSR_GPSR(IP4_3_1,	AUDATA4),
    782	PINMUX_IPSR_GPSR(IP4_3_1,	ARM_TRACEDATA_4),
    783	PINMUX_IPSR_GPSR(IP4_3_1,	TX1_D),
    784	PINMUX_IPSR_GPSR(IP4_3_1,	CAN0_TX_A),
    785	PINMUX_IPSR_GPSR(IP4_3_1,	ADICHS0),
    786
    787	PINMUX_IPSR_GPSR(IP4_6_4,	DU0_DG1),
    788	PINMUX_IPSR_GPSR(IP4_6_4,	LCDOUT9),
    789	PINMUX_IPSR_GPSR(IP4_6_4,	AUDATA5),
    790	PINMUX_IPSR_GPSR(IP4_6_4,	ARM_TRACEDATA_5),
    791	PINMUX_IPSR_MSEL(IP4_6_4,	RX1_D,		SEL_SCIF1_D),
    792	PINMUX_IPSR_MSEL(IP4_6_4,	CAN0_RX_A,	SEL_CAN0_A),
    793	PINMUX_IPSR_GPSR(IP4_6_4,	ADIDATA),
    794
    795	PINMUX_IPSR_GPSR(IP4_7,		DU0_DG2),
    796	PINMUX_IPSR_GPSR(IP4_7,		LCDOUT10),
    797
    798	PINMUX_IPSR_GPSR(IP4_8,		DU0_DG3),
    799	PINMUX_IPSR_GPSR(IP4_8,		LCDOUT11),
    800
    801	PINMUX_IPSR_GPSR(IP4_10_9,	DU0_DG4),
    802	PINMUX_IPSR_GPSR(IP4_10_9,	LCDOUT12),
    803	PINMUX_IPSR_MSEL(IP4_10_9,	RX0_B,		SEL_SCIF0_B),
    804
    805	PINMUX_IPSR_GPSR(IP4_12_11,	DU0_DG5),
    806	PINMUX_IPSR_GPSR(IP4_12_11,	LCDOUT13),
    807	PINMUX_IPSR_GPSR(IP4_12_11,	TX0_B),
    808
    809	PINMUX_IPSR_GPSR(IP4_14_13,	DU0_DG6),
    810	PINMUX_IPSR_GPSR(IP4_14_13,	LCDOUT14),
    811	PINMUX_IPSR_MSEL(IP4_14_13,	RX4_A,		SEL_SCIF4_A),
    812
    813	PINMUX_IPSR_GPSR(IP4_16_15,	DU0_DG7),
    814	PINMUX_IPSR_GPSR(IP4_16_15,	LCDOUT15),
    815	PINMUX_IPSR_GPSR(IP4_16_15,	TX4_A),
    816
    817	PINMUX_IPSR_MSEL(IP4_20_17,	SSI_SCK2_B,	SEL_SSI2_B),
    818	PINMUX_DATA(VI0_R0_B_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_B), /* see sel_vi0 */
    819	PINMUX_DATA(VI0_R0_D_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_D), /* see sel_vi0 */
    820	PINMUX_IPSR_GPSR(IP4_20_17,	DU0_DB0),
    821	PINMUX_IPSR_GPSR(IP4_20_17,	LCDOUT16),
    822	PINMUX_IPSR_GPSR(IP4_20_17,	AUDATA6),
    823	PINMUX_IPSR_GPSR(IP4_20_17,	ARM_TRACEDATA_6),
    824	PINMUX_IPSR_MSEL(IP4_20_17,	GPSCLK_A,	SEL_GPS_A),
    825	PINMUX_IPSR_GPSR(IP4_20_17,	PWM0_A),
    826	PINMUX_IPSR_GPSR(IP4_20_17,	ADICLK),
    827	PINMUX_IPSR_MSEL(IP4_20_17,	TS_SDAT0_B,	SEL_TSIF0_B),
    828
    829	PINMUX_IPSR_GPSR(IP4_24_21,	AUDIO_CLKC),
    830	PINMUX_DATA(VI0_R1_B_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_B), /* see sel_vi0 */
    831	PINMUX_DATA(VI0_R1_D_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_D), /* see sel_vi0 */
    832	PINMUX_IPSR_GPSR(IP4_24_21,	DU0_DB1),
    833	PINMUX_IPSR_GPSR(IP4_24_21,	LCDOUT17),
    834	PINMUX_IPSR_GPSR(IP4_24_21,	AUDATA7),
    835	PINMUX_IPSR_GPSR(IP4_24_21,	ARM_TRACEDATA_7),
    836	PINMUX_IPSR_MSEL(IP4_24_21,	GPSIN_A,	SEL_GPS_A),
    837	PINMUX_IPSR_GPSR(IP4_24_21,	ADICS_SAMP),
    838	PINMUX_IPSR_MSEL(IP4_24_21,	TS_SCK0_B,	SEL_TSIF0_B),
    839
    840	PINMUX_DATA(VI0_R2_B_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_B), /* see sel_vi0 */
    841	PINMUX_DATA(VI0_R2_D_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_D), /* see sel_vi0 */
    842	PINMUX_IPSR_GPSR(IP4_26_25,	DU0_DB2),
    843	PINMUX_IPSR_GPSR(IP4_26_25,	LCDOUT18),
    844
    845	PINMUX_IPSR_MSEL(IP4_28_27,	VI0_R3_B,	SEL_VI0_B),
    846	PINMUX_IPSR_GPSR(IP4_28_27,	DU0_DB3),
    847	PINMUX_IPSR_GPSR(IP4_28_27,	LCDOUT19),
    848
    849	PINMUX_DATA(VI0_R4_B_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_B), /* see sel_vi0 */
    850	PINMUX_DATA(VI0_R4_D_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_D), /* see sel_vi0 */
    851	PINMUX_IPSR_GPSR(IP4_30_29,	DU0_DB4),
    852	PINMUX_IPSR_GPSR(IP4_30_29,	LCDOUT20),
    853
    854	/* IPSR5 */
    855	PINMUX_DATA(VI0_R5_B_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_B), /* see sel_vi0 */
    856	PINMUX_DATA(VI0_R5_D_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_D), /* see sel_vi0 */
    857	PINMUX_IPSR_GPSR(IP5_1_0,	DU0_DB5),
    858	PINMUX_IPSR_GPSR(IP5_1_0,	LCDOUT21),
    859
    860	PINMUX_IPSR_MSEL(IP5_3_2,	VI1_DATA10_B,	SEL_VI1_B),
    861	PINMUX_IPSR_GPSR(IP5_3_2,	DU0_DB6),
    862	PINMUX_IPSR_GPSR(IP5_3_2,	LCDOUT22),
    863
    864	PINMUX_IPSR_MSEL(IP5_5_4,	VI1_DATA11_B,	SEL_VI1_B),
    865	PINMUX_IPSR_GPSR(IP5_5_4,	DU0_DB7),
    866	PINMUX_IPSR_GPSR(IP5_5_4,	LCDOUT23),
    867
    868	PINMUX_IPSR_GPSR(IP5_6,		DU0_DOTCLKIN),
    869	PINMUX_IPSR_GPSR(IP5_6,		QSTVA_QVS),
    870
    871	PINMUX_IPSR_GPSR(IP5_7,		DU0_DOTCLKO_UT0),
    872	PINMUX_IPSR_GPSR(IP5_7,		QCLK),
    873
    874	PINMUX_IPSR_GPSR(IP5_9_8,	DU0_DOTCLKO_UT1),
    875	PINMUX_IPSR_GPSR(IP5_9_8,	QSTVB_QVE),
    876	PINMUX_IPSR_GPSR(IP5_9_8,	AUDIO_CLKOUT_A),
    877	PINMUX_IPSR_MSEL(IP5_9_8,	REMOCON_C,	SEL_REMOCON_C),
    878
    879	PINMUX_IPSR_MSEL(IP5_11_10,	SSI_WS2_B,	SEL_SSI2_B),
    880	PINMUX_IPSR_GPSR(IP5_11_10,	DU0_EXHSYNC_DU0_HSYNC),
    881	PINMUX_IPSR_GPSR(IP5_11_10,	QSTH_QHS),
    882
    883	PINMUX_IPSR_GPSR(IP5_12,	DU0_EXVSYNC_DU0_VSYNC),
    884	PINMUX_IPSR_GPSR(IP5_12,	QSTB_QHE),
    885
    886	PINMUX_IPSR_GPSR(IP5_14_13,	DU0_EXODDF_DU0_ODDF_DISP_CDE),
    887	PINMUX_IPSR_GPSR(IP5_14_13,	QCPV_QDE),
    888	PINMUX_IPSR_MSEL(IP5_14_13,	FMCLK_D,	SEL_FM_D),
    889
    890	PINMUX_IPSR_MSEL(IP5_17_15,	SSI_SCK1_A,	SEL_SSI1_A),
    891	PINMUX_IPSR_GPSR(IP5_17_15,	DU0_DISP),
    892	PINMUX_IPSR_GPSR(IP5_17_15,	QPOLA),
    893	PINMUX_IPSR_GPSR(IP5_17_15,	AUDCK),
    894	PINMUX_IPSR_GPSR(IP5_17_15,	ARM_TRACECLK),
    895	PINMUX_IPSR_GPSR(IP5_17_15,	BPFCLK_D),
    896
    897	PINMUX_IPSR_MSEL(IP5_20_18,	SSI_WS1_A,	SEL_SSI1_A),
    898	PINMUX_IPSR_GPSR(IP5_20_18,	DU0_CDE),
    899	PINMUX_IPSR_GPSR(IP5_20_18,	QPOLB),
    900	PINMUX_IPSR_GPSR(IP5_20_18,	AUDSYNC),
    901	PINMUX_IPSR_GPSR(IP5_20_18,	ARM_TRACECTL),
    902	PINMUX_IPSR_MSEL(IP5_20_18,	FMIN_D,		SEL_FM_D),
    903
    904	PINMUX_IPSR_MSEL(IP5_22_21,	SD1_CD_B,	SEL_SD1_B),
    905	PINMUX_IPSR_GPSR(IP5_22_21,	SSI_SCK78),
    906	PINMUX_IPSR_MSEL(IP5_22_21,	HSPI_RX0_B,	SEL_HSPI0_B),
    907	PINMUX_IPSR_GPSR(IP5_22_21,	TX1_B),
    908
    909	PINMUX_IPSR_MSEL(IP5_25_23,	SD1_WP_B,	SEL_SD1_B),
    910	PINMUX_IPSR_GPSR(IP5_25_23,	SSI_WS78),
    911	PINMUX_IPSR_MSEL(IP5_25_23,	HSPI_CLK0_B,	SEL_HSPI0_B),
    912	PINMUX_IPSR_MSEL(IP5_25_23,	RX1_B,		SEL_SCIF1_B),
    913	PINMUX_IPSR_MSEL(IP5_25_23,	CAN_CLK_D,	SEL_CANCLK_D),
    914
    915	PINMUX_IPSR_GPSR(IP5_28_26,	SSI_SDATA8),
    916	PINMUX_IPSR_MSEL(IP5_28_26,	SSI_SCK2_A,	SEL_SSI2_A),
    917	PINMUX_IPSR_MSEL(IP5_28_26,	HSPI_CS0_B,	SEL_HSPI0_B),
    918	PINMUX_IPSR_GPSR(IP5_28_26,	TX2_A),
    919	PINMUX_IPSR_GPSR(IP5_28_26,	CAN0_TX_B),
    920
    921	PINMUX_IPSR_GPSR(IP5_30_29,	SSI_SDATA7),
    922	PINMUX_IPSR_GPSR(IP5_30_29,	HSPI_TX0_B),
    923	PINMUX_IPSR_MSEL(IP5_30_29,	RX2_A,		SEL_SCIF2_A),
    924	PINMUX_IPSR_MSEL(IP5_30_29,	CAN0_RX_B,	SEL_CAN0_B),
    925
    926	/* IPSR6 */
    927	PINMUX_IPSR_GPSR(IP6_1_0,	SSI_SCK6),
    928	PINMUX_IPSR_MSEL(IP6_1_0,	HSPI_RX2_A,	SEL_HSPI2_A),
    929	PINMUX_IPSR_MSEL(IP6_1_0,	FMCLK_B,	SEL_FM_B),
    930	PINMUX_IPSR_GPSR(IP6_1_0,	CAN1_TX_B),
    931
    932	PINMUX_IPSR_GPSR(IP6_4_2,	SSI_WS6),
    933	PINMUX_IPSR_MSEL(IP6_4_2,	HSPI_CLK2_A,	SEL_HSPI2_A),
    934	PINMUX_IPSR_GPSR(IP6_4_2,	BPFCLK_B),
    935	PINMUX_IPSR_MSEL(IP6_4_2,	CAN1_RX_B,	SEL_CAN1_B),
    936
    937	PINMUX_IPSR_GPSR(IP6_6_5,	SSI_SDATA6),
    938	PINMUX_IPSR_GPSR(IP6_6_5,	HSPI_TX2_A),
    939	PINMUX_IPSR_MSEL(IP6_6_5,	FMIN_B,		SEL_FM_B),
    940
    941	PINMUX_IPSR_GPSR(IP6_7,		SSI_SCK5),
    942	PINMUX_IPSR_MSEL(IP6_7,		RX4_C,		SEL_SCIF4_C),
    943
    944	PINMUX_IPSR_GPSR(IP6_8,		SSI_WS5),
    945	PINMUX_IPSR_GPSR(IP6_8,		TX4_C),
    946
    947	PINMUX_IPSR_GPSR(IP6_9,		SSI_SDATA5),
    948	PINMUX_IPSR_MSEL(IP6_9,		RX0_D,		SEL_SCIF0_D),
    949
    950	PINMUX_IPSR_GPSR(IP6_10,	SSI_WS34),
    951	PINMUX_IPSR_GPSR(IP6_10,	ARM_TRACEDATA_8),
    952
    953	PINMUX_IPSR_GPSR(IP6_12_11,	SSI_SDATA4),
    954	PINMUX_IPSR_MSEL(IP6_12_11,	SSI_WS2_A,	SEL_SSI2_A),
    955	PINMUX_IPSR_GPSR(IP6_12_11,	ARM_TRACEDATA_9),
    956
    957	PINMUX_IPSR_GPSR(IP6_13,	SSI_SDATA3),
    958	PINMUX_IPSR_GPSR(IP6_13,	ARM_TRACEDATA_10),
    959
    960	PINMUX_IPSR_GPSR(IP6_15_14,	SSI_SCK012),
    961	PINMUX_IPSR_GPSR(IP6_15_14,	ARM_TRACEDATA_11),
    962	PINMUX_IPSR_GPSR(IP6_15_14,	TX0_D),
    963
    964	PINMUX_IPSR_GPSR(IP6_16,	SSI_WS012),
    965	PINMUX_IPSR_GPSR(IP6_16,	ARM_TRACEDATA_12),
    966
    967	PINMUX_IPSR_GPSR(IP6_18_17,	SSI_SDATA2),
    968	PINMUX_IPSR_MSEL(IP6_18_17,	HSPI_CS2_A,	SEL_HSPI2_A),
    969	PINMUX_IPSR_GPSR(IP6_18_17,	ARM_TRACEDATA_13),
    970	PINMUX_IPSR_MSEL(IP6_18_17,	SDA1_A,		SEL_I2C1_A),
    971
    972	PINMUX_IPSR_GPSR(IP6_20_19,	SSI_SDATA1),
    973	PINMUX_IPSR_GPSR(IP6_20_19,	ARM_TRACEDATA_14),
    974	PINMUX_IPSR_MSEL(IP6_20_19,	SCL1_A,		SEL_I2C1_A),
    975	PINMUX_IPSR_MSEL(IP6_20_19,	SCK2_A,		SEL_SCIF2_A),
    976
    977	PINMUX_IPSR_GPSR(IP6_21,	SSI_SDATA0),
    978	PINMUX_IPSR_GPSR(IP6_21,	ARM_TRACEDATA_15),
    979
    980	PINMUX_IPSR_GPSR(IP6_23_22,	SD0_CLK),
    981	PINMUX_IPSR_GPSR(IP6_23_22,	SUB_TDO),
    982
    983	PINMUX_IPSR_GPSR(IP6_25_24,	SD0_CMD),
    984	PINMUX_IPSR_GPSR(IP6_25_24,	SUB_TRST),
    985
    986	PINMUX_IPSR_GPSR(IP6_27_26,	SD0_DAT0),
    987	PINMUX_IPSR_GPSR(IP6_27_26,	SUB_TMS),
    988
    989	PINMUX_IPSR_GPSR(IP6_29_28,	SD0_DAT1),
    990	PINMUX_IPSR_GPSR(IP6_29_28,	SUB_TCK),
    991
    992	PINMUX_IPSR_GPSR(IP6_31_30,	SD0_DAT2),
    993	PINMUX_IPSR_GPSR(IP6_31_30,	SUB_TDI),
    994
    995	/* IPSR7 */
    996	PINMUX_IPSR_GPSR(IP7_1_0,	SD0_DAT3),
    997	PINMUX_IPSR_MSEL(IP7_1_0,	IRQ1_B,		SEL_IRQ1_B),
    998
    999	PINMUX_IPSR_GPSR(IP7_3_2,	SD0_CD),
   1000	PINMUX_IPSR_GPSR(IP7_3_2,	TX5_A),
   1001
   1002	PINMUX_IPSR_GPSR(IP7_5_4,	SD0_WP),
   1003	PINMUX_IPSR_MSEL(IP7_5_4,	RX5_A,		SEL_SCIF5_A),
   1004
   1005	PINMUX_IPSR_GPSR(IP7_8_6,	VI1_CLKENB),
   1006	PINMUX_IPSR_MSEL(IP7_8_6,	HSPI_CLK0_A,	SEL_HSPI0_A),
   1007	PINMUX_IPSR_GPSR(IP7_8_6,	HTX1_A),
   1008	PINMUX_IPSR_MSEL(IP7_8_6,	RTS1_C,		SEL_SCIF1_C),
   1009
   1010	PINMUX_IPSR_GPSR(IP7_11_9,	VI1_FIELD),
   1011	PINMUX_IPSR_MSEL(IP7_11_9,	HSPI_CS0_A,	SEL_HSPI0_A),
   1012	PINMUX_IPSR_MSEL(IP7_11_9,	HRX1_A,		SEL_HSCIF1_A),
   1013	PINMUX_IPSR_MSEL(IP7_11_9,	SCK1_C,		SEL_SCIF1_C),
   1014
   1015	PINMUX_IPSR_GPSR(IP7_14_12,	VI1_HSYNC),
   1016	PINMUX_IPSR_MSEL(IP7_14_12,	HSPI_RX0_A,	SEL_HSPI0_A),
   1017	PINMUX_IPSR_MSEL(IP7_14_12,	HRTS1_A,	SEL_HSCIF1_A),
   1018	PINMUX_IPSR_MSEL(IP7_14_12,	FMCLK_A,	SEL_FM_A),
   1019	PINMUX_IPSR_MSEL(IP7_14_12,	RX1_C,		SEL_SCIF1_C),
   1020
   1021	PINMUX_IPSR_GPSR(IP7_17_15,	VI1_VSYNC),
   1022	PINMUX_IPSR_GPSR(IP7_17_15,	HSPI_TX0),
   1023	PINMUX_IPSR_MSEL(IP7_17_15,	HCTS1_A,	SEL_HSCIF1_A),
   1024	PINMUX_IPSR_GPSR(IP7_17_15,	BPFCLK_A),
   1025	PINMUX_IPSR_GPSR(IP7_17_15,	TX1_C),
   1026
   1027	PINMUX_IPSR_GPSR(IP7_20_18,	TCLK0),
   1028	PINMUX_IPSR_MSEL(IP7_20_18,	HSCK1_A,	SEL_HSCIF1_A),
   1029	PINMUX_IPSR_MSEL(IP7_20_18,	FMIN_A,		SEL_FM_A),
   1030	PINMUX_IPSR_MSEL(IP7_20_18,	IRQ2_C,		SEL_IRQ2_C),
   1031	PINMUX_IPSR_MSEL(IP7_20_18,	CTS1_C,		SEL_SCIF1_C),
   1032	PINMUX_IPSR_GPSR(IP7_20_18,	SPEEDIN),
   1033
   1034	PINMUX_IPSR_GPSR(IP7_21,	VI0_CLK),
   1035	PINMUX_IPSR_MSEL(IP7_21,	CAN_CLK_A,	SEL_CANCLK_A),
   1036
   1037	PINMUX_IPSR_GPSR(IP7_24_22,	VI0_CLKENB),
   1038	PINMUX_IPSR_MSEL(IP7_24_22,	SD2_DAT2_B,	SEL_SD2_B),
   1039	PINMUX_IPSR_GPSR(IP7_24_22,	VI1_DATA0),
   1040	PINMUX_IPSR_GPSR(IP7_24_22,	DU1_DG6),
   1041	PINMUX_IPSR_MSEL(IP7_24_22,	HSPI_RX1_A,	SEL_HSPI1_A),
   1042	PINMUX_IPSR_MSEL(IP7_24_22,	RX4_B,		SEL_SCIF4_B),
   1043
   1044	PINMUX_IPSR_GPSR(IP7_28_25,	VI0_FIELD),
   1045	PINMUX_IPSR_MSEL(IP7_28_25,	SD2_DAT3_B,	SEL_SD2_B),
   1046	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_C), /* see sel_vi0 */
   1047	PINMUX_DATA(VI0_R3_D_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_D), /* see sel_vi0 */
   1048	PINMUX_IPSR_GPSR(IP7_28_25,	VI1_DATA1),
   1049	PINMUX_IPSR_GPSR(IP7_28_25,	DU1_DG7),
   1050	PINMUX_IPSR_MSEL(IP7_28_25,	HSPI_CLK1_A,	SEL_HSPI1_A),
   1051	PINMUX_IPSR_GPSR(IP7_28_25,	TX4_B),
   1052
   1053	PINMUX_IPSR_GPSR(IP7_31_29,	VI0_HSYNC),
   1054	PINMUX_IPSR_MSEL(IP7_31_29,	SD2_CD_B,	SEL_SD2_B),
   1055	PINMUX_IPSR_GPSR(IP7_31_29,	VI1_DATA2),
   1056	PINMUX_IPSR_GPSR(IP7_31_29,	DU1_DR2),
   1057	PINMUX_IPSR_MSEL(IP7_31_29,	HSPI_CS1_A,	SEL_HSPI1_A),
   1058	PINMUX_IPSR_MSEL(IP7_31_29,	RX3_B,		SEL_SCIF3_B),
   1059
   1060	/* IPSR8 */
   1061	PINMUX_IPSR_GPSR(IP8_2_0,	VI0_VSYNC),
   1062	PINMUX_IPSR_MSEL(IP8_2_0,	SD2_WP_B,	SEL_SD2_B),
   1063	PINMUX_IPSR_GPSR(IP8_2_0,	VI1_DATA3),
   1064	PINMUX_IPSR_GPSR(IP8_2_0,	DU1_DR3),
   1065	PINMUX_IPSR_GPSR(IP8_2_0,	HSPI_TX1_A),
   1066	PINMUX_IPSR_GPSR(IP8_2_0,	TX3_B),
   1067
   1068	PINMUX_IPSR_GPSR(IP8_5_3,	VI0_DATA0_VI0_B0),
   1069	PINMUX_IPSR_GPSR(IP8_5_3,	DU1_DG2),
   1070	PINMUX_IPSR_MSEL(IP8_5_3,	IRQ2_B,		SEL_IRQ2_B),
   1071	PINMUX_IPSR_MSEL(IP8_5_3,	RX3_D,		SEL_SCIF3_D),
   1072
   1073	PINMUX_IPSR_GPSR(IP8_8_6,	VI0_DATA1_VI0_B1),
   1074	PINMUX_IPSR_GPSR(IP8_8_6,	DU1_DG3),
   1075	PINMUX_IPSR_MSEL(IP8_8_6,	IRQ3_B,		SEL_IRQ3_B),
   1076	PINMUX_IPSR_GPSR(IP8_8_6,	TX3_D),
   1077
   1078	PINMUX_IPSR_GPSR(IP8_10_9,	VI0_DATA2_VI0_B2),
   1079	PINMUX_IPSR_GPSR(IP8_10_9,	DU1_DG4),
   1080	PINMUX_IPSR_MSEL(IP8_10_9,	RX0_C,		SEL_SCIF0_C),
   1081
   1082	PINMUX_IPSR_GPSR(IP8_13_11,	VI0_DATA3_VI0_B3),
   1083	PINMUX_IPSR_GPSR(IP8_13_11,	DU1_DG5),
   1084	PINMUX_IPSR_GPSR(IP8_13_11,	TX1_A),
   1085	PINMUX_IPSR_GPSR(IP8_13_11,	TX0_C),
   1086
   1087	PINMUX_IPSR_GPSR(IP8_15_14,	VI0_DATA4_VI0_B4),
   1088	PINMUX_IPSR_GPSR(IP8_15_14,	DU1_DB2),
   1089	PINMUX_IPSR_MSEL(IP8_15_14,	RX1_A,		SEL_SCIF1_A),
   1090
   1091	PINMUX_IPSR_GPSR(IP8_18_16,	VI0_DATA5_VI0_B5),
   1092	PINMUX_IPSR_GPSR(IP8_18_16,	DU1_DB3),
   1093	PINMUX_IPSR_MSEL(IP8_18_16,	SCK1_A,		SEL_SCIF1_A),
   1094	PINMUX_IPSR_GPSR(IP8_18_16,	PWM4),
   1095	PINMUX_IPSR_MSEL(IP8_18_16,	HSCK1_B,	SEL_HSCIF1_B),
   1096
   1097	PINMUX_IPSR_GPSR(IP8_21_19,	VI0_DATA6_VI0_G0),
   1098	PINMUX_IPSR_GPSR(IP8_21_19,	DU1_DB4),
   1099	PINMUX_IPSR_MSEL(IP8_21_19,	CTS1_A,		SEL_SCIF1_A),
   1100	PINMUX_IPSR_GPSR(IP8_21_19,	PWM5),
   1101
   1102	PINMUX_IPSR_GPSR(IP8_23_22,	VI0_DATA7_VI0_G1),
   1103	PINMUX_IPSR_GPSR(IP8_23_22,	DU1_DB5),
   1104	PINMUX_IPSR_MSEL(IP8_23_22,	RTS1_A,		SEL_SCIF1_A),
   1105
   1106	PINMUX_IPSR_GPSR(IP8_26_24,	VI0_G2),
   1107	PINMUX_IPSR_GPSR(IP8_26_24,	SD2_CLK_B),
   1108	PINMUX_IPSR_GPSR(IP8_26_24,	VI1_DATA4),
   1109	PINMUX_IPSR_GPSR(IP8_26_24,	DU1_DR4),
   1110	PINMUX_IPSR_GPSR(IP8_26_24,	HTX1_B),
   1111
   1112	PINMUX_IPSR_GPSR(IP8_29_27,	VI0_G3),
   1113	PINMUX_IPSR_MSEL(IP8_29_27,	SD2_CMD_B,	SEL_SD2_B),
   1114	PINMUX_IPSR_GPSR(IP8_29_27,	VI1_DATA5),
   1115	PINMUX_IPSR_GPSR(IP8_29_27,	DU1_DR5),
   1116	PINMUX_IPSR_MSEL(IP8_29_27,	HRX1_B,		SEL_HSCIF1_B),
   1117
   1118	/* IPSR9 */
   1119	PINMUX_IPSR_GPSR(IP9_2_0,	VI0_G4),
   1120	PINMUX_IPSR_MSEL(IP9_2_0,	SD2_DAT0_B,	SEL_SD2_B),
   1121	PINMUX_IPSR_GPSR(IP9_2_0,	VI1_DATA6),
   1122	PINMUX_IPSR_GPSR(IP9_2_0,	DU1_DR6),
   1123	PINMUX_IPSR_MSEL(IP9_2_0,	HRTS1_B,	SEL_HSCIF1_B),
   1124
   1125	PINMUX_IPSR_GPSR(IP9_5_3,	VI0_G5),
   1126	PINMUX_IPSR_MSEL(IP9_5_3,	SD2_DAT1_B,	SEL_SD2_B),
   1127	PINMUX_IPSR_GPSR(IP9_5_3,	VI1_DATA7),
   1128	PINMUX_IPSR_GPSR(IP9_5_3,	DU1_DR7),
   1129	PINMUX_IPSR_MSEL(IP9_5_3,	HCTS1_B,	SEL_HSCIF1_B),
   1130
   1131	PINMUX_DATA(VI0_R0_A_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_A), /* see sel_vi0 */
   1132	PINMUX_DATA(VI0_R0_C_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_C), /* see sel_vi0 */
   1133	PINMUX_IPSR_GPSR(IP9_8_6,	VI1_CLK),
   1134	PINMUX_IPSR_GPSR(IP9_8_6,	ETH_REF_CLK),
   1135	PINMUX_IPSR_GPSR(IP9_8_6,	DU1_DOTCLKIN),
   1136
   1137	PINMUX_DATA(VI0_R1_A_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_A), /* see sel_vi0 */
   1138	PINMUX_DATA(VI0_R1_C_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_C), /* see sel_vi0 */
   1139	PINMUX_IPSR_GPSR(IP9_11_9,	VI1_DATA8),
   1140	PINMUX_IPSR_GPSR(IP9_11_9,	DU1_DB6),
   1141	PINMUX_IPSR_GPSR(IP9_11_9,	ETH_TXD0),
   1142	PINMUX_IPSR_GPSR(IP9_11_9,	PWM2),
   1143	PINMUX_IPSR_GPSR(IP9_11_9,	TCLK1),
   1144
   1145	PINMUX_DATA(VI0_R2_A_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_A), /* see sel_vi0 */
   1146	PINMUX_DATA(VI0_R2_C_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_C), /* see sel_vi0 */
   1147	PINMUX_IPSR_GPSR(IP9_14_12,	VI1_DATA9),
   1148	PINMUX_IPSR_GPSR(IP9_14_12,	DU1_DB7),
   1149	PINMUX_IPSR_GPSR(IP9_14_12,	ETH_TXD1),
   1150	PINMUX_IPSR_GPSR(IP9_14_12,	PWM3),
   1151
   1152	PINMUX_IPSR_MSEL(IP9_17_15,	VI0_R3_A,	SEL_VI0_A),
   1153	PINMUX_IPSR_GPSR(IP9_17_15,	ETH_CRS_DV),
   1154	PINMUX_IPSR_GPSR(IP9_17_15,	IECLK),
   1155	PINMUX_IPSR_MSEL(IP9_17_15,	SCK2_C,		SEL_SCIF2_C),
   1156
   1157	PINMUX_DATA(VI0_R4_A_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_A), /* see sel_vi0 */
   1158	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_C), /* see sel_vi0 */
   1159	PINMUX_IPSR_GPSR(IP9_20_18,	ETH_TX_EN),
   1160	PINMUX_IPSR_GPSR(IP9_20_18,	IETX),
   1161	PINMUX_IPSR_GPSR(IP9_20_18,	TX2_C),
   1162
   1163	PINMUX_DATA(VI0_R5_A_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_A), /* see sel_vi0 */
   1164	PINMUX_DATA(VI0_R5_C_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_C), /* see sel_vi0 */
   1165	PINMUX_IPSR_GPSR(IP9_23_21,	ETH_RX_ER),
   1166	PINMUX_IPSR_MSEL(IP9_23_21,	FMCLK_C,	SEL_FM_C),
   1167	PINMUX_IPSR_GPSR(IP9_23_21,	IERX),
   1168	PINMUX_IPSR_MSEL(IP9_23_21,	RX2_C,		SEL_SCIF2_C),
   1169
   1170	PINMUX_IPSR_MSEL(IP9_26_24,	VI1_DATA10_A,	SEL_VI1_A),
   1171	PINMUX_IPSR_GPSR(IP9_26_24,	DU1_DOTCLKOUT),
   1172	PINMUX_IPSR_GPSR(IP9_26_24,	ETH_RXD0),
   1173	PINMUX_IPSR_GPSR(IP9_26_24,	BPFCLK_C),
   1174	PINMUX_IPSR_GPSR(IP9_26_24,	TX2_D),
   1175	PINMUX_IPSR_MSEL(IP9_26_24,	SDA2_C,		SEL_I2C2_C),
   1176
   1177	PINMUX_IPSR_MSEL(IP9_29_27,	VI1_DATA11_A,	SEL_VI1_A),
   1178	PINMUX_IPSR_GPSR(IP9_29_27,	DU1_EXHSYNC_DU1_HSYNC),
   1179	PINMUX_IPSR_GPSR(IP9_29_27,	ETH_RXD1),
   1180	PINMUX_IPSR_MSEL(IP9_29_27,	FMIN_C,		SEL_FM_C),
   1181	PINMUX_IPSR_MSEL(IP9_29_27,	RX2_D,		SEL_SCIF2_D),
   1182	PINMUX_IPSR_MSEL(IP9_29_27,	SCL2_C,		SEL_I2C2_C),
   1183
   1184	/* IPSR10 */
   1185	PINMUX_IPSR_GPSR(IP10_2_0,	SD2_CLK_A),
   1186	PINMUX_IPSR_GPSR(IP10_2_0,	DU1_EXVSYNC_DU1_VSYNC),
   1187	PINMUX_IPSR_GPSR(IP10_2_0,	ATARD1),
   1188	PINMUX_IPSR_GPSR(IP10_2_0,	ETH_MDC),
   1189	PINMUX_IPSR_MSEL(IP10_2_0,	SDA1_B,		SEL_I2C1_B),
   1190
   1191	PINMUX_IPSR_MSEL(IP10_5_3,	SD2_CMD_A,	SEL_SD2_A),
   1192	PINMUX_IPSR_GPSR(IP10_5_3,	DU1_EXODDF_DU1_ODDF_DISP_CDE),
   1193	PINMUX_IPSR_GPSR(IP10_5_3,	ATAWR1),
   1194	PINMUX_IPSR_GPSR(IP10_5_3,	ETH_MDIO),
   1195	PINMUX_IPSR_MSEL(IP10_5_3,	SCL1_B,		SEL_I2C1_B),
   1196
   1197	PINMUX_IPSR_MSEL(IP10_8_6,	SD2_DAT0_A,	SEL_SD2_A),
   1198	PINMUX_IPSR_GPSR(IP10_8_6,	DU1_DISP),
   1199	PINMUX_IPSR_GPSR(IP10_8_6,	ATACS01),
   1200	PINMUX_IPSR_MSEL(IP10_8_6,	DREQ1_B,	SEL_DREQ1_B),
   1201	PINMUX_IPSR_GPSR(IP10_8_6,	ETH_LINK),
   1202	PINMUX_IPSR_MSEL(IP10_8_6,	CAN1_RX_A,	SEL_CAN1_A),
   1203
   1204	PINMUX_IPSR_MSEL(IP10_12_9,	SD2_DAT1_A,	SEL_SD2_A),
   1205	PINMUX_IPSR_GPSR(IP10_12_9,	DU1_CDE),
   1206	PINMUX_IPSR_GPSR(IP10_12_9,	ATACS11),
   1207	PINMUX_IPSR_GPSR(IP10_12_9,	DACK1_B),
   1208	PINMUX_IPSR_GPSR(IP10_12_9,	ETH_MAGIC),
   1209	PINMUX_IPSR_GPSR(IP10_12_9,	CAN1_TX_A),
   1210	PINMUX_IPSR_GPSR(IP10_12_9,	PWM6),
   1211
   1212	PINMUX_IPSR_MSEL(IP10_15_13,	SD2_DAT2_A,	SEL_SD2_A),
   1213	PINMUX_IPSR_GPSR(IP10_15_13,	VI1_DATA12),
   1214	PINMUX_IPSR_MSEL(IP10_15_13,	DREQ2_B,	SEL_DREQ2_B),
   1215	PINMUX_IPSR_GPSR(IP10_15_13,	ATADIR1),
   1216	PINMUX_IPSR_MSEL(IP10_15_13,	HSPI_CLK2_B,	SEL_HSPI2_B),
   1217	PINMUX_IPSR_MSEL(IP10_15_13,	GPSCLK_B,	SEL_GPS_B),
   1218
   1219	PINMUX_IPSR_MSEL(IP10_18_16,	SD2_DAT3_A,	SEL_SD2_A),
   1220	PINMUX_IPSR_GPSR(IP10_18_16,	VI1_DATA13),
   1221	PINMUX_IPSR_GPSR(IP10_18_16,	DACK2_B),
   1222	PINMUX_IPSR_GPSR(IP10_18_16,	ATAG1),
   1223	PINMUX_IPSR_MSEL(IP10_18_16,	HSPI_CS2_B,	SEL_HSPI2_B),
   1224	PINMUX_IPSR_MSEL(IP10_18_16,	GPSIN_B,	SEL_GPS_B),
   1225
   1226	PINMUX_IPSR_MSEL(IP10_21_19,	SD2_CD_A,	SEL_SD2_A),
   1227	PINMUX_IPSR_GPSR(IP10_21_19,	VI1_DATA14),
   1228	PINMUX_IPSR_MSEL(IP10_21_19,	EX_WAIT1_B,	SEL_WAIT1_B),
   1229	PINMUX_IPSR_MSEL(IP10_21_19,	DREQ0_B,	SEL_DREQ0_B),
   1230	PINMUX_IPSR_MSEL(IP10_21_19,	HSPI_RX2_B,	SEL_HSPI2_B),
   1231	PINMUX_IPSR_MSEL(IP10_21_19,	REMOCON_A,	SEL_REMOCON_A),
   1232
   1233	PINMUX_IPSR_MSEL(IP10_24_22,	SD2_WP_A,	SEL_SD2_A),
   1234	PINMUX_IPSR_GPSR(IP10_24_22,	VI1_DATA15),
   1235	PINMUX_IPSR_MSEL(IP10_24_22,	EX_WAIT2_B,	SEL_WAIT2_B),
   1236	PINMUX_IPSR_GPSR(IP10_24_22,	DACK0_B),
   1237	PINMUX_IPSR_GPSR(IP10_24_22,	HSPI_TX2_B),
   1238	PINMUX_IPSR_MSEL(IP10_24_22,	CAN_CLK_C,	SEL_CANCLK_C),
   1239};
   1240
   1241/*
   1242 * Pins not associated with a GPIO port.
   1243 */
   1244enum {
   1245	GP_ASSIGN_LAST(),
   1246	NOGP_ALL(),
   1247};
   1248
   1249static const struct sh_pfc_pin pinmux_pins[] = {
   1250	PINMUX_GPIO_GP_ALL(),
   1251	PINMUX_NOGP_ALL(),
   1252};
   1253
   1254/* - macro */
   1255#define SH_PFC_PINS(name, args...) \
   1256	static const unsigned int name ##_pins[] = { args }
   1257#define SH_PFC_MUX1(name, arg1)					\
   1258	static const unsigned int name ##_mux[]  = { arg1##_MARK }
   1259#define SH_PFC_MUX2(name, arg1, arg2)					\
   1260	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
   1261#define SH_PFC_MUX3(name, arg1, arg2, arg3)					\
   1262	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,	\
   1263						     arg3##_MARK }
   1264#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)			\
   1265	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
   1266						     arg3##_MARK, arg4##_MARK }
   1267#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
   1268	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
   1269						     arg3##_MARK, arg4##_MARK, \
   1270						     arg5##_MARK, arg6##_MARK, \
   1271						     arg7##_MARK, arg8##_MARK, }
   1272
   1273/* - AUDIO macro -------------------------------------------------------------*/
   1274#define AUDIO_PFC_PIN(name, pin)	SH_PFC_PINS(name, pin)
   1275#define AUDIO_PFC_DAT(name, pin)	SH_PFC_MUX1(name, pin)
   1276
   1277/* - AUDIO clock -------------------------------------------------------------*/
   1278AUDIO_PFC_PIN(audio_clk_a,	RCAR_GP_PIN(2, 22));
   1279AUDIO_PFC_DAT(audio_clk_a,	AUDIO_CLKA);
   1280AUDIO_PFC_PIN(audio_clk_b,	RCAR_GP_PIN(2, 23));
   1281AUDIO_PFC_DAT(audio_clk_b,	AUDIO_CLKB);
   1282AUDIO_PFC_PIN(audio_clk_c,	RCAR_GP_PIN(2, 7));
   1283AUDIO_PFC_DAT(audio_clk_c,	AUDIO_CLKC);
   1284AUDIO_PFC_PIN(audio_clkout_a,	RCAR_GP_PIN(2, 16));
   1285AUDIO_PFC_DAT(audio_clkout_a,	AUDIO_CLKOUT_A);
   1286AUDIO_PFC_PIN(audio_clkout_b,	RCAR_GP_PIN(1, 16));
   1287AUDIO_PFC_DAT(audio_clkout_b,	AUDIO_CLKOUT_B);
   1288
   1289/* - CAN macro --------_----------------------------------------------------- */
   1290#define CAN_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
   1291#define CAN_PFC_DATA(name, tx, rx)		SH_PFC_MUX2(name, tx, rx)
   1292#define CAN_PFC_CLK(name, clk)			SH_PFC_MUX1(name, clk)
   1293
   1294/* - CAN0 ------------------------------------------------------------------- */
   1295CAN_PFC_PINS(can0_data_a,	RCAR_GP_PIN(1, 30),	RCAR_GP_PIN(1, 31));
   1296CAN_PFC_DATA(can0_data_a,	CAN0_TX_A,		CAN0_RX_A);
   1297CAN_PFC_PINS(can0_data_b,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(2, 27));
   1298CAN_PFC_DATA(can0_data_b,	CAN0_TX_B,		CAN0_RX_B);
   1299
   1300/* - CAN1 ------------------------------------------------------------------- */
   1301CAN_PFC_PINS(can1_data_a,	RCAR_GP_PIN(4, 20),	RCAR_GP_PIN(4, 19));
   1302CAN_PFC_DATA(can1_data_a,	CAN1_TX_A,		CAN1_RX_A);
   1303CAN_PFC_PINS(can1_data_b,	RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 29));
   1304CAN_PFC_DATA(can1_data_b,	CAN1_TX_B,		CAN1_RX_B);
   1305
   1306/* - CAN_CLK  --------------------------------------------------------------- */
   1307CAN_PFC_PINS(can_clk_a,		RCAR_GP_PIN(3, 24));
   1308CAN_PFC_CLK(can_clk_a,		CAN_CLK_A);
   1309CAN_PFC_PINS(can_clk_b,		RCAR_GP_PIN(1, 16));
   1310CAN_PFC_CLK(can_clk_b,		CAN_CLK_B);
   1311CAN_PFC_PINS(can_clk_c,		RCAR_GP_PIN(4, 24));
   1312CAN_PFC_CLK(can_clk_c,		CAN_CLK_C);
   1313CAN_PFC_PINS(can_clk_d,		RCAR_GP_PIN(2, 25));
   1314CAN_PFC_CLK(can_clk_d,		CAN_CLK_D);
   1315
   1316/* - Ether ------------------------------------------------------------------ */
   1317SH_PFC_PINS(ether_rmii,		RCAR_GP_PIN(4, 10),	RCAR_GP_PIN(4, 11),
   1318				RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 9),
   1319				RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16),
   1320				RCAR_GP_PIN(4, 12),	RCAR_GP_PIN(4, 14),
   1321				RCAR_GP_PIN(4, 18),	RCAR_GP_PIN(4, 17));
   1322static const unsigned int ether_rmii_mux[] = {
   1323	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
   1324	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
   1325	ETH_MDIO_MARK, ETH_MDC_MARK,
   1326};
   1327SH_PFC_PINS(ether_link,		RCAR_GP_PIN(4, 19));
   1328SH_PFC_MUX1(ether_link,		ETH_LINK);
   1329SH_PFC_PINS(ether_magic,	RCAR_GP_PIN(4, 20));
   1330SH_PFC_MUX1(ether_magic,	ETH_MAGIC);
   1331
   1332/* - SCIF macro ------------------------------------------------------------- */
   1333#define SCIF_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
   1334#define SCIF_PFC_DAT(name, tx, rx)	SH_PFC_MUX2(name, tx, rx)
   1335#define SCIF_PFC_CTR(name, cts, rts)	SH_PFC_MUX2(name, cts, rts)
   1336#define SCIF_PFC_CLK(name, sck)		SH_PFC_MUX1(name, sck)
   1337
   1338/* - HSCIF0 ----------------------------------------------------------------- */
   1339SCIF_PFC_PIN(hscif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
   1340SCIF_PFC_DAT(hscif0_data_a,	HTX0_A,			HRX0_A);
   1341SCIF_PFC_PIN(hscif0_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 30));
   1342SCIF_PFC_DAT(hscif0_data_b,	HTX0_B,			HRX0_B);
   1343SCIF_PFC_PIN(hscif0_ctrl_a,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
   1344SCIF_PFC_CTR(hscif0_ctrl_a,	HCTS0_A,		HRTS0_A);
   1345SCIF_PFC_PIN(hscif0_ctrl_b,	RCAR_GP_PIN(0, 31),	RCAR_GP_PIN(0, 28));
   1346SCIF_PFC_CTR(hscif0_ctrl_b,	HCTS0_B,		HRTS0_B);
   1347SCIF_PFC_PIN(hscif0_clk,	RCAR_GP_PIN(1, 19));
   1348SCIF_PFC_CLK(hscif0_clk,	HSCK0);
   1349
   1350/* - HSCIF1 ----------------------------------------------------------------- */
   1351SCIF_PFC_PIN(hscif1_data_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20));
   1352SCIF_PFC_DAT(hscif1_data_a,	HTX1_A,			HRX1_A);
   1353SCIF_PFC_PIN(hscif1_data_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
   1354SCIF_PFC_DAT(hscif1_data_b,	HTX1_B,			HRX1_B);
   1355SCIF_PFC_PIN(hscif1_ctrl_a,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
   1356SCIF_PFC_CTR(hscif1_ctrl_a,	HCTS1_A,		HRTS1_A);
   1357SCIF_PFC_PIN(hscif1_ctrl_b,	RCAR_GP_PIN(4, 8),	RCAR_GP_PIN(4, 7));
   1358SCIF_PFC_CTR(hscif1_ctrl_b,	HCTS1_B,		HRTS1_B);
   1359SCIF_PFC_PIN(hscif1_clk_a,	RCAR_GP_PIN(3, 23));
   1360SCIF_PFC_CLK(hscif1_clk_a,	HSCK1_A);
   1361SCIF_PFC_PIN(hscif1_clk_b,	RCAR_GP_PIN(4, 2));
   1362SCIF_PFC_CLK(hscif1_clk_b,	HSCK1_B);
   1363
   1364/* - HSPI macro --------------------------------------------------------------*/
   1365#define HSPI_PFC_PIN(name, args...)		SH_PFC_PINS(name, args)
   1366#define HSPI_PFC_DAT(name, clk, cs, rx, tx)	SH_PFC_MUX4(name, clk, cs, rx, tx)
   1367
   1368/* - HSPI0 -------------------------------------------------------------------*/
   1369HSPI_PFC_PIN(hspi0_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20),
   1370			RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
   1371HSPI_PFC_DAT(hspi0_a,	HSPI_CLK0_A,		HSPI_CS0_A,
   1372			HSPI_RX0_A,		HSPI_TX0);
   1373
   1374HSPI_PFC_PIN(hspi0_b,	RCAR_GP_PIN(2, 25),	RCAR_GP_PIN(2, 26),
   1375			RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 27));
   1376HSPI_PFC_DAT(hspi0_b,	HSPI_CLK0_B,		HSPI_CS0_B,
   1377			HSPI_RX0_B,		HSPI_TX0_B);
   1378
   1379/* - HSPI1 -------------------------------------------------------------------*/
   1380HSPI_PFC_PIN(hspi1_a,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 27),
   1381			RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 28));
   1382HSPI_PFC_DAT(hspi1_a,	HSPI_CLK1_A,		HSPI_CS1_A,
   1383			HSPI_RX1_A,		HSPI_TX1_A);
   1384
   1385HSPI_PFC_PIN(hspi1_b,	RCAR_GP_PIN(0, 27),	RCAR_GP_PIN(0, 26),
   1386			PIN_CS0,		PIN_CLKOUT);
   1387HSPI_PFC_DAT(hspi1_b,	HSPI_CLK1_B,		HSPI_CS1_B,
   1388			HSPI_RX1_B,		HSPI_TX1_B);
   1389
   1390/* - HSPI2 -------------------------------------------------------------------*/
   1391HSPI_PFC_PIN(hspi2_a,	RCAR_GP_PIN(2, 29),	RCAR_GP_PIN(3, 8),
   1392			RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 30));
   1393HSPI_PFC_DAT(hspi2_a,	HSPI_CLK2_A,		HSPI_CS2_A,
   1394			HSPI_RX2_A,		HSPI_TX2_A);
   1395
   1396HSPI_PFC_PIN(hspi2_b,	RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22),
   1397			RCAR_GP_PIN(4, 23),	RCAR_GP_PIN(4, 24));
   1398HSPI_PFC_DAT(hspi2_b,	HSPI_CLK2_B,		HSPI_CS2_B,
   1399			HSPI_RX2_B,		HSPI_TX2_B);
   1400
   1401/* - I2C macro ------------------------------------------------------------- */
   1402#define I2C_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
   1403#define I2C_PFC_MUX(name, sda, scl)	SH_PFC_MUX2(name, sda, scl)
   1404
   1405/* - I2C1 ------------------------------------------------------------------ */
   1406I2C_PFC_PIN(i2c1_a,	RCAR_GP_PIN(3, 8),	RCAR_GP_PIN(3, 9));
   1407I2C_PFC_MUX(i2c1_a,	SDA1_A,			SCL1_A);
   1408I2C_PFC_PIN(i2c1_b,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
   1409I2C_PFC_MUX(i2c1_b,	SDA1_B,			SCL1_B);
   1410
   1411/* - I2C2 ------------------------------------------------------------------ */
   1412I2C_PFC_PIN(i2c2_a,	PIN_CS1_A26,		RCAR_GP_PIN(1, 3));
   1413I2C_PFC_MUX(i2c2_a,	SDA2_A,			SCL2_A);
   1414I2C_PFC_PIN(i2c2_b,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
   1415I2C_PFC_MUX(i2c2_b,	SDA2_B,			SCL2_B);
   1416I2C_PFC_PIN(i2c2_c,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
   1417I2C_PFC_MUX(i2c2_c,	SDA2_C,			SCL2_C);
   1418
   1419/* - I2C3 ------------------------------------------------------------------ */
   1420I2C_PFC_PIN(i2c3_a,	RCAR_GP_PIN(1, 14),	RCAR_GP_PIN(1, 15));
   1421I2C_PFC_MUX(i2c3_a,	SDA3_A,			SCL3_A);
   1422I2C_PFC_PIN(i2c3_b,	RCAR_GP_PIN(1, 16),	RCAR_GP_PIN(1, 19));
   1423I2C_PFC_MUX(i2c3_b,	SDA3_B,			SCL3_B);
   1424I2C_PFC_PIN(i2c3_c,	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 23));
   1425I2C_PFC_MUX(i2c3_c,	SDA3_C,			SCL3_C);
   1426
   1427/* - MMC macro -------------------------------------------------------------- */
   1428#define MMC_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
   1429#define MMC_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
   1430#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
   1431			SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
   1432
   1433/* - MMC -------------------------------------------------------------------- */
   1434MMC_PFC_PINS(mmc_ctrl,		RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
   1435MMC_PFC_CTRL(mmc_ctrl,		MMC_CLK,		MMC_CMD);
   1436MMC_PFC_PINS(mmc_data,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
   1437				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6),
   1438				RCAR_GP_PIN(1, 4),	RCAR_GP_PIN(1, 0),
   1439				RCAR_GP_PIN(0, 30),	RCAR_GP_PIN(0, 31));
   1440MMC_PFC_DAT8(mmc_data,		MMC_D0,			MMC_D1,
   1441				MMC_D2,			MMC_D3,
   1442				MMC_D4,			MMC_D5,
   1443				MMC_D6,			MMC_D7);
   1444
   1445/* - SCIF CLOCK ------------------------------------------------------------- */
   1446SCIF_PFC_PIN(scif_clk,		RCAR_GP_PIN(1, 16));
   1447SCIF_PFC_CLK(scif_clk,		SCIF_CLK);
   1448
   1449/* - SCIF0 ------------------------------------------------------------------ */
   1450SCIF_PFC_PIN(scif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
   1451SCIF_PFC_DAT(scif0_data_a,	TX0_A,			RX0_A);
   1452SCIF_PFC_PIN(scif0_data_b,	RCAR_GP_PIN(2, 3),	RCAR_GP_PIN(2, 2));
   1453SCIF_PFC_DAT(scif0_data_b,	TX0_B,			RX0_B);
   1454SCIF_PFC_PIN(scif0_data_c,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(3, 31));
   1455SCIF_PFC_DAT(scif0_data_c,	TX0_C,			RX0_C);
   1456SCIF_PFC_PIN(scif0_data_d,	RCAR_GP_PIN(3, 6),	RCAR_GP_PIN(3, 1));
   1457SCIF_PFC_DAT(scif0_data_d,	TX0_D,			RX0_D);
   1458SCIF_PFC_PIN(scif0_ctrl,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
   1459SCIF_PFC_CTR(scif0_ctrl,	CTS0,			RTS0);
   1460SCIF_PFC_PIN(scif0_clk,		RCAR_GP_PIN(1, 19));
   1461SCIF_PFC_CLK(scif0_clk,		SCK0);
   1462
   1463/* - SCIF1 ------------------------------------------------------------------ */
   1464SCIF_PFC_PIN(scif1_data_a,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(4, 1));
   1465SCIF_PFC_DAT(scif1_data_a,	TX1_A,			RX1_A);
   1466SCIF_PFC_PIN(scif1_data_b,	RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 25));
   1467SCIF_PFC_DAT(scif1_data_b,	TX1_B,			RX1_B);
   1468SCIF_PFC_PIN(scif1_data_c,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
   1469SCIF_PFC_DAT(scif1_data_c,	TX1_C,			RX1_C);
   1470SCIF_PFC_PIN(scif1_data_d,	RCAR_GP_PIN(1, 30),	RCAR_GP_PIN(1, 31));
   1471SCIF_PFC_DAT(scif1_data_d,	TX1_D,			RX1_D);
   1472SCIF_PFC_PIN(scif1_ctrl_a,	RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
   1473SCIF_PFC_CTR(scif1_ctrl_a,	CTS1_A,			RTS1_A);
   1474SCIF_PFC_PIN(scif1_ctrl_c,	RCAR_GP_PIN(3, 23),	RCAR_GP_PIN(3, 19));
   1475SCIF_PFC_CTR(scif1_ctrl_c,	CTS1_C,			RTS1_C);
   1476SCIF_PFC_PIN(scif1_clk_a,	RCAR_GP_PIN(4, 2));
   1477SCIF_PFC_CLK(scif1_clk_a,	SCK1_A);
   1478SCIF_PFC_PIN(scif1_clk_c,	RCAR_GP_PIN(3, 20));
   1479SCIF_PFC_CLK(scif1_clk_c,	SCK1_C);
   1480
   1481/* - SCIF2 ------------------------------------------------------------------ */
   1482SCIF_PFC_PIN(scif2_data_a,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(2, 27));
   1483SCIF_PFC_DAT(scif2_data_a,	TX2_A,			RX2_A);
   1484SCIF_PFC_PIN(scif2_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 28));
   1485SCIF_PFC_DAT(scif2_data_b,	TX2_B,			RX2_B);
   1486SCIF_PFC_PIN(scif2_data_c,	RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 14));
   1487SCIF_PFC_DAT(scif2_data_c,	TX2_C,			RX2_C);
   1488SCIF_PFC_PIN(scif2_data_d,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
   1489SCIF_PFC_DAT(scif2_data_d,	TX2_D,			RX2_D);
   1490SCIF_PFC_PIN(scif2_data_e,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
   1491SCIF_PFC_DAT(scif2_data_e,	TX2_E,			RX2_E);
   1492SCIF_PFC_PIN(scif2_clk_a,	RCAR_GP_PIN(3, 9));
   1493SCIF_PFC_CLK(scif2_clk_a,	SCK2_A);
   1494SCIF_PFC_PIN(scif2_clk_b,	PIN_CS1_A26);
   1495SCIF_PFC_CLK(scif2_clk_b,	SCK2_B);
   1496SCIF_PFC_PIN(scif2_clk_c,	RCAR_GP_PIN(4, 12));
   1497SCIF_PFC_CLK(scif2_clk_c,	SCK2_C);
   1498
   1499/* - SCIF3 ------------------------------------------------------------------ */
   1500SCIF_PFC_PIN(scif3_data_a,	RCAR_GP_PIN(1, 10),	RCAR_GP_PIN(1, 9));
   1501SCIF_PFC_DAT(scif3_data_a,	TX3_A,			RX3_A);
   1502SCIF_PFC_PIN(scif3_data_b,	RCAR_GP_PIN(3, 28),	RCAR_GP_PIN(3, 27));
   1503SCIF_PFC_DAT(scif3_data_b,	TX3_B,			RX3_B);
   1504SCIF_PFC_PIN(scif3_data_c,	RCAR_GP_PIN(1, 3),	RCAR_GP_PIN(0, 31));
   1505SCIF_PFC_DAT(scif3_data_c,	TX3_C,			RX3_C);
   1506SCIF_PFC_PIN(scif3_data_d,	RCAR_GP_PIN(3, 30),	RCAR_GP_PIN(3, 29));
   1507SCIF_PFC_DAT(scif3_data_d,	TX3_D,			RX3_D);
   1508
   1509/* - SCIF4 ------------------------------------------------------------------ */
   1510SCIF_PFC_PIN(scif4_data_a,	RCAR_GP_PIN(2, 5),	RCAR_GP_PIN(2, 4));
   1511SCIF_PFC_DAT(scif4_data_a,	TX4_A,			RX4_A);
   1512SCIF_PFC_PIN(scif4_data_b,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 25));
   1513SCIF_PFC_DAT(scif4_data_b,	TX4_B,			RX4_B);
   1514SCIF_PFC_PIN(scif4_data_c,	RCAR_GP_PIN(3, 0),	RCAR_GP_PIN(2, 31));
   1515SCIF_PFC_DAT(scif4_data_c,	TX4_C,			RX4_C);
   1516
   1517/* - SCIF5 ------------------------------------------------------------------ */
   1518SCIF_PFC_PIN(scif5_data_a,	RCAR_GP_PIN(3, 17),	RCAR_GP_PIN(3, 18));
   1519SCIF_PFC_DAT(scif5_data_a,	TX5_A,			RX5_A);
   1520SCIF_PFC_PIN(scif5_data_b,	RCAR_GP_PIN(1, 15),	RCAR_GP_PIN(1, 14));
   1521SCIF_PFC_DAT(scif5_data_b,	TX5_B,			RX5_B);
   1522
   1523/* - SDHI macro ------------------------------------------------------------- */
   1524#define SDHI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
   1525#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
   1526#define SDHI_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
   1527#define SDHI_PFC_CDPN(name, cd)			SH_PFC_MUX1(name, cd)
   1528#define SDHI_PFC_WPPN(name, wp)			SH_PFC_MUX1(name, wp)
   1529
   1530/* - SDHI0 ------------------------------------------------------------------ */
   1531SDHI_PFC_PINS(sdhi0_cd,		RCAR_GP_PIN(3, 17));
   1532SDHI_PFC_CDPN(sdhi0_cd,		SD0_CD);
   1533SDHI_PFC_PINS(sdhi0_ctrl,	RCAR_GP_PIN(3, 11),	RCAR_GP_PIN(3, 12));
   1534SDHI_PFC_CTRL(sdhi0_ctrl,	SD0_CLK,		SD0_CMD);
   1535SDHI_PFC_PINS(sdhi0_data,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
   1536				RCAR_GP_PIN(3, 15),	RCAR_GP_PIN(3, 16));
   1537SDHI_PFC_DAT4(sdhi0_data,	SD0_DAT0,		SD0_DAT1,
   1538				SD0_DAT2,		SD0_DAT3);
   1539SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
   1540SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
   1541
   1542/* - SDHI1 ------------------------------------------------------------------ */
   1543SDHI_PFC_PINS(sdhi1_cd_a,	RCAR_GP_PIN(0, 30));
   1544SDHI_PFC_CDPN(sdhi1_cd_a,	SD1_CD_A);
   1545SDHI_PFC_PINS(sdhi1_cd_b,	RCAR_GP_PIN(2, 24));
   1546SDHI_PFC_CDPN(sdhi1_cd_b,	SD1_CD_B);
   1547SDHI_PFC_PINS(sdhi1_ctrl_a,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
   1548SDHI_PFC_CTRL(sdhi1_ctrl_a,	SD1_CLK_A,		SD1_CMD_A);
   1549SDHI_PFC_PINS(sdhi1_ctrl_b,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
   1550SDHI_PFC_CTRL(sdhi1_ctrl_b,	SD1_CLK_B,		SD1_CMD_B);
   1551SDHI_PFC_PINS(sdhi1_data_a,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
   1552				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
   1553SDHI_PFC_DAT4(sdhi1_data_a,	SD1_DAT0_A,		SD1_DAT1_A,
   1554				SD1_DAT2_A,		SD1_DAT3_A);
   1555SDHI_PFC_PINS(sdhi1_data_b,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
   1556				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
   1557SDHI_PFC_DAT4(sdhi1_data_b,	SD1_DAT0_B,		SD1_DAT1_B,
   1558				SD1_DAT2_B,		SD1_DAT3_B);
   1559SDHI_PFC_PINS(sdhi1_wp_a,	RCAR_GP_PIN(0, 31));
   1560SDHI_PFC_WPPN(sdhi1_wp_a,	SD1_WP_A);
   1561SDHI_PFC_PINS(sdhi1_wp_b,	RCAR_GP_PIN(2, 25));
   1562SDHI_PFC_WPPN(sdhi1_wp_b,	SD1_WP_B);
   1563
   1564/* - SDH2 ------------------------------------------------------------------- */
   1565SDHI_PFC_PINS(sdhi2_cd_a,	RCAR_GP_PIN(4, 23));
   1566SDHI_PFC_CDPN(sdhi2_cd_a,	SD2_CD_A);
   1567SDHI_PFC_PINS(sdhi2_cd_b,	RCAR_GP_PIN(3, 27));
   1568SDHI_PFC_CDPN(sdhi2_cd_b,	SD2_CD_B);
   1569SDHI_PFC_PINS(sdhi2_ctrl_a,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
   1570SDHI_PFC_CTRL(sdhi2_ctrl_a,	SD2_CLK_A,		SD2_CMD_A);
   1571SDHI_PFC_PINS(sdhi2_ctrl_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
   1572SDHI_PFC_CTRL(sdhi2_ctrl_b,	SD2_CLK_B,		SD2_CMD_B);
   1573SDHI_PFC_PINS(sdhi2_data_a,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
   1574				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
   1575SDHI_PFC_DAT4(sdhi2_data_a,	SD2_DAT0_A,		SD2_DAT1_A,
   1576				SD2_DAT2_A,		SD2_DAT3_A);
   1577SDHI_PFC_PINS(sdhi2_data_b,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
   1578				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
   1579SDHI_PFC_DAT4(sdhi2_data_b,	SD2_DAT0_B,		SD2_DAT1_B,
   1580				SD2_DAT2_B,		SD2_DAT3_B);
   1581SDHI_PFC_PINS(sdhi2_wp_a,	RCAR_GP_PIN(4, 24));
   1582SDHI_PFC_WPPN(sdhi2_wp_a,	SD2_WP_A);
   1583SDHI_PFC_PINS(sdhi2_wp_b,	RCAR_GP_PIN(3, 28));
   1584SDHI_PFC_WPPN(sdhi2_wp_b,	SD2_WP_B);
   1585
   1586/* - SSI macro -------------------------------------------------------------- */
   1587#define SSI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
   1588#define SSI_PFC_CTRL(name, sck, ws)		SH_PFC_MUX2(name, sck, ws)
   1589#define SSI_PFC_DATA(name, d)			SH_PFC_MUX1(name, d)
   1590
   1591/* - SSI 0/1/2 -------------------------------------------------------------- */
   1592SSI_PFC_PINS(ssi012_ctrl,	RCAR_GP_PIN(3, 6),	RCAR_GP_PIN(3, 7));
   1593SSI_PFC_CTRL(ssi012_ctrl,	SSI_SCK012,		SSI_WS012);
   1594SSI_PFC_PINS(ssi0_data,		RCAR_GP_PIN(3, 10));
   1595SSI_PFC_DATA(ssi0_data,		SSI_SDATA0);
   1596SSI_PFC_PINS(ssi1_a_ctrl,	RCAR_GP_PIN(2, 20),	RCAR_GP_PIN(2, 21));
   1597SSI_PFC_CTRL(ssi1_a_ctrl,	SSI_SCK1_A,		SSI_WS1_A);
   1598SSI_PFC_PINS(ssi1_b_ctrl,	PIN_CS1_A26,		RCAR_GP_PIN(1, 3));
   1599SSI_PFC_CTRL(ssi1_b_ctrl,	SSI_SCK1_B,		SSI_WS1_B);
   1600SSI_PFC_PINS(ssi1_data,		RCAR_GP_PIN(3, 9));
   1601SSI_PFC_DATA(ssi1_data,		SSI_SDATA1);
   1602SSI_PFC_PINS(ssi2_a_ctrl,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(3, 4));
   1603SSI_PFC_CTRL(ssi2_a_ctrl,	SSI_SCK2_A,		SSI_WS2_A);
   1604SSI_PFC_PINS(ssi2_b_ctrl,	RCAR_GP_PIN(2, 6),	RCAR_GP_PIN(2, 17));
   1605SSI_PFC_CTRL(ssi2_b_ctrl,	SSI_SCK2_B,		SSI_WS2_B);
   1606SSI_PFC_PINS(ssi2_data,		RCAR_GP_PIN(3, 8));
   1607SSI_PFC_DATA(ssi2_data,		SSI_SDATA2);
   1608
   1609/* - SSI 3/4 ---------------------------------------------------------------- */
   1610SSI_PFC_PINS(ssi34_ctrl,	RCAR_GP_PIN(3, 2),	RCAR_GP_PIN(3, 3));
   1611SSI_PFC_CTRL(ssi34_ctrl,	SSI_SCK34,		SSI_WS34);
   1612SSI_PFC_PINS(ssi3_data,		RCAR_GP_PIN(3, 5));
   1613SSI_PFC_DATA(ssi3_data,		SSI_SDATA3);
   1614SSI_PFC_PINS(ssi4_ctrl,		RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
   1615SSI_PFC_CTRL(ssi4_ctrl,		SSI_SCK4,               SSI_WS4);
   1616SSI_PFC_PINS(ssi4_data,		RCAR_GP_PIN(3, 4));
   1617SSI_PFC_DATA(ssi4_data,		SSI_SDATA4);
   1618
   1619/* - SSI 5 ------------------------------------------------------------------ */
   1620SSI_PFC_PINS(ssi5_ctrl,		RCAR_GP_PIN(2, 31),	RCAR_GP_PIN(3, 0));
   1621SSI_PFC_CTRL(ssi5_ctrl,		SSI_SCK5,		SSI_WS5);
   1622SSI_PFC_PINS(ssi5_data,		RCAR_GP_PIN(3, 1));
   1623SSI_PFC_DATA(ssi5_data,		SSI_SDATA5);
   1624
   1625/* - SSI 6 ------------------------------------------------------------------ */
   1626SSI_PFC_PINS(ssi6_ctrl,		RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 29));
   1627SSI_PFC_CTRL(ssi6_ctrl,		SSI_SCK6,		SSI_WS6);
   1628SSI_PFC_PINS(ssi6_data,		RCAR_GP_PIN(2, 30));
   1629SSI_PFC_DATA(ssi6_data,		SSI_SDATA6);
   1630
   1631/* - SSI 7/8  --------------------------------------------------------------- */
   1632SSI_PFC_PINS(ssi78_ctrl,	RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 25));
   1633SSI_PFC_CTRL(ssi78_ctrl,	SSI_SCK78,		SSI_WS78);
   1634SSI_PFC_PINS(ssi7_data,		RCAR_GP_PIN(2, 27));
   1635SSI_PFC_DATA(ssi7_data,		SSI_SDATA7);
   1636SSI_PFC_PINS(ssi8_data,		RCAR_GP_PIN(2, 26));
   1637SSI_PFC_DATA(ssi8_data,		SSI_SDATA8);
   1638
   1639/* - USB0 ------------------------------------------------------------------- */
   1640SH_PFC_PINS(usb0,		RCAR_GP_PIN(0, 1));
   1641SH_PFC_MUX1(usb0,		PENC0);
   1642SH_PFC_PINS(usb0_ovc,		RCAR_GP_PIN(0, 3));
   1643SH_PFC_MUX1(usb0_ovc,		USB_OVC0);
   1644
   1645/* - USB1 ------------------------------------------------------------------- */
   1646SH_PFC_PINS(usb1,		RCAR_GP_PIN(0, 2));
   1647SH_PFC_MUX1(usb1,		PENC1);
   1648SH_PFC_PINS(usb1_ovc,		RCAR_GP_PIN(0, 4));
   1649SH_PFC_MUX1(usb1_ovc,		USB_OVC1);
   1650
   1651/* - VIN macros ------------------------------------------------------------- */
   1652#define VIN_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
   1653#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
   1654	SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
   1655#define VIN_PFC_CLK(name, clk)			SH_PFC_MUX1(name, clk)
   1656#define VIN_PFC_SYNC(name, hsync, vsync)	SH_PFC_MUX2(name, hsync, vsync)
   1657
   1658/* - VIN0 ------------------------------------------------------------------- */
   1659VIN_PFC_PINS(vin0_data8,	RCAR_GP_PIN(3, 29),	RCAR_GP_PIN(3, 30),
   1660				RCAR_GP_PIN(3, 31),	RCAR_GP_PIN(4, 0),
   1661				RCAR_GP_PIN(4, 1),	RCAR_GP_PIN(4, 2),
   1662				RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
   1663VIN_PFC_DAT8(vin0_data8,	VI0_DATA0_VI0_B0,	VI0_DATA1_VI0_B1,
   1664				VI0_DATA2_VI0_B2,	VI0_DATA3_VI0_B3,
   1665				VI0_DATA4_VI0_B4,	VI0_DATA5_VI0_B5,
   1666				VI0_DATA6_VI0_G0,	VI0_DATA7_VI0_G1);
   1667VIN_PFC_PINS(vin0_clk,		RCAR_GP_PIN(3, 24));
   1668VIN_PFC_CLK(vin0_clk,		VI0_CLK);
   1669VIN_PFC_PINS(vin0_sync,		RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28));
   1670VIN_PFC_SYNC(vin0_sync,		VI0_HSYNC,		VI0_VSYNC);
   1671/* - VIN1 ------------------------------------------------------------------- */
   1672VIN_PFC_PINS(vin1_data8,	RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26),
   1673				RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28),
   1674				RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6),
   1675				RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8));
   1676VIN_PFC_DAT8(vin1_data8,	VI1_DATA0,		VI1_DATA1,
   1677				VI1_DATA2,		VI1_DATA3,
   1678				VI1_DATA4,		VI1_DATA5,
   1679				VI1_DATA6,		VI1_DATA7);
   1680VIN_PFC_PINS(vin1_clk,		RCAR_GP_PIN(4, 9));
   1681VIN_PFC_CLK(vin1_clk,		VI1_CLK);
   1682VIN_PFC_PINS(vin1_sync,		RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
   1683VIN_PFC_SYNC(vin1_sync,		VI1_HSYNC,		VI1_VSYNC);
   1684
   1685static const struct sh_pfc_pin_group pinmux_groups[] = {
   1686	SH_PFC_PIN_GROUP(audio_clk_a),
   1687	SH_PFC_PIN_GROUP(audio_clk_b),
   1688	SH_PFC_PIN_GROUP(audio_clk_c),
   1689	SH_PFC_PIN_GROUP(audio_clkout_a),
   1690	SH_PFC_PIN_GROUP(audio_clkout_b),
   1691	SH_PFC_PIN_GROUP(can0_data_a),
   1692	SH_PFC_PIN_GROUP(can0_data_b),
   1693	SH_PFC_PIN_GROUP(can1_data_a),
   1694	SH_PFC_PIN_GROUP(can1_data_b),
   1695	SH_PFC_PIN_GROUP(can_clk_a),
   1696	SH_PFC_PIN_GROUP(can_clk_b),
   1697	SH_PFC_PIN_GROUP(can_clk_c),
   1698	SH_PFC_PIN_GROUP(can_clk_d),
   1699	SH_PFC_PIN_GROUP(ether_rmii),
   1700	SH_PFC_PIN_GROUP(ether_link),
   1701	SH_PFC_PIN_GROUP(ether_magic),
   1702	SH_PFC_PIN_GROUP(hscif0_data_a),
   1703	SH_PFC_PIN_GROUP(hscif0_data_b),
   1704	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
   1705	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
   1706	SH_PFC_PIN_GROUP(hscif0_clk),
   1707	SH_PFC_PIN_GROUP(hscif1_data_a),
   1708	SH_PFC_PIN_GROUP(hscif1_data_b),
   1709	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
   1710	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
   1711	SH_PFC_PIN_GROUP(hscif1_clk_a),
   1712	SH_PFC_PIN_GROUP(hscif1_clk_b),
   1713	SH_PFC_PIN_GROUP(hspi0_a),
   1714	SH_PFC_PIN_GROUP(hspi0_b),
   1715	SH_PFC_PIN_GROUP(hspi1_a),
   1716	SH_PFC_PIN_GROUP(hspi1_b),
   1717	SH_PFC_PIN_GROUP(hspi2_a),
   1718	SH_PFC_PIN_GROUP(hspi2_b),
   1719	SH_PFC_PIN_GROUP(i2c1_a),
   1720	SH_PFC_PIN_GROUP(i2c1_b),
   1721	SH_PFC_PIN_GROUP(i2c2_a),
   1722	SH_PFC_PIN_GROUP(i2c2_b),
   1723	SH_PFC_PIN_GROUP(i2c2_c),
   1724	SH_PFC_PIN_GROUP(i2c3_a),
   1725	SH_PFC_PIN_GROUP(i2c3_b),
   1726	SH_PFC_PIN_GROUP(i2c3_c),
   1727	SH_PFC_PIN_GROUP(mmc_ctrl),
   1728	BUS_DATA_PIN_GROUP(mmc_data, 1),
   1729	BUS_DATA_PIN_GROUP(mmc_data, 4),
   1730	BUS_DATA_PIN_GROUP(mmc_data, 8),
   1731	SH_PFC_PIN_GROUP(scif_clk),
   1732	SH_PFC_PIN_GROUP(scif0_data_a),
   1733	SH_PFC_PIN_GROUP(scif0_data_b),
   1734	SH_PFC_PIN_GROUP(scif0_data_c),
   1735	SH_PFC_PIN_GROUP(scif0_data_d),
   1736	SH_PFC_PIN_GROUP(scif0_ctrl),
   1737	SH_PFC_PIN_GROUP(scif0_clk),
   1738	SH_PFC_PIN_GROUP(scif1_data_a),
   1739	SH_PFC_PIN_GROUP(scif1_data_b),
   1740	SH_PFC_PIN_GROUP(scif1_data_c),
   1741	SH_PFC_PIN_GROUP(scif1_data_d),
   1742	SH_PFC_PIN_GROUP(scif1_ctrl_a),
   1743	SH_PFC_PIN_GROUP(scif1_ctrl_c),
   1744	SH_PFC_PIN_GROUP(scif1_clk_a),
   1745	SH_PFC_PIN_GROUP(scif1_clk_c),
   1746	SH_PFC_PIN_GROUP(scif2_data_a),
   1747	SH_PFC_PIN_GROUP(scif2_data_b),
   1748	SH_PFC_PIN_GROUP(scif2_data_c),
   1749	SH_PFC_PIN_GROUP(scif2_data_d),
   1750	SH_PFC_PIN_GROUP(scif2_data_e),
   1751	SH_PFC_PIN_GROUP(scif2_clk_a),
   1752	SH_PFC_PIN_GROUP(scif2_clk_b),
   1753	SH_PFC_PIN_GROUP(scif2_clk_c),
   1754	SH_PFC_PIN_GROUP(scif3_data_a),
   1755	SH_PFC_PIN_GROUP(scif3_data_b),
   1756	SH_PFC_PIN_GROUP(scif3_data_c),
   1757	SH_PFC_PIN_GROUP(scif3_data_d),
   1758	SH_PFC_PIN_GROUP(scif4_data_a),
   1759	SH_PFC_PIN_GROUP(scif4_data_b),
   1760	SH_PFC_PIN_GROUP(scif4_data_c),
   1761	SH_PFC_PIN_GROUP(scif5_data_a),
   1762	SH_PFC_PIN_GROUP(scif5_data_b),
   1763	SH_PFC_PIN_GROUP(sdhi0_cd),
   1764	SH_PFC_PIN_GROUP(sdhi0_ctrl),
   1765	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
   1766	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
   1767	SH_PFC_PIN_GROUP(sdhi0_wp),
   1768	SH_PFC_PIN_GROUP(sdhi1_cd_a),
   1769	SH_PFC_PIN_GROUP(sdhi1_cd_b),
   1770	SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
   1771	SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
   1772	BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
   1773	BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
   1774	BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
   1775	BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
   1776	SH_PFC_PIN_GROUP(sdhi1_wp_a),
   1777	SH_PFC_PIN_GROUP(sdhi1_wp_b),
   1778	SH_PFC_PIN_GROUP(sdhi2_cd_a),
   1779	SH_PFC_PIN_GROUP(sdhi2_cd_b),
   1780	SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
   1781	SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
   1782	BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
   1783	BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
   1784	BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
   1785	BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
   1786	SH_PFC_PIN_GROUP(sdhi2_wp_a),
   1787	SH_PFC_PIN_GROUP(sdhi2_wp_b),
   1788	SH_PFC_PIN_GROUP(ssi012_ctrl),
   1789	SH_PFC_PIN_GROUP(ssi0_data),
   1790	SH_PFC_PIN_GROUP(ssi1_a_ctrl),
   1791	SH_PFC_PIN_GROUP(ssi1_b_ctrl),
   1792	SH_PFC_PIN_GROUP(ssi1_data),
   1793	SH_PFC_PIN_GROUP(ssi2_a_ctrl),
   1794	SH_PFC_PIN_GROUP(ssi2_b_ctrl),
   1795	SH_PFC_PIN_GROUP(ssi2_data),
   1796	SH_PFC_PIN_GROUP(ssi34_ctrl),
   1797	SH_PFC_PIN_GROUP(ssi3_data),
   1798	SH_PFC_PIN_GROUP(ssi4_ctrl),
   1799	SH_PFC_PIN_GROUP(ssi4_data),
   1800	SH_PFC_PIN_GROUP(ssi5_ctrl),
   1801	SH_PFC_PIN_GROUP(ssi5_data),
   1802	SH_PFC_PIN_GROUP(ssi6_ctrl),
   1803	SH_PFC_PIN_GROUP(ssi6_data),
   1804	SH_PFC_PIN_GROUP(ssi78_ctrl),
   1805	SH_PFC_PIN_GROUP(ssi7_data),
   1806	SH_PFC_PIN_GROUP(ssi8_data),
   1807	SH_PFC_PIN_GROUP(usb0),
   1808	SH_PFC_PIN_GROUP(usb0_ovc),
   1809	SH_PFC_PIN_GROUP(usb1),
   1810	SH_PFC_PIN_GROUP(usb1_ovc),
   1811	SH_PFC_PIN_GROUP(vin0_data8),
   1812	SH_PFC_PIN_GROUP(vin0_clk),
   1813	SH_PFC_PIN_GROUP(vin0_sync),
   1814	SH_PFC_PIN_GROUP(vin1_data8),
   1815	SH_PFC_PIN_GROUP(vin1_clk),
   1816	SH_PFC_PIN_GROUP(vin1_sync),
   1817};
   1818
   1819static const char * const audio_clk_groups[] = {
   1820	"audio_clk_a",
   1821	"audio_clk_b",
   1822	"audio_clk_c",
   1823	"audio_clkout_a",
   1824	"audio_clkout_b",
   1825};
   1826
   1827static const char * const can0_groups[] = {
   1828	"can0_data_a",
   1829	"can0_data_b",
   1830	"can_clk_a",
   1831	"can_clk_b",
   1832	"can_clk_c",
   1833	"can_clk_d",
   1834};
   1835
   1836static const char * const can1_groups[] = {
   1837	"can1_data_a",
   1838	"can1_data_b",
   1839	"can_clk_a",
   1840	"can_clk_b",
   1841	"can_clk_c",
   1842	"can_clk_d",
   1843};
   1844
   1845static const char * const ether_groups[] = {
   1846	"ether_rmii",
   1847	"ether_link",
   1848	"ether_magic",
   1849};
   1850
   1851static const char * const hscif0_groups[] = {
   1852	"hscif0_data_a",
   1853	"hscif0_data_b",
   1854	"hscif0_ctrl_a",
   1855	"hscif0_ctrl_b",
   1856	"hscif0_clk",
   1857};
   1858
   1859static const char * const hscif1_groups[] = {
   1860	"hscif1_data_a",
   1861	"hscif1_data_b",
   1862	"hscif1_ctrl_a",
   1863	"hscif1_ctrl_b",
   1864	"hscif1_clk_a",
   1865	"hscif1_clk_b",
   1866};
   1867
   1868static const char * const hspi0_groups[] = {
   1869	"hspi0_a",
   1870	"hspi0_b",
   1871};
   1872
   1873static const char * const hspi1_groups[] = {
   1874	"hspi1_a",
   1875	"hspi1_b",
   1876};
   1877
   1878static const char * const hspi2_groups[] = {
   1879	"hspi2_a",
   1880	"hspi2_b",
   1881};
   1882
   1883static const char * const i2c1_groups[] = {
   1884	"i2c1_a",
   1885	"i2c1_b",
   1886};
   1887
   1888static const char * const i2c2_groups[] = {
   1889	"i2c2_a",
   1890	"i2c2_b",
   1891	"i2c2_c",
   1892};
   1893
   1894static const char * const i2c3_groups[] = {
   1895	"i2c3_a",
   1896	"i2c3_b",
   1897	"i2c3_c",
   1898};
   1899
   1900static const char * const mmc_groups[] = {
   1901	"mmc_ctrl",
   1902	"mmc_data1",
   1903	"mmc_data4",
   1904	"mmc_data8",
   1905};
   1906
   1907static const char * const scif_clk_groups[] = {
   1908	"scif_clk",
   1909};
   1910
   1911static const char * const scif0_groups[] = {
   1912	"scif0_data_a",
   1913	"scif0_data_b",
   1914	"scif0_data_c",
   1915	"scif0_data_d",
   1916	"scif0_ctrl",
   1917	"scif0_clk",
   1918};
   1919
   1920static const char * const scif1_groups[] = {
   1921	"scif1_data_a",
   1922	"scif1_data_b",
   1923	"scif1_data_c",
   1924	"scif1_data_d",
   1925	"scif1_ctrl_a",
   1926	"scif1_ctrl_c",
   1927	"scif1_clk_a",
   1928	"scif1_clk_c",
   1929};
   1930
   1931static const char * const scif2_groups[] = {
   1932	"scif2_data_a",
   1933	"scif2_data_b",
   1934	"scif2_data_c",
   1935	"scif2_data_d",
   1936	"scif2_data_e",
   1937	"scif2_clk_a",
   1938	"scif2_clk_b",
   1939	"scif2_clk_c",
   1940};
   1941
   1942static const char * const scif3_groups[] = {
   1943	"scif3_data_a",
   1944	"scif3_data_b",
   1945	"scif3_data_c",
   1946	"scif3_data_d",
   1947};
   1948
   1949static const char * const scif4_groups[] = {
   1950	"scif4_data_a",
   1951	"scif4_data_b",
   1952	"scif4_data_c",
   1953};
   1954
   1955static const char * const scif5_groups[] = {
   1956	"scif5_data_a",
   1957	"scif5_data_b",
   1958};
   1959
   1960
   1961static const char * const sdhi0_groups[] = {
   1962	"sdhi0_cd",
   1963	"sdhi0_ctrl",
   1964	"sdhi0_data1",
   1965	"sdhi0_data4",
   1966	"sdhi0_wp",
   1967};
   1968
   1969static const char * const sdhi1_groups[] = {
   1970	"sdhi1_cd_a",
   1971	"sdhi1_cd_b",
   1972	"sdhi1_ctrl_a",
   1973	"sdhi1_ctrl_b",
   1974	"sdhi1_data1_a",
   1975	"sdhi1_data1_b",
   1976	"sdhi1_data4_a",
   1977	"sdhi1_data4_b",
   1978	"sdhi1_wp_a",
   1979	"sdhi1_wp_b",
   1980};
   1981
   1982static const char * const sdhi2_groups[] = {
   1983	"sdhi2_cd_a",
   1984	"sdhi2_cd_b",
   1985	"sdhi2_ctrl_a",
   1986	"sdhi2_ctrl_b",
   1987	"sdhi2_data1_a",
   1988	"sdhi2_data1_b",
   1989	"sdhi2_data4_a",
   1990	"sdhi2_data4_b",
   1991	"sdhi2_wp_a",
   1992	"sdhi2_wp_b",
   1993};
   1994
   1995static const char * const ssi_groups[] = {
   1996	"ssi012_ctrl",
   1997	"ssi0_data",
   1998	"ssi1_a_ctrl",
   1999	"ssi1_b_ctrl",
   2000	"ssi1_data",
   2001	"ssi2_a_ctrl",
   2002	"ssi2_b_ctrl",
   2003	"ssi2_data",
   2004	"ssi34_ctrl",
   2005	"ssi3_data",
   2006	"ssi4_ctrl",
   2007	"ssi4_data",
   2008	"ssi5_ctrl",
   2009	"ssi5_data",
   2010	"ssi6_ctrl",
   2011	"ssi6_data",
   2012	"ssi78_ctrl",
   2013	"ssi7_data",
   2014	"ssi8_data",
   2015};
   2016
   2017static const char * const usb0_groups[] = {
   2018	"usb0",
   2019	"usb0_ovc",
   2020};
   2021
   2022static const char * const usb1_groups[] = {
   2023	"usb1",
   2024	"usb1_ovc",
   2025};
   2026
   2027static const char * const vin0_groups[] = {
   2028	"vin0_data8",
   2029	"vin0_clk",
   2030	"vin0_sync",
   2031};
   2032
   2033static const char * const vin1_groups[] = {
   2034	"vin1_data8",
   2035	"vin1_clk",
   2036	"vin1_sync",
   2037};
   2038
   2039static const struct sh_pfc_function pinmux_functions[] = {
   2040	SH_PFC_FUNCTION(audio_clk),
   2041	SH_PFC_FUNCTION(can0),
   2042	SH_PFC_FUNCTION(can1),
   2043	SH_PFC_FUNCTION(ether),
   2044	SH_PFC_FUNCTION(hscif0),
   2045	SH_PFC_FUNCTION(hscif1),
   2046	SH_PFC_FUNCTION(hspi0),
   2047	SH_PFC_FUNCTION(hspi1),
   2048	SH_PFC_FUNCTION(hspi2),
   2049	SH_PFC_FUNCTION(i2c1),
   2050	SH_PFC_FUNCTION(i2c2),
   2051	SH_PFC_FUNCTION(i2c3),
   2052	SH_PFC_FUNCTION(mmc),
   2053	SH_PFC_FUNCTION(scif_clk),
   2054	SH_PFC_FUNCTION(scif0),
   2055	SH_PFC_FUNCTION(scif1),
   2056	SH_PFC_FUNCTION(scif2),
   2057	SH_PFC_FUNCTION(scif3),
   2058	SH_PFC_FUNCTION(scif4),
   2059	SH_PFC_FUNCTION(scif5),
   2060	SH_PFC_FUNCTION(sdhi0),
   2061	SH_PFC_FUNCTION(sdhi1),
   2062	SH_PFC_FUNCTION(sdhi2),
   2063	SH_PFC_FUNCTION(ssi),
   2064	SH_PFC_FUNCTION(usb0),
   2065	SH_PFC_FUNCTION(usb1),
   2066	SH_PFC_FUNCTION(vin0),
   2067	SH_PFC_FUNCTION(vin1),
   2068};
   2069
   2070static const struct pinmux_cfg_reg pinmux_config_regs[] = {
   2071	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
   2072		GP_0_31_FN,	FN_IP1_14_11,
   2073		GP_0_30_FN,	FN_IP1_10_8,
   2074		GP_0_29_FN,	FN_IP1_7_5,
   2075		GP_0_28_FN,	FN_IP1_4_2,
   2076		GP_0_27_FN,	FN_IP1_1,
   2077		GP_0_26_FN,	FN_IP1_0,
   2078		GP_0_25_FN,	FN_IP0_30,
   2079		GP_0_24_FN,	FN_IP0_29,
   2080		GP_0_23_FN,	FN_IP0_28,
   2081		GP_0_22_FN,	FN_IP0_27,
   2082		GP_0_21_FN,	FN_IP0_26,
   2083		GP_0_20_FN,	FN_IP0_25,
   2084		GP_0_19_FN,	FN_IP0_24,
   2085		GP_0_18_FN,	FN_IP0_23,
   2086		GP_0_17_FN,	FN_IP0_22,
   2087		GP_0_16_FN,	FN_IP0_21,
   2088		GP_0_15_FN,	FN_IP0_20,
   2089		GP_0_14_FN,	FN_IP0_19,
   2090		GP_0_13_FN,	FN_IP0_18,
   2091		GP_0_12_FN,	FN_IP0_17,
   2092		GP_0_11_FN,	FN_IP0_16,
   2093		GP_0_10_FN,	FN_IP0_15,
   2094		GP_0_9_FN,	FN_A3,
   2095		GP_0_8_FN,	FN_A2,
   2096		GP_0_7_FN,	FN_A1,
   2097		GP_0_6_FN,	FN_IP0_14_12,
   2098		GP_0_5_FN,	FN_IP0_11_8,
   2099		GP_0_4_FN,	FN_IP0_7_5,
   2100		GP_0_3_FN,	FN_IP0_4_2,
   2101		GP_0_2_FN,	FN_PENC1,
   2102		GP_0_1_FN,	FN_PENC0,
   2103		GP_0_0_FN,	FN_IP0_1_0 ))
   2104	},
   2105	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
   2106		GP_1_31_FN,	FN_IP4_6_4,
   2107		GP_1_30_FN,	FN_IP4_3_1,
   2108		GP_1_29_FN,	FN_IP4_0,
   2109		GP_1_28_FN,	FN_IP3_31,
   2110		GP_1_27_FN,	FN_IP3_30,
   2111		GP_1_26_FN,	FN_IP3_29,
   2112		GP_1_25_FN,	FN_IP3_28,
   2113		GP_1_24_FN,	FN_IP3_27,
   2114		GP_1_23_FN,	FN_IP3_26_24,
   2115		GP_1_22_FN,	FN_IP3_23_21,
   2116		GP_1_21_FN,	FN_IP3_20_19,
   2117		GP_1_20_FN,	FN_IP3_18_16,
   2118		GP_1_19_FN,	FN_IP3_15_13,
   2119		GP_1_18_FN,	FN_IP3_12_10,
   2120		GP_1_17_FN,	FN_IP3_9_8,
   2121		GP_1_16_FN,	FN_IP3_7_5,
   2122		GP_1_15_FN,	FN_IP3_4_2,
   2123		GP_1_14_FN,	FN_IP3_1_0,
   2124		GP_1_13_FN,	FN_IP2_31,
   2125		GP_1_12_FN,	FN_IP2_30,
   2126		GP_1_11_FN,	FN_IP2_17,
   2127		GP_1_10_FN,	FN_IP2_16_14,
   2128		GP_1_9_FN,	FN_IP2_13_12,
   2129		GP_1_8_FN,	FN_IP2_11_9,
   2130		GP_1_7_FN,	FN_IP2_8_6,
   2131		GP_1_6_FN,	FN_IP2_5_3,
   2132		GP_1_5_FN,	FN_IP2_2_0,
   2133		GP_1_4_FN,	FN_IP1_29_28,
   2134		GP_1_3_FN,	FN_IP1_27_25,
   2135		GP_1_2_FN,	FN_IP1_24,
   2136		GP_1_1_FN,	FN_WE0,
   2137		GP_1_0_FN,	FN_IP1_23_21 ))
   2138	},
   2139	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
   2140		GP_2_31_FN,	FN_IP6_7,
   2141		GP_2_30_FN,	FN_IP6_6_5,
   2142		GP_2_29_FN,	FN_IP6_4_2,
   2143		GP_2_28_FN,	FN_IP6_1_0,
   2144		GP_2_27_FN,	FN_IP5_30_29,
   2145		GP_2_26_FN,	FN_IP5_28_26,
   2146		GP_2_25_FN,	FN_IP5_25_23,
   2147		GP_2_24_FN,	FN_IP5_22_21,
   2148		GP_2_23_FN,	FN_AUDIO_CLKB,
   2149		GP_2_22_FN,	FN_AUDIO_CLKA,
   2150		GP_2_21_FN,	FN_IP5_20_18,
   2151		GP_2_20_FN,	FN_IP5_17_15,
   2152		GP_2_19_FN,	FN_IP5_14_13,
   2153		GP_2_18_FN,	FN_IP5_12,
   2154		GP_2_17_FN,	FN_IP5_11_10,
   2155		GP_2_16_FN,	FN_IP5_9_8,
   2156		GP_2_15_FN,	FN_IP5_7,
   2157		GP_2_14_FN,	FN_IP5_6,
   2158		GP_2_13_FN,	FN_IP5_5_4,
   2159		GP_2_12_FN,	FN_IP5_3_2,
   2160		GP_2_11_FN,	FN_IP5_1_0,
   2161		GP_2_10_FN,	FN_IP4_30_29,
   2162		GP_2_9_FN,	FN_IP4_28_27,
   2163		GP_2_8_FN,	FN_IP4_26_25,
   2164		GP_2_7_FN,	FN_IP4_24_21,
   2165		GP_2_6_FN,	FN_IP4_20_17,
   2166		GP_2_5_FN,	FN_IP4_16_15,
   2167		GP_2_4_FN,	FN_IP4_14_13,
   2168		GP_2_3_FN,	FN_IP4_12_11,
   2169		GP_2_2_FN,	FN_IP4_10_9,
   2170		GP_2_1_FN,	FN_IP4_8,
   2171		GP_2_0_FN,	FN_IP4_7 ))
   2172	},
   2173	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
   2174		GP_3_31_FN,	FN_IP8_10_9,
   2175		GP_3_30_FN,	FN_IP8_8_6,
   2176		GP_3_29_FN,	FN_IP8_5_3,
   2177		GP_3_28_FN,	FN_IP8_2_0,
   2178		GP_3_27_FN,	FN_IP7_31_29,
   2179		GP_3_26_FN,	FN_IP7_28_25,
   2180		GP_3_25_FN,	FN_IP7_24_22,
   2181		GP_3_24_FN,	FN_IP7_21,
   2182		GP_3_23_FN,	FN_IP7_20_18,
   2183		GP_3_22_FN,	FN_IP7_17_15,
   2184		GP_3_21_FN,	FN_IP7_14_12,
   2185		GP_3_20_FN,	FN_IP7_11_9,
   2186		GP_3_19_FN,	FN_IP7_8_6,
   2187		GP_3_18_FN,	FN_IP7_5_4,
   2188		GP_3_17_FN,	FN_IP7_3_2,
   2189		GP_3_16_FN,	FN_IP7_1_0,
   2190		GP_3_15_FN,	FN_IP6_31_30,
   2191		GP_3_14_FN,	FN_IP6_29_28,
   2192		GP_3_13_FN,	FN_IP6_27_26,
   2193		GP_3_12_FN,	FN_IP6_25_24,
   2194		GP_3_11_FN,	FN_IP6_23_22,
   2195		GP_3_10_FN,	FN_IP6_21,
   2196		GP_3_9_FN,	FN_IP6_20_19,
   2197		GP_3_8_FN,	FN_IP6_18_17,
   2198		GP_3_7_FN,	FN_IP6_16,
   2199		GP_3_6_FN,	FN_IP6_15_14,
   2200		GP_3_5_FN,	FN_IP6_13,
   2201		GP_3_4_FN,	FN_IP6_12_11,
   2202		GP_3_3_FN,	FN_IP6_10,
   2203		GP_3_2_FN,	FN_SSI_SCK34,
   2204		GP_3_1_FN,	FN_IP6_9,
   2205		GP_3_0_FN,	FN_IP6_8 ))
   2206	},
   2207	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
   2208		0, 0,
   2209		0, 0,
   2210		0, 0,
   2211		0, 0,
   2212		0, 0,
   2213		GP_4_26_FN,	FN_AVS2,
   2214		GP_4_25_FN,	FN_AVS1,
   2215		GP_4_24_FN,	FN_IP10_24_22,
   2216		GP_4_23_FN,	FN_IP10_21_19,
   2217		GP_4_22_FN,	FN_IP10_18_16,
   2218		GP_4_21_FN,	FN_IP10_15_13,
   2219		GP_4_20_FN,	FN_IP10_12_9,
   2220		GP_4_19_FN,	FN_IP10_8_6,
   2221		GP_4_18_FN,	FN_IP10_5_3,
   2222		GP_4_17_FN,	FN_IP10_2_0,
   2223		GP_4_16_FN,	FN_IP9_29_27,
   2224		GP_4_15_FN,	FN_IP9_26_24,
   2225		GP_4_14_FN,	FN_IP9_23_21,
   2226		GP_4_13_FN,	FN_IP9_20_18,
   2227		GP_4_12_FN,	FN_IP9_17_15,
   2228		GP_4_11_FN,	FN_IP9_14_12,
   2229		GP_4_10_FN,	FN_IP9_11_9,
   2230		GP_4_9_FN,	FN_IP9_8_6,
   2231		GP_4_8_FN,	FN_IP9_5_3,
   2232		GP_4_7_FN,	FN_IP9_2_0,
   2233		GP_4_6_FN,	FN_IP8_29_27,
   2234		GP_4_5_FN,	FN_IP8_26_24,
   2235		GP_4_4_FN,	FN_IP8_23_22,
   2236		GP_4_3_FN,	FN_IP8_21_19,
   2237		GP_4_2_FN,	FN_IP8_18_16,
   2238		GP_4_1_FN,	FN_IP8_15_14,
   2239		GP_4_0_FN,	FN_IP8_13_11 ))
   2240	},
   2241
   2242	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
   2243			     GROUP(-1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
   2244				   1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
   2245			     GROUP(
   2246		/* IP0_31 [1] RESERVED */
   2247		/* IP0_30 [1] */
   2248		FN_A19,	0,
   2249		/* IP0_29 [1] */
   2250		FN_A18,	0,
   2251		/* IP0_28 [1] */
   2252		FN_A17,	0,
   2253		/* IP0_27 [1] */
   2254		FN_A16,	0,
   2255		/* IP0_26 [1] */
   2256		FN_A15,	0,
   2257		/* IP0_25 [1] */
   2258		FN_A14,	0,
   2259		/* IP0_24 [1] */
   2260		FN_A13,	0,
   2261		/* IP0_23 [1] */
   2262		FN_A12,	0,
   2263		/* IP0_22 [1] */
   2264		FN_A11,	0,
   2265		/* IP0_21 [1] */
   2266		FN_A10,	0,
   2267		/* IP0_20 [1] */
   2268		FN_A9,	0,
   2269		/* IP0_19 [1] */
   2270		FN_A8,	0,
   2271		/* IP0_18 [1] */
   2272		FN_A7,	0,
   2273		/* IP0_17 [1] */
   2274		FN_A6,	0,
   2275		/* IP0_16 [1] */
   2276		FN_A5,	0,
   2277		/* IP0_15 [1] */
   2278		FN_A4,	0,
   2279		/* IP0_14_12 [3] */
   2280		FN_SD1_DAT3_A,	FN_MMC_D3,	0,		FN_A0,
   2281		FN_ATAG0_A,	0,		FN_REMOCON_B,	0,
   2282		/* IP0_11_8 [4] */
   2283		FN_SD1_DAT2_A,	FN_MMC_D2,	0,		FN_BS,
   2284		FN_ATADIR0_A,	0,		FN_SDSELF_A,	0,
   2285		FN_PWM4_B,	0,		0,		0,
   2286		0,		0,		0,		0,
   2287		/* IP0_7_5 [3] */
   2288		FN_AUDATA1,	FN_ARM_TRACEDATA_1,	FN_GPSIN_C,	FN_USB_OVC1,
   2289		FN_RX2_E,	FN_SCL2_B,		0,		0,
   2290		/* IP0_4_2 [3] */
   2291		FN_AUDATA0,	FN_ARM_TRACEDATA_0,	FN_GPSCLK_C,	FN_USB_OVC0,
   2292		FN_TX2_E,	FN_SDA2_B,		0,		0,
   2293		/* IP0_1_0 [2] */
   2294		FN_PRESETOUT,	0,	FN_PWM1,	0,
   2295		))
   2296	},
   2297	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
   2298			     GROUP(-2, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
   2299				   3, 1, 1),
   2300			     GROUP(
   2301		/* IP1_31_30 [2] RESERVED */
   2302		/* IP1_29_28 [2] */
   2303		FN_EX_CS1,	FN_MMC_D4,	0,	0,
   2304		/* IP1_27_25 [3] */
   2305		FN_SSI_WS1_B,	FN_EX_CS0,	FN_SCL2_A,	FN_TX3_C,
   2306		FN_TS_SCK0_A,	0,		0,		0,
   2307		/* IP1_24 [1] */
   2308		FN_WE1,		FN_ATAWR0_B,
   2309		/* IP1_23_21 [3] */
   2310		FN_MMC_D5,	FN_ATADIR0_B,	0,		FN_RD_WR,
   2311		0,		0,		0,		0,
   2312		/* IP1_20_18 [3] */
   2313		FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
   2314		FN_SCK2_B,	0,		0,		0,
   2315		/* IP1_17 [1] */
   2316		FN_CS0,		FN_HSPI_RX1_B,
   2317		/* IP1_16_15 [2] */
   2318		FN_CLKOUT,	FN_HSPI_TX1_B,	FN_PWM0_B,	0,
   2319		/* IP1_14_11 [4] */
   2320		FN_SD1_WP_A,	FN_MMC_D7,	0,		FN_A25,
   2321		FN_DACK1_A,	0,		FN_HCTS0_B,	FN_RX3_C,
   2322		FN_TS_SDAT0_A,	0,		0,		0,
   2323		0,		0,		0,		0,
   2324		/* IP1_10_8 [3] */
   2325		FN_SD1_CD_A,	FN_MMC_D6,	0,		FN_A24,
   2326		FN_DREQ1_A,	0,		FN_HRX0_B,	FN_TS_SPSYNC0_A,
   2327		/* IP1_7_5 [3] */
   2328		FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
   2329		FN_TS_SDEN0_A,	0,		0,		0,
   2330		/* IP1_4_2 [3] */
   2331		FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
   2332		0,		0,		0,		0,
   2333		/* IP1_1 [1] */
   2334		FN_A21,		FN_HSPI_CLK1_B,
   2335		/* IP1_0 [1] */
   2336		FN_A20,		FN_HSPI_CS1_B,
   2337		))
   2338	},
   2339	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
   2340			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
   2341				   1, 1, 1, 3, 2, 3, 3, 3, 3),
   2342			     GROUP(
   2343		/* IP2_31 [1] */
   2344		FN_MLB_CLK,	FN_IRQ1_A,
   2345		/* IP2_30 [1] */
   2346		FN_RD_WR_B,	FN_IRQ0,
   2347		/* IP2_29 [1] */
   2348		FN_D11,		0,
   2349		/* IP2_28 [1] */
   2350		FN_D10,		0,
   2351		/* IP2_27 [1] */
   2352		FN_D9,		0,
   2353		/* IP2_26 [1] */
   2354		FN_D8,		0,
   2355		/* IP2_25 [1] */
   2356		FN_D7,		0,
   2357		/* IP2_24 [1] */
   2358		FN_D6,		0,
   2359		/* IP2_23 [1] */
   2360		FN_D5,		0,
   2361		/* IP2_22 [1] */
   2362		FN_D4,		0,
   2363		/* IP2_21 [1] */
   2364		FN_D3,		0,
   2365		/* IP2_20 [1] */
   2366		FN_D2,		0,
   2367		/* IP2_19 [1] */
   2368		FN_D1,		0,
   2369		/* IP2_18 [1] */
   2370		FN_D0,		0,
   2371		/* IP2_17 [1] */
   2372		FN_EX_WAIT0,	FN_PWM0_C,
   2373		/* IP2_16_14 [3] */
   2374		FN_DACK0,	0,	0,	FN_TX3_A,
   2375		FN_DRACK0,	0,	0,	0,
   2376		/* IP2_13_12 [2] */
   2377		FN_DREQ0_A,	0,	0,	FN_RX3_A,
   2378		/* IP2_11_9 [3] */
   2379		FN_SD1_DAT1_A,	FN_MMC_D1,	0,	FN_ATAWR0_A,
   2380		FN_EX_CS5,	FN_EX_WAIT2_A,	0,	0,
   2381		/* IP2_8_6 [3] */
   2382		FN_SD1_DAT0_A,	FN_MMC_D0,	0,	FN_ATARD0,
   2383		FN_EX_CS4,	FN_EX_WAIT1_A,	0,	0,
   2384		/* IP2_5_3 [3] */
   2385		FN_SD1_CMD_A,	FN_MMC_CMD,	0,	FN_ATACS10,
   2386		FN_EX_CS3,	0,		0,	0,
   2387		/* IP2_2_0 [3] */
   2388		FN_SD1_CLK_A,	FN_MMC_CLK,	0,	FN_ATACS00,
   2389		FN_EX_CS2,	0,		0,	0,
   2390		))
   2391	},
   2392	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
   2393			     GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
   2394				   3, 3, 2),
   2395			     GROUP(
   2396		/* IP3_31 [1] */
   2397		FN_DU0_DR6,	FN_LCDOUT6,
   2398		/* IP3_30 [1] */
   2399		FN_DU0_DR5,	FN_LCDOUT5,
   2400		/* IP3_29 [1] */
   2401		FN_DU0_DR4,	FN_LCDOUT4,
   2402		/* IP3_28 [1] */
   2403		FN_DU0_DR3,	FN_LCDOUT3,
   2404		/* IP3_27 [1] */
   2405		FN_DU0_DR2,	FN_LCDOUT2,
   2406		/* IP3_26_24 [3] */
   2407		FN_SSI_WS4,		FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,
   2408		FN_ARM_TRACEDATA_3,	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
   2409		/* IP3_23_21 [3] */
   2410		FN_SSI_SCK4,		FN_DU0_DR0,	FN_LCDOUT0,	FN_AUDATA2,
   2411		FN_ARM_TRACEDATA_2,	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,
   2412		/* IP3_20_19 [2] */
   2413		FN_SD1_DAT3_B,	FN_HRTS0_A,	FN_RTS0,	0,
   2414		/* IP3_18_16 [3] */
   2415		FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	0,
   2416		0,		0,		0,		0,
   2417		/* IP3_15_13 [3] */
   2418		FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
   2419		0,		0,		0,		0,
   2420		/* IP3_12_10 [3] */
   2421		FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,	0,
   2422		0,		0,		0,		0,
   2423		/* IP3_9_8 [2] */
   2424		FN_SD1_CLK_B,	FN_HTX0_A,	FN_TX0_A,	0,
   2425		/* IP3_7_5 [3] */
   2426		FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,	FN_CAN_CLK_B,
   2427		FN_SDA3_B,	0,		0,			0,
   2428		/* IP3_4_2 [3] */
   2429		FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
   2430		FN_SDSELF_B,	0,		0,		0,
   2431		/* IP3_1_0 [2] */
   2432		FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
   2433		))
   2434	},
   2435	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
   2436			     GROUP(-1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
   2437				   3, 3, 1),
   2438			     GROUP(
   2439		/* IP4_31 [1] RESERVED */
   2440		/* IP4_30_29 [2] */
   2441		FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,	0,
   2442		/* IP4_28_27 [2] */
   2443		FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,	0,
   2444		/* IP4_26_25 [2] */
   2445		FN_VI0_R2_B,	FN_DU0_DB2,	FN_LCDOUT18,	0,
   2446		/* IP4_24_21 [4] */
   2447		FN_AUDIO_CLKC,	FN_VI0_R1_B,		FN_DU0_DB1,	FN_LCDOUT17,
   2448		FN_AUDATA7,	FN_ARM_TRACEDATA_7,	FN_GPSIN_A,	0,
   2449		FN_ADICS_SAMP,	FN_TS_SCK0_B,		0,		0,
   2450		0,		0,			0,		0,
   2451		/* IP4_20_17 [4] */
   2452		FN_SSI_SCK2_B,	FN_VI0_R0_B,		FN_DU0_DB0,	FN_LCDOUT16,
   2453		FN_AUDATA6,	FN_ARM_TRACEDATA_6,	FN_GPSCLK_A,	FN_PWM0_A,
   2454		FN_ADICLK,	FN_TS_SDAT0_B,		0,		0,
   2455		0,		0,			0,		0,
   2456		/* IP4_16_15 [2] */
   2457		FN_DU0_DG7,	FN_LCDOUT15,	FN_TX4_A,	0,
   2458		/* IP4_14_13 [2] */
   2459		FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	0,
   2460		/* IP4_12_11 [2] */
   2461		FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,	0,
   2462		/* IP4_10_9 [2] */
   2463		FN_DU0_DG4,	FN_LCDOUT12,	FN_RX0_B,	0,
   2464		/* IP4_8 [1] */
   2465		FN_DU0_DG3,	FN_LCDOUT11,
   2466		/* IP4_7 [1] */
   2467		FN_DU0_DG2,	FN_LCDOUT10,
   2468		/* IP4_6_4 [3] */
   2469		FN_DU0_DG1,	FN_LCDOUT9,	FN_AUDATA5,	FN_ARM_TRACEDATA_5,
   2470		FN_RX1_D,	FN_CAN0_RX_A,	FN_ADIDATA,	0,
   2471		/* IP4_3_1 [3] */
   2472		FN_DU0_DG0,	FN_LCDOUT8,	FN_AUDATA4,	FN_ARM_TRACEDATA_4,
   2473		FN_TX1_D,	FN_CAN0_TX_A,	FN_ADICHS0,	0,
   2474		/* IP4_0 [1] */
   2475		FN_DU0_DR7,	FN_LCDOUT7,
   2476		))
   2477	},
   2478	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
   2479			     GROUP(-1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
   2480				   1, 2, 2, 2),
   2481			     GROUP(
   2482
   2483		/* IP5_31 [1] RESERVED */
   2484		/* IP5_30_29 [2] */
   2485		FN_SSI_SDATA7,	FN_HSPI_TX0_B,	FN_RX2_A,	FN_CAN0_RX_B,
   2486		/* IP5_28_26 [3] */
   2487		FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,	FN_TX2_A,
   2488		FN_CAN0_TX_B,	0,		0,		0,
   2489		/* IP5_25_23 [3] */
   2490		FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
   2491		FN_CAN_CLK_D,	0,		0,		0,
   2492		/* IP5_22_21 [2] */
   2493		FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
   2494		/* IP5_20_18 [3] */
   2495		FN_SSI_WS1_A,		FN_DU0_CDE,	FN_QPOLB,	FN_AUDSYNC,
   2496		FN_ARM_TRACECTL,	FN_FMIN_D,	0,		0,
   2497		/* IP5_17_15 [3] */
   2498		FN_SSI_SCK1_A,		FN_DU0_DISP,	FN_QPOLA,	FN_AUDCK,
   2499		FN_ARM_TRACECLK,	FN_BPFCLK_D,	0,		0,
   2500		/* IP5_14_13 [2] */
   2501		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,	FN_QCPV_QDE,
   2502		FN_FMCLK_D,				0,
   2503		/* IP5_12 [1] */
   2504		FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
   2505		/* IP5_11_10 [2] */
   2506		FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
   2507		FN_QSTH_QHS,	0,
   2508		/* IP5_9_8 [2] */
   2509		FN_DU0_DOTCLKO_UT1,	FN_QSTVB_QVE,
   2510		FN_AUDIO_CLKOUT_A,	FN_REMOCON_C,
   2511		/* IP5_7 [1] */
   2512		FN_DU0_DOTCLKO_UT0,	FN_QCLK,
   2513		/* IP5_6 [1] */
   2514		FN_DU0_DOTCLKIN,	FN_QSTVA_QVS,
   2515		/* IP5_5_4 [2] */
   2516		FN_VI1_DATA11_B,	FN_DU0_DB7,	FN_LCDOUT23,	0,
   2517		/* IP5_3_2 [2] */
   2518		FN_VI1_DATA10_B,	FN_DU0_DB6,	FN_LCDOUT22,	0,
   2519		/* IP5_1_0 [2] */
   2520		FN_VI0_R5_B,		FN_DU0_DB5,	FN_LCDOUT21,	0,
   2521		))
   2522	},
   2523	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
   2524			     GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
   2525				   1, 1, 1, 1, 2, 3, 2),
   2526			     GROUP(
   2527		/* IP6_31_30 [2] */
   2528		FN_SD0_DAT2,	0,	FN_SUB_TDI,	0,
   2529		/* IP6_29_28 [2] */
   2530		FN_SD0_DAT1,	0,	FN_SUB_TCK,	0,
   2531		/* IP6_27_26 [2] */
   2532		FN_SD0_DAT0,	0,	FN_SUB_TMS,	0,
   2533		/* IP6_25_24 [2] */
   2534		FN_SD0_CMD,	0,	FN_SUB_TRST,	0,
   2535		/* IP6_23_22 [2] */
   2536		FN_SD0_CLK,	0,	FN_SUB_TDO,	0,
   2537		/* IP6_21 [1] */
   2538		FN_SSI_SDATA0,		FN_ARM_TRACEDATA_15,
   2539		/* IP6_20_19 [2] */
   2540		FN_SSI_SDATA1,		FN_ARM_TRACEDATA_14,
   2541		FN_SCL1_A,		FN_SCK2_A,
   2542		/* IP6_18_17 [2] */
   2543		FN_SSI_SDATA2,		FN_HSPI_CS2_A,
   2544		FN_ARM_TRACEDATA_13,	FN_SDA1_A,
   2545		/* IP6_16 [1] */
   2546		FN_SSI_WS012,		FN_ARM_TRACEDATA_12,
   2547		/* IP6_15_14 [2] */
   2548		FN_SSI_SCK012,		FN_ARM_TRACEDATA_11,
   2549		FN_TX0_D,		0,
   2550		/* IP6_13 [1] */
   2551		FN_SSI_SDATA3,		FN_ARM_TRACEDATA_10,
   2552		/* IP6_12_11 [2] */
   2553		FN_SSI_SDATA4,		FN_SSI_WS2_A,
   2554		FN_ARM_TRACEDATA_9,	0,
   2555		/* IP6_10 [1] */
   2556		FN_SSI_WS34,		FN_ARM_TRACEDATA_8,
   2557		/* IP6_9 [1] */
   2558		FN_SSI_SDATA5,		FN_RX0_D,
   2559		/* IP6_8 [1] */
   2560		FN_SSI_WS5,		FN_TX4_C,
   2561		/* IP6_7 [1] */
   2562		FN_SSI_SCK5,		FN_RX4_C,
   2563		/* IP6_6_5 [2] */
   2564		FN_SSI_SDATA6,		FN_HSPI_TX2_A,
   2565		FN_FMIN_B,		0,
   2566		/* IP6_4_2 [3] */
   2567		FN_SSI_WS6,		FN_HSPI_CLK2_A,
   2568		FN_BPFCLK_B,		FN_CAN1_RX_B,
   2569		0,	0,	0,	0,
   2570		/* IP6_1_0 [2] */
   2571		FN_SSI_SCK6,		FN_HSPI_RX2_A,
   2572		FN_FMCLK_B,		FN_CAN1_TX_B,
   2573		))
   2574	},
   2575	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
   2576			     GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
   2577			     GROUP(
   2578
   2579		/* IP7_31_29 [3] */
   2580		FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,	FN_DU1_DR2,
   2581		0,		FN_HSPI_CS1_A,	FN_RX3_B,	0,
   2582		/* IP7_28_25 [4] */
   2583		FN_VI0_FIELD,	FN_SD2_DAT3_B,	FN_VI0_R3_C,	FN_VI1_DATA1,
   2584		FN_DU1_DG7,	0,		FN_HSPI_CLK1_A,	FN_TX4_B,
   2585		0,	0,	0,	0,
   2586		0,	0,	0,	0,
   2587		/* IP7_24_22 [3] */
   2588		FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
   2589		0,		FN_HSPI_RX1_A,	FN_RX4_B,	0,
   2590		/* IP7_21 [1] */
   2591		FN_VI0_CLK,	FN_CAN_CLK_A,
   2592		/* IP7_20_18 [3] */
   2593		FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	0,
   2594		FN_IRQ2_C,	FN_CTS1_C,	FN_SPEEDIN,	0,
   2595		/* IP7_17_15 [3] */
   2596		FN_VI1_VSYNC,	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,
   2597		0,		FN_TX1_C,	0,		0,
   2598		/* IP7_14_12 [3] */
   2599		FN_VI1_HSYNC,	FN_HSPI_RX0_A,	FN_HRTS1_A,	FN_FMCLK_A,
   2600		0,		FN_RX1_C,	0,		0,
   2601		/* IP7_11_9 [3] */
   2602		FN_VI1_FIELD,	FN_HSPI_CS0_A,	FN_HRX1_A,	0,
   2603		FN_SCK1_C,	0,		0,		0,
   2604		/* IP7_8_6 [3] */
   2605		FN_VI1_CLKENB,	FN_HSPI_CLK0_A,	FN_HTX1_A,	0,
   2606		FN_RTS1_C,	0,		0,		0,
   2607		/* IP7_5_4 [2] */
   2608		FN_SD0_WP,	0,		FN_RX5_A,	0,
   2609		/* IP7_3_2 [2] */
   2610		FN_SD0_CD,	0,		FN_TX5_A,	0,
   2611		/* IP7_1_0 [2] */
   2612		FN_SD0_DAT3,	0,		FN_IRQ1_B,	0,
   2613		))
   2614	},
   2615	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
   2616			     GROUP(-2, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
   2617			     GROUP(
   2618		/* IP8_31_30 [2] RESERVED */
   2619		/* IP8_29_27 [3] */
   2620		FN_VI0_G3,	FN_SD2_CMD_B,	FN_VI1_DATA5,	FN_DU1_DR5,
   2621		0,		FN_HRX1_B,	0,		0,
   2622		/* IP8_26_24 [3] */
   2623		FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,	FN_DU1_DR4,
   2624		0,		FN_HTX1_B,	0,		0,
   2625		/* IP8_23_22 [2] */
   2626		FN_VI0_DATA7_VI0_G1,	FN_DU1_DB5,
   2627		FN_RTS1_A,		0,
   2628		/* IP8_21_19 [3] */
   2629		FN_VI0_DATA6_VI0_G0,	FN_DU1_DB4,
   2630		FN_CTS1_A,		FN_PWM5,
   2631		0,	0,	0,	0,
   2632		/* IP8_18_16 [3] */
   2633		FN_VI0_DATA5_VI0_B5,	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,
   2634		0,			FN_HSCK1_B,	0,		0,
   2635		/* IP8_15_14 [2] */
   2636		FN_VI0_DATA4_VI0_B4,	FN_DU1_DB2,	FN_RX1_A,	0,
   2637		/* IP8_13_11 [3] */
   2638		FN_VI0_DATA3_VI0_B3,	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,
   2639		0,			 0,		0,		0,
   2640		/* IP8_10_9 [2] */
   2641		FN_VI0_DATA2_VI0_B2,	FN_DU1_DG4,	FN_RX0_C,	0,
   2642		/* IP8_8_6 [3] */
   2643		FN_VI0_DATA1_VI0_B1,	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,
   2644		0,			 0,		0,		0,
   2645		/* IP8_5_3 [3] */
   2646		FN_VI0_DATA0_VI0_B0,	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,
   2647		0,			 0,		0,		0,
   2648		/* IP8_2_0 [3] */
   2649		FN_VI0_VSYNC,		FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
   2650		0,			FN_HSPI_TX1_A,	FN_TX3_B,	0,
   2651		))
   2652	},
   2653	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
   2654			     GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
   2655			     GROUP(
   2656		/* IP9_31_30 [2] RESERVED */
   2657		/* IP9_29_27 [3] */
   2658		FN_VI1_DATA11_A,	FN_DU1_EXHSYNC_DU1_HSYNC,
   2659		FN_ETH_RXD1,		FN_FMIN_C,
   2660		0,			FN_RX2_D,
   2661		FN_SCL2_C,		0,
   2662		/* IP9_26_24 [3] */
   2663		FN_VI1_DATA10_A,	FN_DU1_DOTCLKOUT,
   2664		FN_ETH_RXD0,		FN_BPFCLK_C,
   2665		0,			FN_TX2_D,
   2666		FN_SDA2_C,		0,
   2667		/* IP9_23_21 [3] */
   2668		FN_VI0_R5_A,	0,		FN_ETH_RX_ER,	FN_FMCLK_C,
   2669		FN_IERX,	FN_RX2_C,	0,		0,
   2670		/* IP9_20_18 [3] */
   2671		FN_VI0_R4_A,	FN_ETH_TX_EN,	0,		0,
   2672		FN_IETX,	FN_TX2_C,	0,		0,
   2673		/* IP9_17_15 [3] */
   2674		FN_VI0_R3_A,	FN_ETH_CRS_DV,	0,		FN_IECLK,
   2675		FN_SCK2_C,	0,		0,		0,
   2676		/* IP9_14_12 [3] */
   2677		FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,	FN_ETH_TXD1,
   2678		0,		FN_PWM3,	0,		0,
   2679		/* IP9_11_9 [3] */
   2680		FN_VI0_R1_A,	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,
   2681		0,		FN_PWM2,	FN_TCLK1,	0,
   2682		/* IP9_8_6 [3] */
   2683		FN_VI0_R0_A,	FN_VI1_CLK,	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,
   2684		0,		0,		0,		0,
   2685		/* IP9_5_3 [3] */
   2686		FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,	FN_DU1_DR7,
   2687		0,		FN_HCTS1_B,	0,		0,
   2688		/* IP9_2_0 [3] */
   2689		FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
   2690		0,		FN_HRTS1_B,	0,		0,
   2691		))
   2692	},
   2693	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
   2694			     GROUP(-7, 3, 3, 3, 3, 4, 3, 3, 3),
   2695			     GROUP(
   2696
   2697		/* IP10_31_25 [7] RESERVED */
   2698		/* IP10_24_22 [3] */
   2699		FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,	FN_DACK0_B,
   2700		FN_HSPI_TX2_B,	FN_CAN_CLK_C,	0,		0,
   2701		/* IP10_21_19 [3] */
   2702		FN_SD2_CD_A,	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,
   2703		FN_HSPI_RX2_B,	FN_REMOCON_A,	0,		0,
   2704		/* IP10_18_16 [3] */
   2705		FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,	FN_ATAG1,
   2706		FN_HSPI_CS2_B,	FN_GPSIN_B,	0,		0,
   2707		/* IP10_15_13 [3] */
   2708		FN_SD2_DAT2_A,	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,
   2709		FN_HSPI_CLK2_B,	FN_GPSCLK_B,	0,		0,
   2710		/* IP10_12_9 [4] */
   2711		FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
   2712		FN_ETH_MAGIC,	FN_CAN1_TX_A,	0,		FN_PWM6,
   2713		0, 0, 0, 0,
   2714		0, 0, 0, 0,
   2715		/* IP10_8_6 [3] */
   2716		FN_SD2_DAT0_A,	FN_DU1_DISP,	FN_ATACS01,	FN_DREQ1_B,
   2717		FN_ETH_LINK,	FN_CAN1_RX_A,	0,		0,
   2718		/* IP10_5_3 [3] */
   2719		FN_SD2_CMD_A,	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
   2720		FN_ATAWR1,	FN_ETH_MDIO,
   2721		FN_SCL1_B,	0,
   2722		0,		0,
   2723		/* IP10_2_0 [3] */
   2724		FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,
   2725		FN_ATARD1,	FN_ETH_MDC,
   2726		FN_SDA1_B,	0,
   2727		0,		0,
   2728		))
   2729	},
   2730	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
   2731			     GROUP(-1, 1, 2, 2, 3, 2, 2, -1, 1, 1, 1, 2,
   2732				   -1, 1, 1, 1, 2, 1, -1, 1, 1, 1, 1, 1),
   2733			     GROUP(
   2734
   2735		/* SEL 31  [1] RESERVED */
   2736		/* SEL_30 (SCIF5) [1] */
   2737		FN_SEL_SCIF5_A,		FN_SEL_SCIF5_B,
   2738		/* SEL_29_28 (SCIF4) [2] */
   2739		FN_SEL_SCIF4_A,		FN_SEL_SCIF4_B,
   2740		FN_SEL_SCIF4_C,		0,
   2741		/* SEL_27_26 (SCIF3) [2] */
   2742		FN_SEL_SCIF3_A,		FN_SEL_SCIF3_B,
   2743		FN_SEL_SCIF3_C,		FN_SEL_SCIF3_D,
   2744		/* SEL_25_23 (SCIF2) [3] */
   2745		FN_SEL_SCIF2_A,		FN_SEL_SCIF2_B,
   2746		FN_SEL_SCIF2_C,		FN_SEL_SCIF2_D,
   2747		FN_SEL_SCIF2_E,		0,
   2748		0,			0,
   2749		/* SEL_22_21 (SCIF1) [2] */
   2750		FN_SEL_SCIF1_A,		FN_SEL_SCIF1_B,
   2751		FN_SEL_SCIF1_C,		FN_SEL_SCIF1_D,
   2752		/* SEL_20_19 (SCIF0) [2] */
   2753		FN_SEL_SCIF0_A,		FN_SEL_SCIF0_B,
   2754		FN_SEL_SCIF0_C,		FN_SEL_SCIF0_D,
   2755		/* SEL_18 [1] RESERVED */
   2756		/* SEL_17 (SSI2) [1] */
   2757		FN_SEL_SSI2_A,		FN_SEL_SSI2_B,
   2758		/* SEL_16 (SSI1) [1] */
   2759		FN_SEL_SSI1_A,		FN_SEL_SSI1_B,
   2760		/* SEL_15 (VI1) [1] */
   2761		FN_SEL_VI1_A,		FN_SEL_VI1_B,
   2762		/* SEL_14_13 (VI0) [2] */
   2763		FN_SEL_VI0_A,		FN_SEL_VI0_B,
   2764		FN_SEL_VI0_C,		FN_SEL_VI0_D,
   2765		/* SEL_12 [1] RESERVED */
   2766		/* SEL_11 (SD2) [1] */
   2767		FN_SEL_SD2_A,		FN_SEL_SD2_B,
   2768		/* SEL_10 (SD1) [1] */
   2769		FN_SEL_SD1_A,		FN_SEL_SD1_B,
   2770		/* SEL_9 (IRQ3) [1] */
   2771		FN_SEL_IRQ3_A,		FN_SEL_IRQ3_B,
   2772		/* SEL_8_7 (IRQ2) [2] */
   2773		FN_SEL_IRQ2_A,		FN_SEL_IRQ2_B,
   2774		FN_SEL_IRQ2_C,		0,
   2775		/* SEL_6 (IRQ1) [1] */
   2776		FN_SEL_IRQ1_A,		FN_SEL_IRQ1_B,
   2777		/* SEL_5 [1] RESERVED */
   2778		/* SEL_4 (DREQ2) [1] */
   2779		FN_SEL_DREQ2_A,		FN_SEL_DREQ2_B,
   2780		/* SEL_3 (DREQ1) [1] */
   2781		FN_SEL_DREQ1_A,		FN_SEL_DREQ1_B,
   2782		/* SEL_2 (DREQ0) [1] */
   2783		FN_SEL_DREQ0_A,		FN_SEL_DREQ0_B,
   2784		/* SEL_1 (WAIT2) [1] */
   2785		FN_SEL_WAIT2_A,		FN_SEL_WAIT2_B,
   2786		/* SEL_0 (WAIT1) [1] */
   2787		FN_SEL_WAIT1_A,		FN_SEL_WAIT1_B,
   2788		))
   2789	},
   2790	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
   2791			     GROUP(-4, 1, 1, 2, 1, 1, -7,
   2792				   2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
   2793			     GROUP(
   2794
   2795		/* SEL_31_28 [4] RESERVED */
   2796		/* SEL_27 (CAN1) [1] */
   2797		FN_SEL_CAN1_A,		FN_SEL_CAN1_B,
   2798		/* SEL_26 (CAN0) [1] */
   2799		FN_SEL_CAN0_A,		FN_SEL_CAN0_B,
   2800		/* SEL_25_24 (CANCLK) [2] */
   2801		FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
   2802		FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
   2803		/* SEL_23 (HSCIF1) [1] */
   2804		FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
   2805		/* SEL_22 (HSCIF0) [1] */
   2806		FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
   2807		/* SEL_21_15 [7] RESERVED */
   2808		/* SEL_14_13 (REMOCON) [2] */
   2809		FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,
   2810		FN_SEL_REMOCON_C,	0,
   2811		/* SEL_12_11 (FM) [2] */
   2812		FN_SEL_FM_A,		FN_SEL_FM_B,
   2813		FN_SEL_FM_C,		FN_SEL_FM_D,
   2814		/* SEL_10_9 (GPS) [2] */
   2815		FN_SEL_GPS_A,		FN_SEL_GPS_B,
   2816		FN_SEL_GPS_C,		0,
   2817		/* SEL_8 (TSIF0) [1] */
   2818		FN_SEL_TSIF0_A,		FN_SEL_TSIF0_B,
   2819		/* SEL_7 (HSPI2) [1] */
   2820		FN_SEL_HSPI2_A,		FN_SEL_HSPI2_B,
   2821		/* SEL_6 (HSPI1) [1] */
   2822		FN_SEL_HSPI1_A,		FN_SEL_HSPI1_B,
   2823		/* SEL_5 (HSPI0) [1] */
   2824		FN_SEL_HSPI0_A,		FN_SEL_HSPI0_B,
   2825		/* SEL_4_3 (I2C3) [2] */
   2826		FN_SEL_I2C3_A,		FN_SEL_I2C3_B,
   2827		FN_SEL_I2C3_C,		0,
   2828		/* SEL_2_1 (I2C2) [2] */
   2829		FN_SEL_I2C2_A,		FN_SEL_I2C2_B,
   2830		FN_SEL_I2C2_C,		0,
   2831		/* SEL_0 (I2C1) [1] */
   2832		FN_SEL_I2C1_A,		FN_SEL_I2C1_B,
   2833		))
   2834	},
   2835	{ },
   2836};
   2837
   2838static const struct pinmux_bias_reg pinmux_bias_regs[] = {
   2839	{ PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {
   2840		[ 0] = RCAR_GP_PIN(0,  6),	/* A0 */
   2841		[ 1] = RCAR_GP_PIN(0,  7),	/* A1 */
   2842		[ 2] = RCAR_GP_PIN(0,  8),	/* A2 */
   2843		[ 3] = RCAR_GP_PIN(0,  9),	/* A3 */
   2844		[ 4] = RCAR_GP_PIN(0, 10),	/* A4 */
   2845		[ 5] = RCAR_GP_PIN(0, 11),	/* A5 */
   2846		[ 6] = RCAR_GP_PIN(0, 12),	/* A6 */
   2847		[ 7] = RCAR_GP_PIN(0, 13),	/* A7 */
   2848		[ 8] = RCAR_GP_PIN(0, 14),	/* A8 */
   2849		[ 9] = RCAR_GP_PIN(0, 15),	/* A9 */
   2850		[10] = RCAR_GP_PIN(0, 16),	/* A10 */
   2851		[11] = RCAR_GP_PIN(0, 17),	/* A11 */
   2852		[12] = RCAR_GP_PIN(0, 18),	/* A12 */
   2853		[13] = RCAR_GP_PIN(0, 19),	/* A13 */
   2854		[14] = RCAR_GP_PIN(0, 20),	/* A14 */
   2855		[15] = RCAR_GP_PIN(0, 21),	/* A15 */
   2856		[16] = RCAR_GP_PIN(0, 22),	/* A16 */
   2857		[17] = RCAR_GP_PIN(0, 23),	/* A17 */
   2858		[18] = RCAR_GP_PIN(0, 24),	/* A18 */
   2859		[19] = RCAR_GP_PIN(0, 25),	/* A19 */
   2860		[20] = RCAR_GP_PIN(0, 26),	/* A20 */
   2861		[21] = RCAR_GP_PIN(0, 27),	/* A21 */
   2862		[22] = RCAR_GP_PIN(0, 28),	/* A22 */
   2863		[23] = RCAR_GP_PIN(0, 29),	/* A23 */
   2864		[24] = RCAR_GP_PIN(0, 30),	/* A24 */
   2865		[25] = RCAR_GP_PIN(0, 31),	/* A25 */
   2866		[26] = RCAR_GP_PIN(1,  3),	/* /EX_CS0 */
   2867		[27] = RCAR_GP_PIN(1,  4),	/* /EX_CS1 */
   2868		[28] = RCAR_GP_PIN(1,  5),	/* /EX_CS2 */
   2869		[29] = RCAR_GP_PIN(1,  6),	/* /EX_CS3 */
   2870		[30] = RCAR_GP_PIN(1,  7),	/* /EX_CS4 */
   2871		[31] = RCAR_GP_PIN(1,  8),	/* /EX_CS5 */
   2872	} },
   2873	{ PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {
   2874		[ 0] = RCAR_GP_PIN(0,  0),	/* /PRESETOUT	*/
   2875		[ 1] = RCAR_GP_PIN(0,  5),	/* /BS		*/
   2876		[ 2] = RCAR_GP_PIN(1,  0),	/* RD//WR	*/
   2877		[ 3] = RCAR_GP_PIN(1,  1),	/* /WE0		*/
   2878		[ 4] = RCAR_GP_PIN(1,  2),	/* /WE1		*/
   2879		[ 5] = RCAR_GP_PIN(1, 11),	/* EX_WAIT0	*/
   2880		[ 6] = RCAR_GP_PIN(1,  9),	/* DREQ0	*/
   2881		[ 7] = RCAR_GP_PIN(1, 10),	/* DACK0	*/
   2882		[ 8] = RCAR_GP_PIN(1, 12),	/* IRQ0		*/
   2883		[ 9] = RCAR_GP_PIN(1, 13),	/* IRQ1		*/
   2884		[10] = SH_PFC_PIN_NONE,
   2885		[11] = SH_PFC_PIN_NONE,
   2886		[12] = SH_PFC_PIN_NONE,
   2887		[13] = SH_PFC_PIN_NONE,
   2888		[14] = SH_PFC_PIN_NONE,
   2889		[15] = SH_PFC_PIN_NONE,
   2890		[16] = SH_PFC_PIN_NONE,
   2891		[17] = SH_PFC_PIN_NONE,
   2892		[18] = SH_PFC_PIN_NONE,
   2893		[19] = SH_PFC_PIN_NONE,
   2894		[20] = SH_PFC_PIN_NONE,
   2895		[21] = SH_PFC_PIN_NONE,
   2896		[22] = SH_PFC_PIN_NONE,
   2897		[23] = SH_PFC_PIN_NONE,
   2898		[24] = SH_PFC_PIN_NONE,
   2899		[25] = SH_PFC_PIN_NONE,
   2900		[26] = SH_PFC_PIN_NONE,
   2901		[27] = SH_PFC_PIN_NONE,
   2902		[28] = SH_PFC_PIN_NONE,
   2903		[29] = SH_PFC_PIN_NONE,
   2904		[30] = SH_PFC_PIN_NONE,
   2905		[31] = SH_PFC_PIN_NONE,
   2906	} },
   2907	{ PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {
   2908		[ 0] = RCAR_GP_PIN(1, 22),	/* DU0_DR0	*/
   2909		[ 1] = RCAR_GP_PIN(1, 23),	/* DU0_DR1	*/
   2910		[ 2] = RCAR_GP_PIN(1, 24),	/* DU0_DR2	*/
   2911		[ 3] = RCAR_GP_PIN(1, 25),	/* DU0_DR3	*/
   2912		[ 4] = RCAR_GP_PIN(1, 26),	/* DU0_DR4	*/
   2913		[ 5] = RCAR_GP_PIN(1, 27),	/* DU0_DR5	*/
   2914		[ 6] = RCAR_GP_PIN(1, 28),	/* DU0_DR6	*/
   2915		[ 7] = RCAR_GP_PIN(1, 29),	/* DU0_DR7	*/
   2916		[ 8] = RCAR_GP_PIN(1, 30),	/* DU0_DG0	*/
   2917		[ 9] = RCAR_GP_PIN(1, 31),	/* DU0_DG1	*/
   2918		[10] = RCAR_GP_PIN(2,  0),	/* DU0_DG2	*/
   2919		[11] = RCAR_GP_PIN(2,  1),	/* DU0_DG3	*/
   2920		[12] = RCAR_GP_PIN(2,  2),	/* DU0_DG4	*/
   2921		[13] = RCAR_GP_PIN(2,  3),	/* DU0_DG5	*/
   2922		[14] = RCAR_GP_PIN(2,  4),	/* DU0_DG6	*/
   2923		[15] = RCAR_GP_PIN(2,  5),	/* DU0_DG7	*/
   2924		[16] = RCAR_GP_PIN(2,  6),	/* DU0_DB0	*/
   2925		[17] = RCAR_GP_PIN(2,  7),	/* DU0_DB1	*/
   2926		[18] = RCAR_GP_PIN(2,  8),	/* DU0_DB2	*/
   2927		[19] = RCAR_GP_PIN(2,  9),	/* DU0_DB3	*/
   2928		[20] = RCAR_GP_PIN(2, 10),	/* DU0_DB4	*/
   2929		[21] = RCAR_GP_PIN(2, 11),	/* DU0_DB5	*/
   2930		[22] = RCAR_GP_PIN(2, 12),	/* DU0_DB6	*/
   2931		[23] = RCAR_GP_PIN(2, 13),	/* DU0_DB7	*/
   2932		[24] = RCAR_GP_PIN(2, 14),	/* DU0_DOTCLKIN	*/
   2933		[25] = RCAR_GP_PIN(2, 15),	/* DU0_DOTCLKOUT0 */
   2934		[26] = RCAR_GP_PIN(2, 17),	/* DU0_HSYNC	*/
   2935		[27] = RCAR_GP_PIN(2, 18),	/* DU0_VSYNC	*/
   2936		[28] = RCAR_GP_PIN(2, 19),	/* DU0_EXODDF	*/
   2937		[29] = RCAR_GP_PIN(2, 20),	/* DU0_DISP	*/
   2938		[30] = RCAR_GP_PIN(2, 21),	/* DU0_CDE	*/
   2939		[31] = RCAR_GP_PIN(2, 16),	/* DU0_DOTCLKOUT1 */
   2940	} },
   2941	{ PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {
   2942		[ 0] = RCAR_GP_PIN(3, 24),	/* VI0_CLK	*/
   2943		[ 1] = RCAR_GP_PIN(3, 25),	/* VI0_CLKENB	*/
   2944		[ 2] = RCAR_GP_PIN(3, 26),	/* VI0_FIELD	*/
   2945		[ 3] = RCAR_GP_PIN(3, 27),	/* /VI0_HSYNC	*/
   2946		[ 4] = RCAR_GP_PIN(3, 28),	/* /VI0_VSYNC	*/
   2947		[ 5] = RCAR_GP_PIN(3, 29),	/* VI0_DATA0	*/
   2948		[ 6] = RCAR_GP_PIN(3, 30),	/* VI0_DATA1	*/
   2949		[ 7] = RCAR_GP_PIN(3, 31),	/* VI0_DATA2	*/
   2950		[ 8] = RCAR_GP_PIN(4,  0),	/* VI0_DATA3	*/
   2951		[ 9] = RCAR_GP_PIN(4,  1),	/* VI0_DATA4	*/
   2952		[10] = RCAR_GP_PIN(4,  2),	/* VI0_DATA5	*/
   2953		[11] = RCAR_GP_PIN(4,  3),	/* VI0_DATA6	*/
   2954		[12] = RCAR_GP_PIN(4,  4),	/* VI0_DATA7	*/
   2955		[13] = RCAR_GP_PIN(4,  5),	/* VI0_G2	*/
   2956		[14] = RCAR_GP_PIN(4,  6),	/* VI0_G3	*/
   2957		[15] = RCAR_GP_PIN(4,  7),	/* VI0_G4	*/
   2958		[16] = RCAR_GP_PIN(4,  8),	/* VI0_G5	*/
   2959		[17] = RCAR_GP_PIN(4, 21),	/* VI1_DATA12	*/
   2960		[18] = RCAR_GP_PIN(4, 22),	/* VI1_DATA13	*/
   2961		[19] = RCAR_GP_PIN(4, 23),	/* VI1_DATA14	*/
   2962		[20] = RCAR_GP_PIN(4, 24),	/* VI1_DATA15	*/
   2963		[21] = RCAR_GP_PIN(4,  9),	/* ETH_REF_CLK	*/
   2964		[22] = RCAR_GP_PIN(4, 10),	/* ETH_TXD0	*/
   2965		[23] = RCAR_GP_PIN(4, 11),	/* ETH_TXD1	*/
   2966		[24] = RCAR_GP_PIN(4, 12),	/* ETH_CRS_DV	*/
   2967		[25] = RCAR_GP_PIN(4, 13),	/* ETH_TX_EN	*/
   2968		[26] = RCAR_GP_PIN(4, 14),	/* ETH_RX_ER	*/
   2969		[27] = RCAR_GP_PIN(4, 15),	/* ETH_RXD0	*/
   2970		[28] = RCAR_GP_PIN(4, 16),	/* ETH_RXD1	*/
   2971		[29] = RCAR_GP_PIN(4, 17),	/* ETH_MDC	*/
   2972		[30] = RCAR_GP_PIN(4, 18),	/* ETH_MDIO	*/
   2973		[31] = RCAR_GP_PIN(4, 19),	/* ETH_LINK	*/
   2974	} },
   2975	{ PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {
   2976		[ 0] = RCAR_GP_PIN(3,  6),	/* SSI_SCK012	*/
   2977		[ 1] = RCAR_GP_PIN(3,  7),	/* SSI_WS012	*/
   2978		[ 2] = RCAR_GP_PIN(3, 10),	/* SSI_SDATA0	*/
   2979		[ 3] = RCAR_GP_PIN(3,  9),	/* SSI_SDATA1	*/
   2980		[ 4] = RCAR_GP_PIN(3,  8),	/* SSI_SDATA2	*/
   2981		[ 5] = RCAR_GP_PIN(3,  2),	/* SSI_SCK34	*/
   2982		[ 6] = RCAR_GP_PIN(3,  3),	/* SSI_WS34	*/
   2983		[ 7] = RCAR_GP_PIN(3,  5),	/* SSI_SDATA3	*/
   2984		[ 8] = RCAR_GP_PIN(3,  4),	/* SSI_SDATA4	*/
   2985		[ 9] = RCAR_GP_PIN(2, 31),	/* SSI_SCK5	*/
   2986		[10] = RCAR_GP_PIN(3,  0),	/* SSI_WS5	*/
   2987		[11] = RCAR_GP_PIN(3,  1),	/* SSI_SDATA5	*/
   2988		[12] = RCAR_GP_PIN(2, 28),	/* SSI_SCK6	*/
   2989		[13] = RCAR_GP_PIN(2, 29),	/* SSI_WS6	*/
   2990		[14] = RCAR_GP_PIN(2, 30),	/* SSI_SDATA6	*/
   2991		[15] = RCAR_GP_PIN(2, 24),	/* SSI_SCK78	*/
   2992		[16] = RCAR_GP_PIN(2, 25),	/* SSI_WS78	*/
   2993		[17] = RCAR_GP_PIN(2, 27),	/* SSI_SDATA7	*/
   2994		[18] = RCAR_GP_PIN(2, 26),	/* SSI_SDATA8	*/
   2995		[19] = RCAR_GP_PIN(3, 23),	/* TCLK0	*/
   2996		[20] = RCAR_GP_PIN(3, 11),	/* SD0_CLK	*/
   2997		[21] = RCAR_GP_PIN(3, 12),	/* SD0_CMD	*/
   2998		[22] = RCAR_GP_PIN(3, 13),	/* SD0_DAT0	*/
   2999		[23] = RCAR_GP_PIN(3, 14),	/* SD0_DAT1	*/
   3000		[24] = RCAR_GP_PIN(3, 15),	/* SD0_DAT2	*/
   3001		[25] = RCAR_GP_PIN(3, 16),	/* SD0_DAT3	*/
   3002		[26] = RCAR_GP_PIN(3, 17),	/* SD0_CD	*/
   3003		[27] = RCAR_GP_PIN(3, 18),	/* SD0_WP	*/
   3004		[28] = RCAR_GP_PIN(2, 22),	/* AUDIO_CLKA	*/
   3005		[29] = RCAR_GP_PIN(2, 23),	/* AUDIO_CLKB	*/
   3006		[30] = RCAR_GP_PIN(1, 14),	/* IRQ2		*/
   3007		[31] = RCAR_GP_PIN(1, 15),	/* IRQ3		*/
   3008	} },
   3009	{ PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {
   3010		[ 0] = RCAR_GP_PIN(0,  1),	/* PENC0	*/
   3011		[ 1] = RCAR_GP_PIN(0,  2),	/* PENC1	*/
   3012		[ 2] = RCAR_GP_PIN(0,  3),	/* USB_OVC0	*/
   3013		[ 3] = RCAR_GP_PIN(0,  4),	/* USB_OVC1	*/
   3014		[ 4] = RCAR_GP_PIN(1, 16),	/* SCIF_CLK	*/
   3015		[ 5] = RCAR_GP_PIN(1, 17),	/* TX0		*/
   3016		[ 6] = RCAR_GP_PIN(1, 18),	/* RX0		*/
   3017		[ 7] = RCAR_GP_PIN(1, 19),	/* SCK0		*/
   3018		[ 8] = RCAR_GP_PIN(1, 20),	/* /CTS0	*/
   3019		[ 9] = RCAR_GP_PIN(1, 21),	/* /RTS0	*/
   3020		[10] = RCAR_GP_PIN(3, 19),	/* HSPI_CLK0	*/
   3021		[11] = RCAR_GP_PIN(3, 20),	/* /HSPI_CS0	*/
   3022		[12] = RCAR_GP_PIN(3, 21),	/* HSPI_RX0	*/
   3023		[13] = RCAR_GP_PIN(3, 22),	/* HSPI_TX0	*/
   3024		[14] = RCAR_GP_PIN(4, 20),	/* ETH_MAGIC	*/
   3025		[15] = RCAR_GP_PIN(4, 25),	/* AVS1		*/
   3026		[16] = RCAR_GP_PIN(4, 26),	/* AVS2		*/
   3027		[17] = SH_PFC_PIN_NONE,
   3028		[18] = SH_PFC_PIN_NONE,
   3029		[19] = SH_PFC_PIN_NONE,
   3030		[20] = SH_PFC_PIN_NONE,
   3031		[21] = SH_PFC_PIN_NONE,
   3032		[22] = SH_PFC_PIN_NONE,
   3033		[23] = SH_PFC_PIN_NONE,
   3034		[24] = SH_PFC_PIN_NONE,
   3035		[25] = SH_PFC_PIN_NONE,
   3036		[26] = SH_PFC_PIN_NONE,
   3037		[27] = SH_PFC_PIN_NONE,
   3038		[28] = SH_PFC_PIN_NONE,
   3039		[29] = SH_PFC_PIN_NONE,
   3040		[30] = SH_PFC_PIN_NONE,
   3041		[31] = SH_PFC_PIN_NONE,
   3042	} },
   3043	{ /* sentinel */ },
   3044};
   3045
   3046static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
   3047	.get_bias = rcar_pinmux_get_bias,
   3048	.set_bias = rcar_pinmux_set_bias,
   3049};
   3050
   3051const struct sh_pfc_soc_info r8a7778_pinmux_info = {
   3052	.name = "r8a7778_pfc",
   3053	.ops  = &r8a7778_pfc_ops,
   3054
   3055	.unlock_reg = 0xfffc0000, /* PMMR */
   3056
   3057	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
   3058
   3059	.pins = pinmux_pins,
   3060	.nr_pins = ARRAY_SIZE(pinmux_pins),
   3061
   3062	.groups = pinmux_groups,
   3063	.nr_groups = ARRAY_SIZE(pinmux_groups),
   3064
   3065	.functions = pinmux_functions,
   3066	.nr_functions = ARRAY_SIZE(pinmux_functions),
   3067
   3068	.cfg_regs = pinmux_config_regs,
   3069	.bias_regs = pinmux_bias_regs,
   3070
   3071	.pinmux_data = pinmux_data,
   3072	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
   3073};