pfc-r8a7791.c - cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	cachepc-linux Fork of AMDESE/linux with modifications for CachePC side-channel attack
	git clone https://git.sinitax.com/sinitax/cachepc-linux
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pfc-r8a7791.c (216274B)
      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * r8a7791/r8a7743 processor support - PFC hardware block.
      4 *
      5 * Copyright (C) 2013 Renesas Electronics Corporation
      6 * Copyright (C) 2014-2017 Cogent Embedded, Inc.
      7 */
      8
      9#include <linux/errno.h>
     10#include <linux/kernel.h>
     11
     12#include "sh_pfc.h"
     13
     14/*
     15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
     16 * which case they support both 3.3V and 1.8V signalling.
     17 */
     18#define CPU_ALL_GP(fn, sfx)						\
     19	PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     20	PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     21	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     22	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     23	PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     24	PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     25	PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),	\
     26	PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     27	PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     28	PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     29	PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     30	PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     31	PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     32	PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     33	PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     34	PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     35	PORT_GP_1(7, 7, fn, sfx),					\
     36	PORT_GP_1(7, 8, fn, sfx),					\
     37	PORT_GP_1(7, 9, fn, sfx),					\
     38	PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     39	PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     40	PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     41	PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     42	PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     43	PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     44	PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     45	PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     46	PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     47	PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     48	PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     49	PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     50	PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     51	PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     52	PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
     53	PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
     54
     55#define CPU_ALL_NOGP(fn)						\
     56	PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
     57	PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP),		\
     58	PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP),		\
     59	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
     60	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
     61	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
     62	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
     63
     64enum {
     65	PINMUX_RESERVED = 0,
     66
     67	PINMUX_DATA_BEGIN,
     68	GP_ALL(DATA),
     69	PINMUX_DATA_END,
     70
     71	PINMUX_FUNCTION_BEGIN,
     72	GP_ALL(FN),
     73
     74	/* GPSR0 */
     75	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
     76	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
     77	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
     78	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
     79	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
     80	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
     81
     82	/* GPSR1 */
     83	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
     84	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
     85	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
     86	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
     87	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
     88	FN_IP3_21_20,
     89
     90	/* GPSR2 */
     91	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
     92	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
     93	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
     94	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
     95	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
     96	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
     97	FN_IP6_5_3, FN_IP6_7_6,
     98
     99	/* GPSR3 */
    100	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
    101	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
    102	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
    103	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
    104	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
    105	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
    106	FN_IP9_18_17,
    107
    108	/* GPSR4 */
    109	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
    110	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
    111	FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
    112	FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
    113	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
    114	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
    115	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
    116	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
    117
    118	/* GPSR5 */
    119	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
    120	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
    121	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
    122	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
    123	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
    124	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
    125	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
    126
    127	/* GPSR6 */
    128	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
    129	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
    130	FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
    131	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
    132	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
    133	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
    134	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
    135	FN_USB1_OVC, FN_DU0_DOTCLKIN,
    136
    137	/* GPSR7 */
    138	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
    139	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
    140	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
    141	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
    142	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
    143	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
    144
    145	/* IPSR0 */
    146	FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
    147	FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
    148	FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
    149	FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
    150	FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
    151	FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
    152
    153	/* IPSR1 */
    154	FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
    155	FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
    156	FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
    157	FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
    158	FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
    159	FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
    160	FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
    161	FN_A15, FN_BPFCLK_C,
    162	FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
    163	FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
    164	FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
    165
    166	/* IPSR2 */
    167	FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
    168	FN_A20, FN_SPCLK,
    169	FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
    170	FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
    171	FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
    172	FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
    173	FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
    174	FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
    175	FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
    176	FN_EX_CS1_N, FN_MSIOF2_SCK,
    177	FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
    178	FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
    179
    180	/* IPSR3 */
    181	FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
    182	FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
    183	FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
    184	FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
    185	FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
    186	FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
    187	FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
    188	FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
    189	FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
    190	FN_DREQ0, FN_PWM3, FN_TPU_TO3,
    191	FN_DACK0, FN_DRACK0, FN_REMOCON,
    192	FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
    193	FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
    194	FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
    195	FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
    196
    197	/* IPSR4 */
    198	FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
    199	FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
    200	FN_GLO_I0_D,
    201	FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
    202	FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
    203	FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
    204	FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
    205	FN_GLO_Q1_D, FN_HCTS1_N_E,
    206	FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
    207	FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
    208	FN_SSI_SCK4, FN_GLO_SS_D,
    209	FN_SSI_WS4, FN_GLO_RFON_D,
    210	FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
    211	FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
    212	FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
    213
    214	/* IPSR5 */
    215	FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
    216	FN_MSIOF2_TXD_D, FN_VI1_R3_B,
    217	FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
    218	FN_MSIOF2_SS1_D, FN_VI1_R4_B,
    219	FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
    220	FN_MSIOF2_RXD_D, FN_VI1_R5_B,
    221	FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
    222	FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
    223	FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
    224	FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
    225	FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
    226	FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
    227	FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
    228	FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
    229	FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
    230
    231	/* IPSR6 */
    232	FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
    233	FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
    234	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
    235	FN_SCIFA2_RXD, FN_FMIN_E,
    236	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
    237	FN_IRQ0, FN_SCIFB1_RXD_D,
    238	FN_IRQ1, FN_SCIFB1_SCK_C,
    239	FN_IRQ2, FN_SCIFB1_TXD_D,
    240	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
    241	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
    242	FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
    243	FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
    244	FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
    245	FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
    246
    247	/* IPSR7 */
    248	FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
    249	FN_SCIF_CLK_B, FN_GPS_MAG_D,
    250	FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
    251	FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
    252	FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
    253	FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
    254	FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
    255	FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
    256	FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
    257	FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
    258	FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
    259	FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
    260	FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
    261	FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
    262	FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
    263	FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
    264	FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
    265	FN_SCIFA1_SCK, FN_SSI_SCK78_B,
    266
    267	/* IPSR8 */
    268	FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
    269	FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
    270	FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
    271	FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
    272	FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
    273	FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
    274	FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
    275	FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
    276	FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
    277	FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
    278	FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
    279	FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
    280	FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
    281	FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
    282	FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
    283	FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
    284	FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
    285
    286	/* IPSR9 */
    287	FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
    288	FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
    289	FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
    290	FN_DU1_DOTCLKOUT0, FN_QCLK,
    291	FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
    292	FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
    293	FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
    294	FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
    295	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
    296	FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
    297	FN_DU1_DISP, FN_QPOLA,
    298	FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
    299	FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
    300	FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
    301	FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
    302	FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
    303	FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
    304	FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
    305	FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
    306
    307	/* IPSR10 */
    308	FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
    309	FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
    310	FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
    311	FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
    312	FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
    313	FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
    314	FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
    315	FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
    316	FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
    317	FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
    318	FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
    319	FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
    320	FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
    321	FN_TS_SDATA0_C, FN_ATACS11_N,
    322	FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
    323	FN_TS_SCK0_C, FN_ATAG1_N,
    324	FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
    325	FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
    326	FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
    327
    328	/* IPSR11 */
    329	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
    330	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
    331	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
    332	FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
    333	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
    334	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
    335	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
    336	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
    337	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
    338	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
    339	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
    340	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
    341	FN_VI1_DATA7, FN_AVB_MDC,
    342	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
    343	FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
    344
    345	/* IPSR12 */
    346	FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
    347	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
    348	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
    349	FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
    350	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
    351	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
    352	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
    353	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
    354	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
    355	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
    356	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
    357	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
    358	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
    359	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
    360	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
    361	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
    362	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
    363
    364	/* IPSR13 */
    365	FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
    366	FN_ADICLK_B, FN_MSIOF0_SS1_C,
    367	FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
    368	FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
    369	FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
    370	FN_ADICHS2_B, FN_MSIOF0_TXD_C,
    371	FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
    372	FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
    373	FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
    374	FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
    375	FN_SCIFA5_TXD_B, FN_TX3_C,
    376	FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
    377	FN_SCIFA5_RXD_B, FN_RX3_C,
    378	FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
    379	FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
    380	FN_SD1_DATA3, FN_IERX_B,
    381	FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
    382
    383	/* IPSR14 */
    384	FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
    385	FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
    386	FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
    387	FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
    388	FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
    389	FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
    390	FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
    391	FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
    392	FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
    393	FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
    394	FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
    395	FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
    396	FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
    397	FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
    398
    399	/* IPSR15 */
    400	FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
    401	FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
    402	FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
    403	FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
    404	FN_PWM5_B, FN_SCIFA3_TXD_C,
    405	FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
    406	FN_VI1_G6_B, FN_SCIFA3_RXD_C,
    407	FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
    408	FN_VI1_G7_B, FN_SCIFA3_SCK_C,
    409	FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
    410	FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
    411	FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
    412	FN_TCLK2, FN_VI1_DATA3_C,
    413	FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
    414	FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
    415
    416	/* IPSR16 */
    417	FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
    418	FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
    419	FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
    420	FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
    421	FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
    422
    423	/* MOD_SEL */
    424	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
    425	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
    426	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
    427	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
    428	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
    429	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
    430	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
    431	FN_SEL_QSP_0, FN_SEL_QSP_1,
    432	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
    433	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
    434	FN_SEL_HSCIF1_4,
    435	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
    436	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
    437	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
    438	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
    439	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
    440
    441	/* MOD_SEL2 */
    442	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
    443	FN_SEL_SCIF0_4,
    444	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
    445	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
    446	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
    447	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
    448	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
    449	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
    450	FN_SEL_ADG_0, FN_SEL_ADG_1,
    451	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
    452	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
    453	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
    454	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
    455	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
    456	FN_SEL_SIM_0, FN_SEL_SIM_1,
    457	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
    458
    459	/* MOD_SEL3 */
    460	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
    461	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
    462	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
    463	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
    464	FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
    465	FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
    466	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
    467	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
    468	FN_SEL_MMC_0, FN_SEL_MMC_1,
    469	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
    470	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
    471	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
    472	FN_SEL_I2C1_4,
    473	FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
    474
    475	/* MOD_SEL4 */
    476	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
    477	FN_SEL_SOF1_4,
    478	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
    479	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
    480	FN_SEL_RAD_0, FN_SEL_RAD_1,
    481	FN_SEL_RCN_0, FN_SEL_RCN_1,
    482	FN_SEL_RSP_0, FN_SEL_RSP_1,
    483	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
    484	FN_SEL_SCIF2_4,
    485	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
    486	FN_SEL_SOF2_4,
    487	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
    488	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
    489	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
    490	PINMUX_FUNCTION_END,
    491
    492	PINMUX_MARK_BEGIN,
    493
    494	EX_CS0_N_MARK, RD_N_MARK,
    495
    496	AUDIO_CLKA_MARK,
    497
    498	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
    499	VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
    500	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
    501
    502	SD1_CLK_MARK,
    503
    504	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
    505	DU0_DOTCLKIN_MARK,
    506
    507	/* IPSR0 */
    508	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
    509	D6_MARK, D7_MARK, D8_MARK,
    510	D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
    511	A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
    512	PWM2_B_MARK,
    513	A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
    514	A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
    515	A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
    516
    517	/* IPSR1 */
    518	A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
    519	A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
    520	A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
    521	A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
    522	A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
    523	A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
    524	A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
    525	A15_MARK, BPFCLK_C_MARK,
    526	A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
    527	A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
    528	A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
    529
    530	/* IPSR2 */
    531	A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
    532	SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
    533	A20_MARK, SPCLK_MARK,
    534	A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
    535	A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
    536	A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
    537	A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
    538	A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
    539	RX1_MARK, SCIFA1_RXD_MARK,
    540	CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
    541	CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
    542	EX_CS1_N_MARK, MSIOF2_SCK_MARK,
    543	EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
    544	EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
    545	ATAG0_N_MARK, EX_WAIT1_MARK,
    546
    547	/* IPSR3 */
    548	EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
    549	EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
    550	SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
    551	BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
    552	SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
    553	RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
    554	SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
    555	WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
    556	WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
    557	EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
    558	DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
    559	DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
    560	SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
    561	SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
    562	SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
    563	SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
    564	SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
    565	SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
    566
    567	/* IPSR4 */
    568	SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
    569	SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
    570	MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
    571	SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
    572	MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
    573	SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
    574	SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
    575	HSCK1_E_MARK,
    576	SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
    577	GLO_Q1_D_MARK, HCTS1_N_E_MARK,
    578	SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
    579	SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
    580	SSI_SCK4_MARK, GLO_SS_D_MARK,
    581	SSI_WS4_MARK, GLO_RFON_D_MARK,
    582	SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
    583	SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
    584	MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
    585
    586	/* IPSR5 */
    587	SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
    588	MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
    589	SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
    590	MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
    591	SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
    592	MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
    593	SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
    594	SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
    595	SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
    596	SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
    597	SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
    598	SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
    599	SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
    600	SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
    601	SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
    602
    603	/* IPSR6 */
    604	AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
    605	SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
    606	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
    607	SCIFA2_RXD_MARK, FMIN_E_MARK,
    608	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
    609	IRQ0_MARK, SCIFB1_RXD_D_MARK,
    610	IRQ1_MARK, SCIFB1_SCK_C_MARK,
    611	IRQ2_MARK, SCIFB1_TXD_D_MARK,
    612	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
    613	IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
    614	MSIOF2_RXD_E_MARK,
    615	IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
    616	IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
    617	I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
    618	IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
    619	GPS_CLK_C_MARK, GPS_CLK_D_MARK,
    620	IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
    621	GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
    622
    623	/* IPSR7 */
    624	IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
    625	SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
    626	DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
    627	SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
    628	DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
    629	SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
    630	DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
    631	DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
    632	DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
    633	DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
    634	DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
    635	DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
    636	DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
    637	SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
    638	DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
    639	SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
    640	DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
    641	SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
    642
    643	/* IPSR8 */
    644	DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
    645	DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
    646	SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
    647	DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
    648	SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
    649	DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
    650	SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
    651	DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
    652	SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
    653	DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
    654	SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
    655	DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
    656	SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
    657	DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
    658	SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
    659	DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
    660	DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
    661	DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
    662
    663	/* IPSR9 */
    664	DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
    665	DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
    666	SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
    667	DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
    668	DU1_DOTCLKOUT0_MARK, QCLK_MARK,
    669	DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
    670	TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
    671	DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
    672	DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
    673	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
    674	CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
    675	DU1_DISP_MARK, QPOLA_MARK,
    676	DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
    677	VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
    678	VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
    679	VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
    680	VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
    681	VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
    682	VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
    683	HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
    684
    685	/* IPSR10 */
    686	VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
    687	HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
    688	VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
    689	HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
    690	VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
    691	HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
    692	VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
    693	HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
    694	VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
    695	CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
    696	VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
    697	VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
    698	VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
    699	TS_SDATA0_C_MARK, ATACS11_N_MARK,
    700	VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
    701	TS_SCK0_C_MARK, ATAG1_N_MARK,
    702	VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
    703	VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
    704	VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
    705	I2C1_SCL_D_MARK,
    706
    707	/* IPSR11 */
    708	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
    709	I2C1_SDA_D_MARK,
    710	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
    711	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
    712	I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
    713	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
    714	TX4_B_MARK, SCIFA4_TXD_B_MARK,
    715	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
    716	RX4_B_MARK, SCIFA4_RXD_B_MARK,
    717	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
    718	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
    719	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
    720	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
    721	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
    722	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
    723	VI1_DATA7_MARK, AVB_MDC_MARK,
    724	ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
    725	ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
    726
    727	/* IPSR12 */
    728	ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
    729	ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
    730	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
    731	I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
    732	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
    733	I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
    734	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
    735	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
    736	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
    737	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
    738	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
    739	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
    740	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
    741	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
    742	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
    743	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
    744	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
    745	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
    746
    747	/* IPSR13 */
    748	STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
    749	ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
    750	STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
    751	STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
    752	STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
    753	ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
    754	SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
    755	SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
    756	SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
    757	SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
    758	SCIFA5_TXD_B_MARK, TX3_C_MARK,
    759	SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
    760	SCIFA5_RXD_B_MARK, RX3_C_MARK,
    761	SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
    762	SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
    763	SD1_DATA3_MARK, IERX_B_MARK,
    764	SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
    765
    766	/* IPSR14 */
    767	SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
    768	SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
    769	SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
    770	SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
    771	SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
    772	SCIFA5_TXD_C_MARK,
    773	SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
    774	SCIFA5_RXD_C_MARK,
    775	MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
    776	VI1_CLK_C_MARK, VI1_G0_B_MARK,
    777	MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
    778	VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
    779	MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
    780	MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
    781	MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
    782	VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
    783	MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
    784	VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
    785
    786	/* IPSR15 */
    787	SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
    788	SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
    789	SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
    790	GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
    791	PWM5_B_MARK, SCIFA3_TXD_C_MARK,
    792	GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
    793	VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
    794	GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
    795	VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
    796	HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
    797	TCLK1_MARK, VI1_DATA1_C_MARK,
    798	HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
    799	HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
    800	TCLK2_MARK, VI1_DATA3_C_MARK,
    801	HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
    802	CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
    803	HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
    804	CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
    805
    806	/* IPSR16 */
    807	HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
    808	GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
    809	HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
    810	GLO_SS_C_MARK, VI1_DATA7_C_MARK,
    811	HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
    812	HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
    813	HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
    814	PINMUX_MARK_END,
    815};
    816
    817static const u16 pinmux_data[] = {
    818	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
    819
    820	PINMUX_SINGLE(EX_CS0_N),
    821	PINMUX_SINGLE(RD_N),
    822	PINMUX_SINGLE(AUDIO_CLKA),
    823	PINMUX_SINGLE(VI0_CLK),
    824	PINMUX_SINGLE(VI0_DATA0_VI0_B0),
    825	PINMUX_SINGLE(VI0_DATA1_VI0_B1),
    826	PINMUX_SINGLE(VI0_DATA2_VI0_B2),
    827	PINMUX_SINGLE(VI0_DATA4_VI0_B4),
    828	PINMUX_SINGLE(VI0_DATA5_VI0_B5),
    829	PINMUX_SINGLE(VI0_DATA6_VI0_B6),
    830	PINMUX_SINGLE(VI0_DATA7_VI0_B7),
    831	PINMUX_SINGLE(USB0_PWEN),
    832	PINMUX_SINGLE(USB0_OVC),
    833	PINMUX_SINGLE(USB1_PWEN),
    834	PINMUX_SINGLE(USB1_OVC),
    835	PINMUX_SINGLE(DU0_DOTCLKIN),
    836	PINMUX_SINGLE(SD1_CLK),
    837
    838	/* IPSR0 */
    839	PINMUX_IPSR_GPSR(IP0_0, D0),
    840	PINMUX_IPSR_GPSR(IP0_1, D1),
    841	PINMUX_IPSR_GPSR(IP0_2, D2),
    842	PINMUX_IPSR_GPSR(IP0_3, D3),
    843	PINMUX_IPSR_GPSR(IP0_4, D4),
    844	PINMUX_IPSR_GPSR(IP0_5, D5),
    845	PINMUX_IPSR_GPSR(IP0_6, D6),
    846	PINMUX_IPSR_GPSR(IP0_7, D7),
    847	PINMUX_IPSR_GPSR(IP0_8, D8),
    848	PINMUX_IPSR_GPSR(IP0_9, D9),
    849	PINMUX_IPSR_GPSR(IP0_10, D10),
    850	PINMUX_IPSR_GPSR(IP0_11, D11),
    851	PINMUX_IPSR_GPSR(IP0_12, D12),
    852	PINMUX_IPSR_GPSR(IP0_13, D13),
    853	PINMUX_IPSR_GPSR(IP0_14, D14),
    854	PINMUX_IPSR_GPSR(IP0_15, D15),
    855	PINMUX_IPSR_GPSR(IP0_18_16, A0),
    856	PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
    857	PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
    858	PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
    859	PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
    860	PINMUX_IPSR_GPSR(IP0_20_19, A1),
    861	PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
    862	PINMUX_IPSR_GPSR(IP0_22_21, A2),
    863	PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
    864	PINMUX_IPSR_GPSR(IP0_24_23, A3),
    865	PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
    866	PINMUX_IPSR_GPSR(IP0_26_25, A4),
    867	PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
    868	PINMUX_IPSR_GPSR(IP0_28_27, A5),
    869	PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
    870	PINMUX_IPSR_GPSR(IP0_30_29, A6),
    871	PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
    872
    873	/* IPSR1 */
    874	PINMUX_IPSR_GPSR(IP1_1_0, A7),
    875	PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
    876	PINMUX_IPSR_GPSR(IP1_3_2, A8),
    877	PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
    878	PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
    879	PINMUX_IPSR_GPSR(IP1_5_4, A9),
    880	PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
    881	PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
    882	PINMUX_IPSR_GPSR(IP1_7_6, A10),
    883	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
    884	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
    885	PINMUX_IPSR_GPSR(IP1_10_8, A11),
    886	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
    887	PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
    888	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
    889	PINMUX_IPSR_GPSR(IP1_13_11, A12),
    890	PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
    891	PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
    892	PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
    893	PINMUX_IPSR_GPSR(IP1_16_14, A13),
    894	PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
    895	PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
    896	PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
    897	PINMUX_IPSR_GPSR(IP1_19_17, A14),
    898	PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
    899	PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
    900	PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
    901	PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
    902	PINMUX_IPSR_GPSR(IP1_22_20, A15),
    903	PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
    904	PINMUX_IPSR_GPSR(IP1_25_23, A16),
    905	PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
    906	PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
    907	PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
    908	PINMUX_IPSR_GPSR(IP1_28_26, A17),
    909	PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
    910	PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
    911	PINMUX_IPSR_GPSR(IP1_31_29, A18),
    912	PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
    913	PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
    914	PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
    915
    916	/* IPSR2 */
    917	PINMUX_IPSR_GPSR(IP2_2_0, A19),
    918	PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
    919	PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
    920	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
    921	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
    922	PINMUX_IPSR_GPSR(IP2_2_0, A20),
    923	PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
    924	PINMUX_IPSR_GPSR(IP2_6_5, A21),
    925	PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
    926	PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
    927	PINMUX_IPSR_GPSR(IP2_9_7, A22),
    928	PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
    929	PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
    930	PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
    931	PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
    932	PINMUX_IPSR_GPSR(IP2_12_10, A23),
    933	PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
    934	PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
    935	PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
    936	PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
    937	PINMUX_IPSR_GPSR(IP2_15_13, A24),
    938	PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
    939	PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
    940	PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
    941	PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
    942	PINMUX_IPSR_GPSR(IP2_18_16, A25),
    943	PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
    944	PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
    945	PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
    946	PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
    947	PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
    948	PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
    949	PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
    950	PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
    951	PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
    952	PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
    953	PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
    954	PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
    955	PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
    956	PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
    957	PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
    958	PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
    959	PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
    960	PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
    961	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
    962	PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
    963	PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
    964
    965	/* IPSR3 */
    966	PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
    967	PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
    968	PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
    969	PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
    970	PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
    971	PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
    972	PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
    973	PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
    974	PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
    975	PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
    976	PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
    977	PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
    978	PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
    979	PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
    980	PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
    981	PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
    982	PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
    983	PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
    984	PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
    985	PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
    986	PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
    987	PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
    988	PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
    989	PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
    990	PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
    991	PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
    992	PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
    993	PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
    994	PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
    995	PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
    996	PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
    997	PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
    998	PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
    999	PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
   1000	PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
   1001	PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
   1002	PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
   1003	PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
   1004	PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
   1005	PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
   1006	PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
   1007	PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
   1008	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
   1009	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
   1010	PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
   1011	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
   1012	PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
   1013	PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
   1014	PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
   1015	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
   1016	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
   1017	PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
   1018	PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
   1019	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
   1020	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
   1021	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
   1022
   1023	/* IPSR4 */
   1024	PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
   1025	PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
   1026	PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
   1027	PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
   1028	PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
   1029	PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
   1030	PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
   1031	PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
   1032	PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
   1033	PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
   1034	PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
   1035	PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
   1036	PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
   1037	PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
   1038	PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
   1039	PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
   1040	PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
   1041	PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
   1042	PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
   1043	PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
   1044	PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
   1045	PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
   1046	PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
   1047	PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
   1048	PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
   1049	PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
   1050	PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
   1051	PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
   1052	PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
   1053	PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
   1054	PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
   1055	PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
   1056	PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
   1057	PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
   1058	PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
   1059	PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
   1060	PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
   1061	PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
   1062	PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
   1063	PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
   1064	PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
   1065	PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
   1066	PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
   1067	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
   1068	PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
   1069	PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
   1070	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
   1071	PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
   1072
   1073	/* IPSR5 */
   1074	PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
   1075	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
   1076	PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
   1077	PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
   1078	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
   1079	PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
   1080	PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
   1081	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
   1082	PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
   1083	PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
   1084	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
   1085	PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
   1086	PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
   1087	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
   1088	PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
   1089	PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
   1090	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
   1091	PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
   1092	PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
   1093	PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
   1094	PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
   1095	PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
   1096	PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
   1097	PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
   1098	PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
   1099	PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
   1100	PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
   1101	PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
   1102	PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
   1103	PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
   1104	PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
   1105	PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
   1106	PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
   1107	PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
   1108	PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
   1109	PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
   1110	PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
   1111	PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
   1112	PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
   1113	PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
   1114	PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
   1115	PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
   1116	PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
   1117	PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
   1118	PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
   1119	PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
   1120	PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
   1121	PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
   1122	PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
   1123
   1124	/* IPSR6 */
   1125	PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
   1126	PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
   1127	PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
   1128	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
   1129	PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
   1130	PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
   1131	PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
   1132	PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
   1133	PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
   1134	PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
   1135	PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
   1136	PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
   1137	PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
   1138	PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
   1139	PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
   1140	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
   1141	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
   1142	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
   1143	PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
   1144	PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
   1145	PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
   1146	PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
   1147	PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
   1148	PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
   1149	PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
   1150	PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
   1151	PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
   1152	PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
   1153	PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
   1154	PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
   1155	PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
   1156	PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
   1157	PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
   1158	PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
   1159	PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
   1160	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
   1161	PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
   1162	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
   1163	PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
   1164	PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
   1165	PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
   1166	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
   1167	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
   1168	PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
   1169	PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
   1170	PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
   1171	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
   1172	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
   1173
   1174	/* IPSR7 */
   1175	PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
   1176	PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
   1177	PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
   1178	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
   1179	PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
   1180	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
   1181	PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
   1182	PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
   1183	PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
   1184	PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
   1185	PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
   1186	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
   1187	PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
   1188	PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
   1189	PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
   1190	PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
   1191	PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
   1192	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
   1193	PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
   1194	PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
   1195	PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
   1196	PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
   1197	PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
   1198	PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
   1199	PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
   1200	PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
   1201	PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
   1202	PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
   1203	PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
   1204	PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
   1205	PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
   1206	PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
   1207	PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
   1208	PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
   1209	PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
   1210	PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
   1211	PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
   1212	PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
   1213	PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
   1214	PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
   1215	PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
   1216	PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
   1217	PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
   1218	PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
   1219	PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
   1220	PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
   1221	PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
   1222	PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
   1223	PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
   1224	PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
   1225	PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
   1226	PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
   1227	PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
   1228	PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
   1229
   1230	/* IPSR8 */
   1231	PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
   1232	PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
   1233	PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
   1234	PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
   1235	PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
   1236	PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
   1237	PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
   1238	PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
   1239	PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
   1240	PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
   1241	PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
   1242	PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
   1243	PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
   1244	PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
   1245	PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
   1246	PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
   1247	PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
   1248	PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
   1249	PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
   1250	PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
   1251	PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
   1252	PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
   1253	PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
   1254	PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
   1255	PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
   1256	PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
   1257	PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
   1258	PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
   1259	PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
   1260	PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
   1261	PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
   1262	PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
   1263	PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
   1264	PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
   1265	PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
   1266	PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
   1267	PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
   1268	PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
   1269	PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
   1270	PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
   1271	PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
   1272	PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
   1273	PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
   1274	PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
   1275	PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
   1276	PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
   1277	PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
   1278	PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
   1279	PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
   1280	PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
   1281	PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
   1282	PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
   1283	PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
   1284	PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
   1285	PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
   1286	PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
   1287
   1288	/* IPSR9 */
   1289	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
   1290	PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
   1291	PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
   1292	PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
   1293	PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
   1294	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
   1295	PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
   1296	PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
   1297	PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
   1298	PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
   1299	PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
   1300	PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
   1301	PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
   1302	PINMUX_IPSR_GPSR(IP9_7, QCLK),
   1303	PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
   1304	PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
   1305	PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
   1306	PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
   1307	PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
   1308	PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
   1309	PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
   1310	PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
   1311	PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
   1312	PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
   1313	PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
   1314	PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
   1315	PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
   1316	PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
   1317	PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
   1318	PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
   1319	PINMUX_IPSR_GPSR(IP9_16, QPOLA),
   1320	PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
   1321	PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
   1322	PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
   1323	PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
   1324	PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
   1325	PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
   1326	PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
   1327	PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
   1328	PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
   1329	PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
   1330	PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
   1331	PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
   1332	PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
   1333	PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
   1334	PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
   1335	PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
   1336	PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
   1337	PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
   1338	PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
   1339	PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
   1340	PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
   1341	PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
   1342	PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
   1343	PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
   1344	PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
   1345	PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
   1346	PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
   1347	PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
   1348	PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
   1349
   1350	/* IPSR10 */
   1351	PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
   1352	PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
   1353	PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
   1354	PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
   1355	PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
   1356	PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
   1357	PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
   1358	PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
   1359	PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
   1360	PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
   1361	PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
   1362	PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
   1363	PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
   1364	PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
   1365	PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
   1366	PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
   1367	PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
   1368	PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
   1369	PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
   1370	PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
   1371	PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
   1372	PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
   1373	PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
   1374	PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
   1375	PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
   1376	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
   1377	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
   1378	PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
   1379	PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
   1380	PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
   1381	PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
   1382	PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
   1383	PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
   1384	PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
   1385	PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
   1386	PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
   1387	PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
   1388	PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
   1389	PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
   1390	PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
   1391	PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
   1392	PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
   1393	PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
   1394	PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
   1395	PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
   1396	PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
   1397	PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
   1398	PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
   1399	PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
   1400	PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
   1401	PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
   1402	PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
   1403	PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
   1404	PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
   1405	PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
   1406	PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
   1407	PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
   1408	PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
   1409	PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
   1410	PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
   1411	PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
   1412	PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
   1413	PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
   1414
   1415	/* IPSR11 */
   1416	PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
   1417	PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
   1418	PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
   1419	PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
   1420	PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
   1421	PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
   1422	PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
   1423	PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
   1424	PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
   1425	PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
   1426	PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
   1427	PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
   1428	PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
   1429	PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
   1430	PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
   1431	PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
   1432	PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
   1433	PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
   1434	PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
   1435	PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
   1436	PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
   1437	PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
   1438	PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
   1439	PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
   1440	PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
   1441	PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
   1442	PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
   1443	PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
   1444	PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
   1445	PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
   1446	PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
   1447	PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
   1448	PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
   1449	PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
   1450	PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
   1451	PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
   1452	PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
   1453	PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
   1454	PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
   1455	PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
   1456	PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
   1457	PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
   1458	PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
   1459	PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
   1460	PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
   1461	PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
   1462	PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
   1463	PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
   1464	PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
   1465	PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
   1466	PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
   1467	PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
   1468	PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
   1469	PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
   1470	PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
   1471	PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
   1472	PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
   1473
   1474	/* IPSR12 */
   1475	PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
   1476	PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
   1477	PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
   1478	PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
   1479	PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
   1480	PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
   1481	PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
   1482	PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
   1483	PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
   1484	PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
   1485	PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
   1486	PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
   1487	PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
   1488	PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
   1489	PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
   1490	PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
   1491	PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
   1492	PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
   1493	PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
   1494	PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
   1495	PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
   1496	PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
   1497	PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
   1498	PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
   1499	PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
   1500	PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
   1501	PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
   1502	PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
   1503	PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
   1504	PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
   1505	PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
   1506	PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
   1507	PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
   1508	PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
   1509	PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
   1510	PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
   1511	PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
   1512	PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
   1513	PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
   1514	PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
   1515	PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
   1516	PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
   1517	PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
   1518	PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
   1519	PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
   1520	PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
   1521	PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
   1522	PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
   1523	PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
   1524	PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
   1525	PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
   1526
   1527	/* IPSR13 */
   1528	PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
   1529	PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
   1530	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
   1531	PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
   1532	PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
   1533	PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
   1534	PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
   1535	PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
   1536	PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
   1537	PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
   1538	PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
   1539	PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
   1540	PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
   1541	PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
   1542	PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
   1543	PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
   1544	PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
   1545	PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
   1546	PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
   1547	PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
   1548	PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
   1549	PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
   1550	PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
   1551	PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
   1552	PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
   1553	PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
   1554	PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
   1555	PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
   1556	PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
   1557	PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
   1558	PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
   1559	PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
   1560	PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
   1561	PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
   1562	PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
   1563	PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
   1564	PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
   1565	PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
   1566	PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
   1567	PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
   1568	PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
   1569	PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
   1570	PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
   1571	PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
   1572	PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
   1573	PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
   1574	PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
   1575	PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
   1576	PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
   1577	PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
   1578	PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
   1579	PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
   1580	PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
   1581	PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
   1582	PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
   1583	PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
   1584
   1585	/* IPSR14 */
   1586	PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
   1587	PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
   1588	PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
   1589	PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
   1590	PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
   1591	PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
   1592	PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
   1593	PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
   1594	PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
   1595	PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
   1596	PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
   1597	PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
   1598	PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
   1599	PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
   1600	PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
   1601	PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
   1602	PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
   1603	PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
   1604	PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
   1605	PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
   1606	PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
   1607	PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
   1608	PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
   1609	PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
   1610	PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
   1611	PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
   1612	PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
   1613	PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
   1614	PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
   1615	PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
   1616	PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
   1617	PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
   1618	PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
   1619	PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
   1620	PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
   1621	PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
   1622	PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
   1623	PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
   1624	PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
   1625	PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
   1626	PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
   1627	PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
   1628	PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
   1629	PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
   1630	PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
   1631	PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
   1632	PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
   1633	PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
   1634	PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
   1635	PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
   1636	PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
   1637	PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
   1638	PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
   1639	PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
   1640	PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
   1641	PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
   1642	PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
   1643
   1644	/* IPSR15 */
   1645	PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
   1646	PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
   1647	PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
   1648	PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
   1649	PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
   1650	PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
   1651	PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
   1652	PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
   1653	PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
   1654	PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
   1655	PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
   1656	PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
   1657	PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
   1658	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
   1659	PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
   1660	PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
   1661	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
   1662	PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
   1663	PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
   1664	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
   1665	PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
   1666	PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
   1667	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
   1668	PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
   1669	PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
   1670	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
   1671	PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
   1672	PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
   1673	PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
   1674	PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
   1675	PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
   1676	PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
   1677	PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
   1678	PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
   1679	PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
   1680	PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
   1681	PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
   1682	PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
   1683	PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
   1684	PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
   1685	PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
   1686	PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
   1687	PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
   1688	PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
   1689	PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
   1690	PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
   1691	PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
   1692	PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
   1693	PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
   1694	PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
   1695	PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
   1696
   1697	/* IPSR16 */
   1698	PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
   1699	PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
   1700	PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
   1701	PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
   1702	PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
   1703	PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
   1704	PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
   1705	PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
   1706	PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
   1707	PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
   1708	PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
   1709	PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
   1710	PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
   1711	PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
   1712	PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
   1713	PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
   1714	PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
   1715	PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
   1716	PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
   1717	PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
   1718	PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
   1719	PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
   1720};
   1721
   1722/*
   1723 * Pins not associated with a GPIO port.
   1724 */
   1725enum {
   1726	GP_ASSIGN_LAST(),
   1727	NOGP_ALL(),
   1728};
   1729
   1730static const struct sh_pfc_pin pinmux_pins[] = {
   1731	PINMUX_GPIO_GP_ALL(),
   1732	PINMUX_NOGP_ALL(),
   1733};
   1734
   1735#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   1736/* - ADI -------------------------------------------------------------------- */
   1737static const unsigned int adi_common_pins[] = {
   1738	/* ADIDATA, ADICS/SAMP, ADICLK */
   1739	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
   1740};
   1741static const unsigned int adi_common_mux[] = {
   1742	/* ADIDATA, ADICS/SAMP, ADICLK */
   1743	ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
   1744};
   1745static const unsigned int adi_chsel0_pins[] = {
   1746	/* ADICHS 0 */
   1747	RCAR_GP_PIN(6, 27),
   1748};
   1749static const unsigned int adi_chsel0_mux[] = {
   1750	/* ADICHS 0 */
   1751	ADICHS0_MARK,
   1752};
   1753static const unsigned int adi_chsel1_pins[] = {
   1754	/* ADICHS 1 */
   1755	RCAR_GP_PIN(6, 28),
   1756};
   1757static const unsigned int adi_chsel1_mux[] = {
   1758	/* ADICHS 1 */
   1759	ADICHS1_MARK,
   1760};
   1761static const unsigned int adi_chsel2_pins[] = {
   1762	/* ADICHS 2 */
   1763	RCAR_GP_PIN(6, 29),
   1764};
   1765static const unsigned int adi_chsel2_mux[] = {
   1766	/* ADICHS 2 */
   1767	ADICHS2_MARK,
   1768};
   1769static const unsigned int adi_common_b_pins[] = {
   1770	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
   1771	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
   1772};
   1773static const unsigned int adi_common_b_mux[] = {
   1774	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
   1775	ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
   1776};
   1777static const unsigned int adi_chsel0_b_pins[] = {
   1778	/* ADICHS B 0 */
   1779	RCAR_GP_PIN(5, 28),
   1780};
   1781static const unsigned int adi_chsel0_b_mux[] = {
   1782	/* ADICHS B 0 */
   1783	ADICHS0_B_MARK,
   1784};
   1785static const unsigned int adi_chsel1_b_pins[] = {
   1786	/* ADICHS B 1 */
   1787	RCAR_GP_PIN(5, 29),
   1788};
   1789static const unsigned int adi_chsel1_b_mux[] = {
   1790	/* ADICHS B 1 */
   1791	ADICHS1_B_MARK,
   1792};
   1793static const unsigned int adi_chsel2_b_pins[] = {
   1794	/* ADICHS B 2 */
   1795	RCAR_GP_PIN(5, 30),
   1796};
   1797static const unsigned int adi_chsel2_b_mux[] = {
   1798	/* ADICHS B 2 */
   1799	ADICHS2_B_MARK,
   1800};
   1801#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   1802
   1803/* - Audio Clock ------------------------------------------------------------ */
   1804static const unsigned int audio_clk_a_pins[] = {
   1805	/* CLK */
   1806	RCAR_GP_PIN(2, 28),
   1807};
   1808
   1809static const unsigned int audio_clk_a_mux[] = {
   1810	AUDIO_CLKA_MARK,
   1811};
   1812
   1813static const unsigned int audio_clk_b_pins[] = {
   1814	/* CLK */
   1815	RCAR_GP_PIN(2, 29),
   1816};
   1817
   1818static const unsigned int audio_clk_b_mux[] = {
   1819	AUDIO_CLKB_MARK,
   1820};
   1821
   1822static const unsigned int audio_clk_b_b_pins[] = {
   1823	/* CLK */
   1824	RCAR_GP_PIN(7, 20),
   1825};
   1826
   1827static const unsigned int audio_clk_b_b_mux[] = {
   1828	AUDIO_CLKB_B_MARK,
   1829};
   1830
   1831static const unsigned int audio_clk_c_pins[] = {
   1832	/* CLK */
   1833	RCAR_GP_PIN(2, 30),
   1834};
   1835
   1836static const unsigned int audio_clk_c_mux[] = {
   1837	AUDIO_CLKC_MARK,
   1838};
   1839
   1840static const unsigned int audio_clkout_pins[] = {
   1841	/* CLK */
   1842	RCAR_GP_PIN(2, 31),
   1843};
   1844
   1845static const unsigned int audio_clkout_mux[] = {
   1846	AUDIO_CLKOUT_MARK,
   1847};
   1848
   1849/* - AVB -------------------------------------------------------------------- */
   1850static const unsigned int avb_link_pins[] = {
   1851	RCAR_GP_PIN(5, 14),
   1852};
   1853static const unsigned int avb_link_mux[] = {
   1854	AVB_LINK_MARK,
   1855};
   1856static const unsigned int avb_magic_pins[] = {
   1857	RCAR_GP_PIN(5, 11),
   1858};
   1859static const unsigned int avb_magic_mux[] = {
   1860	AVB_MAGIC_MARK,
   1861};
   1862static const unsigned int avb_phy_int_pins[] = {
   1863	RCAR_GP_PIN(5, 16),
   1864};
   1865static const unsigned int avb_phy_int_mux[] = {
   1866	AVB_PHY_INT_MARK,
   1867};
   1868static const unsigned int avb_mdio_pins[] = {
   1869	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
   1870};
   1871static const unsigned int avb_mdio_mux[] = {
   1872	AVB_MDC_MARK, AVB_MDIO_MARK,
   1873};
   1874static const unsigned int avb_mii_pins[] = {
   1875	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
   1876	RCAR_GP_PIN(5, 21),
   1877
   1878	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
   1879	RCAR_GP_PIN(5, 3),
   1880
   1881	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
   1882	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
   1883	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
   1884};
   1885static const unsigned int avb_mii_mux[] = {
   1886	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
   1887	AVB_TXD3_MARK,
   1888
   1889	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
   1890	AVB_RXD3_MARK,
   1891
   1892	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
   1893	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
   1894	AVB_TX_CLK_MARK, AVB_COL_MARK,
   1895};
   1896static const unsigned int avb_gmii_pins[] = {
   1897	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
   1898	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
   1899	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
   1900
   1901	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
   1902	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
   1903	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
   1904
   1905	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
   1906	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
   1907	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
   1908	RCAR_GP_PIN(5, 29),
   1909};
   1910static const unsigned int avb_gmii_mux[] = {
   1911	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
   1912	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
   1913	AVB_TXD6_MARK, AVB_TXD7_MARK,
   1914
   1915	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
   1916	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
   1917	AVB_RXD6_MARK, AVB_RXD7_MARK,
   1918
   1919	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
   1920	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
   1921	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
   1922	AVB_COL_MARK,
   1923};
   1924
   1925/* - CAN -------------------------------------------------------------------- */
   1926
   1927static const unsigned int can0_data_pins[] = {
   1928	/* TX, RX */
   1929	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
   1930};
   1931
   1932static const unsigned int can0_data_mux[] = {
   1933	CAN0_TX_MARK, CAN0_RX_MARK,
   1934};
   1935
   1936static const unsigned int can0_data_b_pins[] = {
   1937	/* TX, RX */
   1938	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
   1939};
   1940
   1941static const unsigned int can0_data_b_mux[] = {
   1942	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
   1943};
   1944
   1945static const unsigned int can0_data_c_pins[] = {
   1946	/* TX, RX */
   1947	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
   1948};
   1949
   1950static const unsigned int can0_data_c_mux[] = {
   1951	CAN0_TX_C_MARK,	CAN0_RX_C_MARK,
   1952};
   1953
   1954static const unsigned int can0_data_d_pins[] = {
   1955	/* TX, RX */
   1956	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
   1957};
   1958
   1959static const unsigned int can0_data_d_mux[] = {
   1960	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
   1961};
   1962
   1963static const unsigned int can0_data_e_pins[] = {
   1964	/* TX, RX */
   1965	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
   1966};
   1967
   1968static const unsigned int can0_data_e_mux[] = {
   1969	CAN0_TX_E_MARK, CAN0_RX_E_MARK,
   1970};
   1971
   1972static const unsigned int can0_data_f_pins[] = {
   1973	/* TX, RX */
   1974	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
   1975};
   1976
   1977static const unsigned int can0_data_f_mux[] = {
   1978	CAN0_TX_F_MARK, CAN0_RX_F_MARK,
   1979};
   1980
   1981static const unsigned int can1_data_pins[] = {
   1982	/* TX, RX */
   1983	 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
   1984};
   1985
   1986static const unsigned int can1_data_mux[] = {
   1987	CAN1_TX_MARK, CAN1_RX_MARK,
   1988};
   1989
   1990static const unsigned int can1_data_b_pins[] = {
   1991	/* TX, RX */
   1992	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
   1993};
   1994
   1995static const unsigned int can1_data_b_mux[] = {
   1996	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
   1997};
   1998
   1999static const unsigned int can1_data_c_pins[] = {
   2000	/* TX, RX */
   2001	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
   2002};
   2003
   2004static const unsigned int can1_data_c_mux[] = {
   2005	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
   2006};
   2007
   2008static const unsigned int can1_data_d_pins[] = {
   2009	/* TX, RX */
   2010	 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
   2011};
   2012
   2013static const unsigned int can1_data_d_mux[] = {
   2014	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
   2015};
   2016
   2017static const unsigned int can_clk_pins[] = {
   2018	/* CLK */
   2019	RCAR_GP_PIN(7, 2),
   2020};
   2021
   2022static const unsigned int can_clk_mux[] = {
   2023	CAN_CLK_MARK,
   2024};
   2025
   2026static const unsigned int can_clk_b_pins[] = {
   2027	/* CLK */
   2028	RCAR_GP_PIN(5, 21),
   2029};
   2030
   2031static const unsigned int can_clk_b_mux[] = {
   2032	CAN_CLK_B_MARK,
   2033};
   2034
   2035static const unsigned int can_clk_c_pins[] = {
   2036	/* CLK */
   2037	RCAR_GP_PIN(4, 30),
   2038};
   2039
   2040static const unsigned int can_clk_c_mux[] = {
   2041	CAN_CLK_C_MARK,
   2042};
   2043
   2044static const unsigned int can_clk_d_pins[] = {
   2045	/* CLK */
   2046	RCAR_GP_PIN(7, 19),
   2047};
   2048
   2049static const unsigned int can_clk_d_mux[] = {
   2050	CAN_CLK_D_MARK,
   2051};
   2052
   2053/* - DU --------------------------------------------------------------------- */
   2054static const unsigned int du_rgb666_pins[] = {
   2055	/* R[7:2], G[7:2], B[7:2] */
   2056	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
   2057	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
   2058	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
   2059	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
   2060	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
   2061	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
   2062};
   2063static const unsigned int du_rgb666_mux[] = {
   2064	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
   2065	DU1_DR3_MARK, DU1_DR2_MARK,
   2066	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
   2067	DU1_DG3_MARK, DU1_DG2_MARK,
   2068	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
   2069	DU1_DB3_MARK, DU1_DB2_MARK,
   2070};
   2071static const unsigned int du_rgb888_pins[] = {
   2072	/* R[7:0], G[7:0], B[7:0] */
   2073	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
   2074	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
   2075	RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
   2076	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
   2077	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
   2078	RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
   2079	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
   2080	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
   2081	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
   2082};
   2083static const unsigned int du_rgb888_mux[] = {
   2084	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
   2085	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
   2086	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
   2087	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
   2088	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
   2089	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
   2090};
   2091static const unsigned int du_clk_out_0_pins[] = {
   2092	/* CLKOUT */
   2093	RCAR_GP_PIN(3, 25),
   2094};
   2095static const unsigned int du_clk_out_0_mux[] = {
   2096	DU1_DOTCLKOUT0_MARK
   2097};
   2098static const unsigned int du_clk_out_1_pins[] = {
   2099	/* CLKOUT */
   2100	RCAR_GP_PIN(3, 26),
   2101};
   2102static const unsigned int du_clk_out_1_mux[] = {
   2103	DU1_DOTCLKOUT1_MARK
   2104};
   2105static const unsigned int du_sync_pins[] = {
   2106	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
   2107	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
   2108};
   2109static const unsigned int du_sync_mux[] = {
   2110	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
   2111};
   2112static const unsigned int du_oddf_pins[] = {
   2113	/* EXDISP/EXODDF/EXCDE */
   2114	RCAR_GP_PIN(3, 29),
   2115};
   2116static const unsigned int du_oddf_mux[] = {
   2117	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
   2118};
   2119static const unsigned int du_cde_pins[] = {
   2120	/* CDE */
   2121	RCAR_GP_PIN(3, 31),
   2122};
   2123static const unsigned int du_cde_mux[] = {
   2124	DU1_CDE_MARK,
   2125};
   2126static const unsigned int du_disp_pins[] = {
   2127	/* DISP */
   2128	RCAR_GP_PIN(3, 30),
   2129};
   2130static const unsigned int du_disp_mux[] = {
   2131	DU1_DISP_MARK,
   2132};
   2133static const unsigned int du0_clk_in_pins[] = {
   2134	/* CLKIN */
   2135	RCAR_GP_PIN(6, 31),
   2136};
   2137static const unsigned int du0_clk_in_mux[] = {
   2138	DU0_DOTCLKIN_MARK
   2139};
   2140static const unsigned int du1_clk_in_pins[] = {
   2141	/* CLKIN */
   2142	RCAR_GP_PIN(3, 24),
   2143};
   2144static const unsigned int du1_clk_in_mux[] = {
   2145	DU1_DOTCLKIN_MARK
   2146};
   2147static const unsigned int du1_clk_in_b_pins[] = {
   2148	/* CLKIN */
   2149	RCAR_GP_PIN(7, 19),
   2150};
   2151static const unsigned int du1_clk_in_b_mux[] = {
   2152	DU1_DOTCLKIN_B_MARK,
   2153};
   2154static const unsigned int du1_clk_in_c_pins[] = {
   2155	/* CLKIN */
   2156	RCAR_GP_PIN(7, 20),
   2157};
   2158static const unsigned int du1_clk_in_c_mux[] = {
   2159	DU1_DOTCLKIN_C_MARK,
   2160};
   2161/* - ETH -------------------------------------------------------------------- */
   2162static const unsigned int eth_link_pins[] = {
   2163	/* LINK */
   2164	RCAR_GP_PIN(5, 18),
   2165};
   2166static const unsigned int eth_link_mux[] = {
   2167	ETH_LINK_MARK,
   2168};
   2169static const unsigned int eth_magic_pins[] = {
   2170	/* MAGIC */
   2171	RCAR_GP_PIN(5, 22),
   2172};
   2173static const unsigned int eth_magic_mux[] = {
   2174	ETH_MAGIC_MARK,
   2175};
   2176static const unsigned int eth_mdio_pins[] = {
   2177	/* MDC, MDIO */
   2178	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
   2179};
   2180static const unsigned int eth_mdio_mux[] = {
   2181	ETH_MDC_MARK, ETH_MDIO_MARK,
   2182};
   2183static const unsigned int eth_rmii_pins[] = {
   2184	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
   2185	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
   2186	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
   2187	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
   2188};
   2189static const unsigned int eth_rmii_mux[] = {
   2190	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
   2191	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
   2192};
   2193
   2194/* - HSCIF0 ----------------------------------------------------------------- */
   2195static const unsigned int hscif0_data_pins[] = {
   2196	/* RX, TX */
   2197	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
   2198};
   2199static const unsigned int hscif0_data_mux[] = {
   2200	HRX0_MARK, HTX0_MARK,
   2201};
   2202static const unsigned int hscif0_clk_pins[] = {
   2203	/* SCK */
   2204	RCAR_GP_PIN(7, 2),
   2205};
   2206static const unsigned int hscif0_clk_mux[] = {
   2207	HSCK0_MARK,
   2208};
   2209static const unsigned int hscif0_ctrl_pins[] = {
   2210	/* RTS, CTS */
   2211	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
   2212};
   2213static const unsigned int hscif0_ctrl_mux[] = {
   2214	HRTS0_N_MARK, HCTS0_N_MARK,
   2215};
   2216static const unsigned int hscif0_data_b_pins[] = {
   2217	/* RX, TX */
   2218	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
   2219};
   2220static const unsigned int hscif0_data_b_mux[] = {
   2221	HRX0_B_MARK, HTX0_B_MARK,
   2222};
   2223static const unsigned int hscif0_ctrl_b_pins[] = {
   2224	/* RTS, CTS */
   2225	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
   2226};
   2227static const unsigned int hscif0_ctrl_b_mux[] = {
   2228	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
   2229};
   2230static const unsigned int hscif0_data_c_pins[] = {
   2231	/* RX, TX */
   2232	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
   2233};
   2234static const unsigned int hscif0_data_c_mux[] = {
   2235	HRX0_C_MARK, HTX0_C_MARK,
   2236};
   2237static const unsigned int hscif0_clk_c_pins[] = {
   2238	/* SCK */
   2239	RCAR_GP_PIN(5, 31),
   2240};
   2241static const unsigned int hscif0_clk_c_mux[] = {
   2242	HSCK0_C_MARK,
   2243};
   2244/* - HSCIF1 ----------------------------------------------------------------- */
   2245static const unsigned int hscif1_data_pins[] = {
   2246	/* RX, TX */
   2247	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
   2248};
   2249static const unsigned int hscif1_data_mux[] = {
   2250	HRX1_MARK, HTX1_MARK,
   2251};
   2252static const unsigned int hscif1_clk_pins[] = {
   2253	/* SCK */
   2254	RCAR_GP_PIN(7, 7),
   2255};
   2256static const unsigned int hscif1_clk_mux[] = {
   2257	HSCK1_MARK,
   2258};
   2259static const unsigned int hscif1_ctrl_pins[] = {
   2260	/* RTS, CTS */
   2261	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
   2262};
   2263static const unsigned int hscif1_ctrl_mux[] = {
   2264	HRTS1_N_MARK, HCTS1_N_MARK,
   2265};
   2266static const unsigned int hscif1_data_b_pins[] = {
   2267	/* RX, TX */
   2268	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
   2269};
   2270static const unsigned int hscif1_data_b_mux[] = {
   2271	HRX1_B_MARK, HTX1_B_MARK,
   2272};
   2273static const unsigned int hscif1_data_c_pins[] = {
   2274	/* RX, TX */
   2275	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
   2276};
   2277static const unsigned int hscif1_data_c_mux[] = {
   2278	HRX1_C_MARK, HTX1_C_MARK,
   2279};
   2280static const unsigned int hscif1_clk_c_pins[] = {
   2281	/* SCK */
   2282	RCAR_GP_PIN(7, 16),
   2283};
   2284static const unsigned int hscif1_clk_c_mux[] = {
   2285	HSCK1_C_MARK,
   2286};
   2287static const unsigned int hscif1_ctrl_c_pins[] = {
   2288	/* RTS, CTS */
   2289	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
   2290};
   2291static const unsigned int hscif1_ctrl_c_mux[] = {
   2292	HRTS1_N_C_MARK, HCTS1_N_C_MARK,
   2293};
   2294static const unsigned int hscif1_data_d_pins[] = {
   2295	/* RX, TX */
   2296	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
   2297};
   2298static const unsigned int hscif1_data_d_mux[] = {
   2299	HRX1_D_MARK, HTX1_D_MARK,
   2300};
   2301static const unsigned int hscif1_clk_e_pins[] = {
   2302	/* SCK */
   2303	RCAR_GP_PIN(2, 6),
   2304};
   2305static const unsigned int hscif1_clk_e_mux[] = {
   2306	HSCK1_E_MARK,
   2307};
   2308static const unsigned int hscif1_ctrl_e_pins[] = {
   2309	/* RTS, CTS */
   2310	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
   2311};
   2312static const unsigned int hscif1_ctrl_e_mux[] = {
   2313	HRTS1_N_E_MARK, HCTS1_N_E_MARK,
   2314};
   2315/* - HSCIF2 ----------------------------------------------------------------- */
   2316static const unsigned int hscif2_data_pins[] = {
   2317	/* RX, TX */
   2318	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
   2319};
   2320static const unsigned int hscif2_data_mux[] = {
   2321	HRX2_MARK, HTX2_MARK,
   2322};
   2323static const unsigned int hscif2_clk_pins[] = {
   2324	/* SCK */
   2325	RCAR_GP_PIN(4, 15),
   2326};
   2327static const unsigned int hscif2_clk_mux[] = {
   2328	HSCK2_MARK,
   2329};
   2330static const unsigned int hscif2_ctrl_pins[] = {
   2331	/* RTS, CTS */
   2332	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
   2333};
   2334static const unsigned int hscif2_ctrl_mux[] = {
   2335	HRTS2_N_MARK, HCTS2_N_MARK,
   2336};
   2337static const unsigned int hscif2_data_b_pins[] = {
   2338	/* RX, TX */
   2339	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
   2340};
   2341static const unsigned int hscif2_data_b_mux[] = {
   2342	HRX2_B_MARK, HTX2_B_MARK,
   2343};
   2344static const unsigned int hscif2_ctrl_b_pins[] = {
   2345	/* RTS, CTS */
   2346	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
   2347};
   2348static const unsigned int hscif2_ctrl_b_mux[] = {
   2349	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
   2350};
   2351static const unsigned int hscif2_data_c_pins[] = {
   2352	/* RX, TX */
   2353	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
   2354};
   2355static const unsigned int hscif2_data_c_mux[] = {
   2356	HRX2_C_MARK, HTX2_C_MARK,
   2357};
   2358static const unsigned int hscif2_clk_c_pins[] = {
   2359	/* SCK */
   2360	RCAR_GP_PIN(5, 31),
   2361};
   2362static const unsigned int hscif2_clk_c_mux[] = {
   2363	HSCK2_C_MARK,
   2364};
   2365static const unsigned int hscif2_data_d_pins[] = {
   2366	/* RX, TX */
   2367	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
   2368};
   2369static const unsigned int hscif2_data_d_mux[] = {
   2370	HRX2_B_MARK, HTX2_D_MARK,
   2371};
   2372/* - I2C0 ------------------------------------------------------------------- */
   2373static const unsigned int i2c0_pins[] = {
   2374	/* SCL, SDA */
   2375	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
   2376};
   2377static const unsigned int i2c0_mux[] = {
   2378	I2C0_SCL_MARK, I2C0_SDA_MARK,
   2379};
   2380static const unsigned int i2c0_b_pins[] = {
   2381	/* SCL, SDA */
   2382	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
   2383};
   2384static const unsigned int i2c0_b_mux[] = {
   2385	I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
   2386};
   2387static const unsigned int i2c0_c_pins[] = {
   2388	/* SCL, SDA */
   2389	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
   2390};
   2391static const unsigned int i2c0_c_mux[] = {
   2392	I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
   2393};
   2394/* - I2C1 ------------------------------------------------------------------- */
   2395static const unsigned int i2c1_pins[] = {
   2396	/* SCL, SDA */
   2397	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
   2398};
   2399static const unsigned int i2c1_mux[] = {
   2400	I2C1_SCL_MARK, I2C1_SDA_MARK,
   2401};
   2402static const unsigned int i2c1_b_pins[] = {
   2403	/* SCL, SDA */
   2404	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
   2405};
   2406static const unsigned int i2c1_b_mux[] = {
   2407	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
   2408};
   2409static const unsigned int i2c1_c_pins[] = {
   2410	/* SCL, SDA */
   2411	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
   2412};
   2413static const unsigned int i2c1_c_mux[] = {
   2414	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
   2415};
   2416static const unsigned int i2c1_d_pins[] = {
   2417	/* SCL, SDA */
   2418	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
   2419};
   2420static const unsigned int i2c1_d_mux[] = {
   2421	I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
   2422};
   2423static const unsigned int i2c1_e_pins[] = {
   2424	/* SCL, SDA */
   2425	RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
   2426};
   2427static const unsigned int i2c1_e_mux[] = {
   2428	I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
   2429};
   2430/* - I2C2 ------------------------------------------------------------------- */
   2431static const unsigned int i2c2_pins[] = {
   2432	/* SCL, SDA */
   2433	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
   2434};
   2435static const unsigned int i2c2_mux[] = {
   2436	I2C2_SCL_MARK, I2C2_SDA_MARK,
   2437};
   2438static const unsigned int i2c2_b_pins[] = {
   2439	/* SCL, SDA */
   2440	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
   2441};
   2442static const unsigned int i2c2_b_mux[] = {
   2443	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
   2444};
   2445static const unsigned int i2c2_c_pins[] = {
   2446	/* SCL, SDA */
   2447	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
   2448};
   2449static const unsigned int i2c2_c_mux[] = {
   2450	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
   2451};
   2452static const unsigned int i2c2_d_pins[] = {
   2453	/* SCL, SDA */
   2454	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
   2455};
   2456static const unsigned int i2c2_d_mux[] = {
   2457	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
   2458};
   2459/* - I2C3 ------------------------------------------------------------------- */
   2460static const unsigned int i2c3_pins[] = {
   2461	/* SCL, SDA */
   2462	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
   2463};
   2464static const unsigned int i2c3_mux[] = {
   2465	I2C3_SCL_MARK, I2C3_SDA_MARK,
   2466};
   2467static const unsigned int i2c3_b_pins[] = {
   2468	/* SCL, SDA */
   2469	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
   2470};
   2471static const unsigned int i2c3_b_mux[] = {
   2472	I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
   2473};
   2474static const unsigned int i2c3_c_pins[] = {
   2475	/* SCL, SDA */
   2476	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
   2477};
   2478static const unsigned int i2c3_c_mux[] = {
   2479	I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
   2480};
   2481static const unsigned int i2c3_d_pins[] = {
   2482	/* SCL, SDA */
   2483	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
   2484};
   2485static const unsigned int i2c3_d_mux[] = {
   2486	I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
   2487};
   2488/* - I2C4 ------------------------------------------------------------------- */
   2489static const unsigned int i2c4_pins[] = {
   2490	/* SCL, SDA */
   2491	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
   2492};
   2493static const unsigned int i2c4_mux[] = {
   2494	I2C4_SCL_MARK, I2C4_SDA_MARK,
   2495};
   2496static const unsigned int i2c4_b_pins[] = {
   2497	/* SCL, SDA */
   2498	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
   2499};
   2500static const unsigned int i2c4_b_mux[] = {
   2501	I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
   2502};
   2503static const unsigned int i2c4_c_pins[] = {
   2504	/* SCL, SDA */
   2505	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
   2506};
   2507static const unsigned int i2c4_c_mux[] = {
   2508	I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
   2509};
   2510/* - I2C7 ------------------------------------------------------------------- */
   2511static const unsigned int i2c7_pins[] = {
   2512	/* SCL, SDA */
   2513	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
   2514};
   2515static const unsigned int i2c7_mux[] = {
   2516	IIC0_SCL_MARK, IIC0_SDA_MARK,
   2517};
   2518static const unsigned int i2c7_b_pins[] = {
   2519	/* SCL, SDA */
   2520	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
   2521};
   2522static const unsigned int i2c7_b_mux[] = {
   2523	IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
   2524};
   2525static const unsigned int i2c7_c_pins[] = {
   2526	/* SCL, SDA */
   2527	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
   2528};
   2529static const unsigned int i2c7_c_mux[] = {
   2530	IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
   2531};
   2532/* - I2C8 ------------------------------------------------------------------- */
   2533static const unsigned int i2c8_pins[] = {
   2534	/* SCL, SDA */
   2535	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
   2536};
   2537static const unsigned int i2c8_mux[] = {
   2538	IIC1_SCL_MARK, IIC1_SDA_MARK,
   2539};
   2540static const unsigned int i2c8_b_pins[] = {
   2541	/* SCL, SDA */
   2542	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
   2543};
   2544static const unsigned int i2c8_b_mux[] = {
   2545	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
   2546};
   2547static const unsigned int i2c8_c_pins[] = {
   2548	/* SCL, SDA */
   2549	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
   2550};
   2551static const unsigned int i2c8_c_mux[] = {
   2552	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
   2553};
   2554/* - INTC ------------------------------------------------------------------- */
   2555static const unsigned int intc_irq0_pins[] = {
   2556	/* IRQ */
   2557	RCAR_GP_PIN(7, 10),
   2558};
   2559static const unsigned int intc_irq0_mux[] = {
   2560	IRQ0_MARK,
   2561};
   2562static const unsigned int intc_irq1_pins[] = {
   2563	/* IRQ */
   2564	RCAR_GP_PIN(7, 11),
   2565};
   2566static const unsigned int intc_irq1_mux[] = {
   2567	IRQ1_MARK,
   2568};
   2569static const unsigned int intc_irq2_pins[] = {
   2570	/* IRQ */
   2571	RCAR_GP_PIN(7, 12),
   2572};
   2573static const unsigned int intc_irq2_mux[] = {
   2574	IRQ2_MARK,
   2575};
   2576static const unsigned int intc_irq3_pins[] = {
   2577	/* IRQ */
   2578	RCAR_GP_PIN(7, 13),
   2579};
   2580static const unsigned int intc_irq3_mux[] = {
   2581	IRQ3_MARK,
   2582};
   2583
   2584#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   2585/* - MLB+ ------------------------------------------------------------------- */
   2586static const unsigned int mlb_3pin_pins[] = {
   2587	RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
   2588};
   2589static const unsigned int mlb_3pin_mux[] = {
   2590	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
   2591};
   2592#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   2593
   2594/* - MMCIF ------------------------------------------------------------------ */
   2595static const unsigned int mmc_data_pins[] = {
   2596	/* D[0:7] */
   2597	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
   2598	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
   2599	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
   2600	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
   2601};
   2602static const unsigned int mmc_data_mux[] = {
   2603	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
   2604	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
   2605};
   2606static const unsigned int mmc_data_b_pins[] = {
   2607	/* D[0:7] */
   2608	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
   2609	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
   2610	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
   2611	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
   2612};
   2613static const unsigned int mmc_data_b_mux[] = {
   2614	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
   2615	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
   2616};
   2617static const unsigned int mmc_ctrl_pins[] = {
   2618	/* CLK, CMD */
   2619	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
   2620};
   2621static const unsigned int mmc_ctrl_mux[] = {
   2622	MMC_CLK_MARK, MMC_CMD_MARK,
   2623};
   2624/* - MSIOF0 ----------------------------------------------------------------- */
   2625static const unsigned int msiof0_clk_pins[] = {
   2626	/* SCK */
   2627	RCAR_GP_PIN(6, 24),
   2628};
   2629static const unsigned int msiof0_clk_mux[] = {
   2630	MSIOF0_SCK_MARK,
   2631};
   2632static const unsigned int msiof0_sync_pins[] = {
   2633	/* SYNC */
   2634	RCAR_GP_PIN(6, 25),
   2635};
   2636static const unsigned int msiof0_sync_mux[] = {
   2637	MSIOF0_SYNC_MARK,
   2638};
   2639static const unsigned int msiof0_ss1_pins[] = {
   2640	/* SS1 */
   2641	RCAR_GP_PIN(6, 28),
   2642};
   2643static const unsigned int msiof0_ss1_mux[] = {
   2644	MSIOF0_SS1_MARK,
   2645};
   2646static const unsigned int msiof0_ss2_pins[] = {
   2647	/* SS2 */
   2648	RCAR_GP_PIN(6, 29),
   2649};
   2650static const unsigned int msiof0_ss2_mux[] = {
   2651	MSIOF0_SS2_MARK,
   2652};
   2653static const unsigned int msiof0_rx_pins[] = {
   2654	/* RXD */
   2655	RCAR_GP_PIN(6, 27),
   2656};
   2657static const unsigned int msiof0_rx_mux[] = {
   2658	MSIOF0_RXD_MARK,
   2659};
   2660static const unsigned int msiof0_tx_pins[] = {
   2661	/* TXD */
   2662	RCAR_GP_PIN(6, 26),
   2663};
   2664static const unsigned int msiof0_tx_mux[] = {
   2665	MSIOF0_TXD_MARK,
   2666};
   2667
   2668static const unsigned int msiof0_clk_b_pins[] = {
   2669	/* SCK */
   2670	RCAR_GP_PIN(0, 16),
   2671};
   2672static const unsigned int msiof0_clk_b_mux[] = {
   2673	MSIOF0_SCK_B_MARK,
   2674};
   2675static const unsigned int msiof0_sync_b_pins[] = {
   2676	/* SYNC */
   2677	RCAR_GP_PIN(0, 17),
   2678};
   2679static const unsigned int msiof0_sync_b_mux[] = {
   2680	MSIOF0_SYNC_B_MARK,
   2681};
   2682static const unsigned int msiof0_ss1_b_pins[] = {
   2683	/* SS1 */
   2684	RCAR_GP_PIN(0, 18),
   2685};
   2686static const unsigned int msiof0_ss1_b_mux[] = {
   2687	MSIOF0_SS1_B_MARK,
   2688};
   2689static const unsigned int msiof0_ss2_b_pins[] = {
   2690	/* SS2 */
   2691	RCAR_GP_PIN(0, 19),
   2692};
   2693static const unsigned int msiof0_ss2_b_mux[] = {
   2694	MSIOF0_SS2_B_MARK,
   2695};
   2696static const unsigned int msiof0_rx_b_pins[] = {
   2697	/* RXD */
   2698	RCAR_GP_PIN(0, 21),
   2699};
   2700static const unsigned int msiof0_rx_b_mux[] = {
   2701	MSIOF0_RXD_B_MARK,
   2702};
   2703static const unsigned int msiof0_tx_b_pins[] = {
   2704	/* TXD */
   2705	RCAR_GP_PIN(0, 20),
   2706};
   2707static const unsigned int msiof0_tx_b_mux[] = {
   2708	MSIOF0_TXD_B_MARK,
   2709};
   2710
   2711static const unsigned int msiof0_clk_c_pins[] = {
   2712	/* SCK */
   2713	RCAR_GP_PIN(5, 26),
   2714};
   2715static const unsigned int msiof0_clk_c_mux[] = {
   2716	MSIOF0_SCK_C_MARK,
   2717};
   2718static const unsigned int msiof0_sync_c_pins[] = {
   2719	/* SYNC */
   2720	RCAR_GP_PIN(5, 25),
   2721};
   2722static const unsigned int msiof0_sync_c_mux[] = {
   2723	MSIOF0_SYNC_C_MARK,
   2724};
   2725static const unsigned int msiof0_ss1_c_pins[] = {
   2726	/* SS1 */
   2727	RCAR_GP_PIN(5, 27),
   2728};
   2729static const unsigned int msiof0_ss1_c_mux[] = {
   2730	MSIOF0_SS1_C_MARK,
   2731};
   2732static const unsigned int msiof0_ss2_c_pins[] = {
   2733	/* SS2 */
   2734	RCAR_GP_PIN(5, 28),
   2735};
   2736static const unsigned int msiof0_ss2_c_mux[] = {
   2737	MSIOF0_SS2_C_MARK,
   2738};
   2739static const unsigned int msiof0_rx_c_pins[] = {
   2740	/* RXD */
   2741	RCAR_GP_PIN(5, 29),
   2742};
   2743static const unsigned int msiof0_rx_c_mux[] = {
   2744	MSIOF0_RXD_C_MARK,
   2745};
   2746static const unsigned int msiof0_tx_c_pins[] = {
   2747	/* TXD */
   2748	RCAR_GP_PIN(5, 30),
   2749};
   2750static const unsigned int msiof0_tx_c_mux[] = {
   2751	MSIOF0_TXD_C_MARK,
   2752};
   2753/* - MSIOF1 ----------------------------------------------------------------- */
   2754static const unsigned int msiof1_clk_pins[] = {
   2755	/* SCK */
   2756	RCAR_GP_PIN(0, 22),
   2757};
   2758static const unsigned int msiof1_clk_mux[] = {
   2759	MSIOF1_SCK_MARK,
   2760};
   2761static const unsigned int msiof1_sync_pins[] = {
   2762	/* SYNC */
   2763	RCAR_GP_PIN(0, 23),
   2764};
   2765static const unsigned int msiof1_sync_mux[] = {
   2766	MSIOF1_SYNC_MARK,
   2767};
   2768static const unsigned int msiof1_ss1_pins[] = {
   2769	/* SS1 */
   2770	RCAR_GP_PIN(0, 24),
   2771};
   2772static const unsigned int msiof1_ss1_mux[] = {
   2773	MSIOF1_SS1_MARK,
   2774};
   2775static const unsigned int msiof1_ss2_pins[] = {
   2776	/* SS2 */
   2777	RCAR_GP_PIN(0, 25),
   2778};
   2779static const unsigned int msiof1_ss2_mux[] = {
   2780	MSIOF1_SS2_MARK,
   2781};
   2782static const unsigned int msiof1_rx_pins[] = {
   2783	/* RXD */
   2784	RCAR_GP_PIN(0, 27),
   2785};
   2786static const unsigned int msiof1_rx_mux[] = {
   2787	MSIOF1_RXD_MARK,
   2788};
   2789static const unsigned int msiof1_tx_pins[] = {
   2790	/* TXD */
   2791	RCAR_GP_PIN(0, 26),
   2792};
   2793static const unsigned int msiof1_tx_mux[] = {
   2794	MSIOF1_TXD_MARK,
   2795};
   2796
   2797static const unsigned int msiof1_clk_b_pins[] = {
   2798	/* SCK */
   2799	RCAR_GP_PIN(2, 29),
   2800};
   2801static const unsigned int msiof1_clk_b_mux[] = {
   2802	MSIOF1_SCK_B_MARK,
   2803};
   2804static const unsigned int msiof1_sync_b_pins[] = {
   2805	/* SYNC */
   2806	RCAR_GP_PIN(2, 30),
   2807};
   2808static const unsigned int msiof1_sync_b_mux[] = {
   2809	MSIOF1_SYNC_B_MARK,
   2810};
   2811static const unsigned int msiof1_ss1_b_pins[] = {
   2812	/* SS1 */
   2813	RCAR_GP_PIN(2, 31),
   2814};
   2815static const unsigned int msiof1_ss1_b_mux[] = {
   2816	MSIOF1_SS1_B_MARK,
   2817};
   2818static const unsigned int msiof1_ss2_b_pins[] = {
   2819	/* SS2 */
   2820	RCAR_GP_PIN(7, 16),
   2821};
   2822static const unsigned int msiof1_ss2_b_mux[] = {
   2823	MSIOF1_SS2_B_MARK,
   2824};
   2825static const unsigned int msiof1_rx_b_pins[] = {
   2826	/* RXD */
   2827	RCAR_GP_PIN(7, 18),
   2828};
   2829static const unsigned int msiof1_rx_b_mux[] = {
   2830	MSIOF1_RXD_B_MARK,
   2831};
   2832static const unsigned int msiof1_tx_b_pins[] = {
   2833	/* TXD */
   2834	RCAR_GP_PIN(7, 17),
   2835};
   2836static const unsigned int msiof1_tx_b_mux[] = {
   2837	MSIOF1_TXD_B_MARK,
   2838};
   2839
   2840static const unsigned int msiof1_clk_c_pins[] = {
   2841	/* SCK */
   2842	RCAR_GP_PIN(2, 15),
   2843};
   2844static const unsigned int msiof1_clk_c_mux[] = {
   2845	MSIOF1_SCK_C_MARK,
   2846};
   2847static const unsigned int msiof1_sync_c_pins[] = {
   2848	/* SYNC */
   2849	RCAR_GP_PIN(2, 16),
   2850};
   2851static const unsigned int msiof1_sync_c_mux[] = {
   2852	MSIOF1_SYNC_C_MARK,
   2853};
   2854static const unsigned int msiof1_rx_c_pins[] = {
   2855	/* RXD */
   2856	RCAR_GP_PIN(2, 18),
   2857};
   2858static const unsigned int msiof1_rx_c_mux[] = {
   2859	MSIOF1_RXD_C_MARK,
   2860};
   2861static const unsigned int msiof1_tx_c_pins[] = {
   2862	/* TXD */
   2863	RCAR_GP_PIN(2, 17),
   2864};
   2865static const unsigned int msiof1_tx_c_mux[] = {
   2866	MSIOF1_TXD_C_MARK,
   2867};
   2868
   2869static const unsigned int msiof1_clk_d_pins[] = {
   2870	/* SCK */
   2871	RCAR_GP_PIN(0, 28),
   2872};
   2873static const unsigned int msiof1_clk_d_mux[] = {
   2874	MSIOF1_SCK_D_MARK,
   2875};
   2876static const unsigned int msiof1_sync_d_pins[] = {
   2877	/* SYNC */
   2878	RCAR_GP_PIN(0, 30),
   2879};
   2880static const unsigned int msiof1_sync_d_mux[] = {
   2881	MSIOF1_SYNC_D_MARK,
   2882};
   2883static const unsigned int msiof1_ss1_d_pins[] = {
   2884	/* SS1 */
   2885	RCAR_GP_PIN(0, 29),
   2886};
   2887static const unsigned int msiof1_ss1_d_mux[] = {
   2888	MSIOF1_SS1_D_MARK,
   2889};
   2890static const unsigned int msiof1_rx_d_pins[] = {
   2891	/* RXD */
   2892	RCAR_GP_PIN(0, 27),
   2893};
   2894static const unsigned int msiof1_rx_d_mux[] = {
   2895	MSIOF1_RXD_D_MARK,
   2896};
   2897static const unsigned int msiof1_tx_d_pins[] = {
   2898	/* TXD */
   2899	RCAR_GP_PIN(0, 26),
   2900};
   2901static const unsigned int msiof1_tx_d_mux[] = {
   2902	MSIOF1_TXD_D_MARK,
   2903};
   2904
   2905static const unsigned int msiof1_clk_e_pins[] = {
   2906	/* SCK */
   2907	RCAR_GP_PIN(5, 18),
   2908};
   2909static const unsigned int msiof1_clk_e_mux[] = {
   2910	MSIOF1_SCK_E_MARK,
   2911};
   2912static const unsigned int msiof1_sync_e_pins[] = {
   2913	/* SYNC */
   2914	RCAR_GP_PIN(5, 19),
   2915};
   2916static const unsigned int msiof1_sync_e_mux[] = {
   2917	MSIOF1_SYNC_E_MARK,
   2918};
   2919static const unsigned int msiof1_rx_e_pins[] = {
   2920	/* RXD */
   2921	RCAR_GP_PIN(5, 17),
   2922};
   2923static const unsigned int msiof1_rx_e_mux[] = {
   2924	MSIOF1_RXD_E_MARK,
   2925};
   2926static const unsigned int msiof1_tx_e_pins[] = {
   2927	/* TXD */
   2928	RCAR_GP_PIN(5, 20),
   2929};
   2930static const unsigned int msiof1_tx_e_mux[] = {
   2931	MSIOF1_TXD_E_MARK,
   2932};
   2933/* - MSIOF2 ----------------------------------------------------------------- */
   2934static const unsigned int msiof2_clk_pins[] = {
   2935	/* SCK */
   2936	RCAR_GP_PIN(1, 13),
   2937};
   2938static const unsigned int msiof2_clk_mux[] = {
   2939	MSIOF2_SCK_MARK,
   2940};
   2941static const unsigned int msiof2_sync_pins[] = {
   2942	/* SYNC */
   2943	RCAR_GP_PIN(1, 14),
   2944};
   2945static const unsigned int msiof2_sync_mux[] = {
   2946	MSIOF2_SYNC_MARK,
   2947};
   2948static const unsigned int msiof2_ss1_pins[] = {
   2949	/* SS1 */
   2950	RCAR_GP_PIN(1, 17),
   2951};
   2952static const unsigned int msiof2_ss1_mux[] = {
   2953	MSIOF2_SS1_MARK,
   2954};
   2955static const unsigned int msiof2_ss2_pins[] = {
   2956	/* SS2 */
   2957	RCAR_GP_PIN(1, 18),
   2958};
   2959static const unsigned int msiof2_ss2_mux[] = {
   2960	MSIOF2_SS2_MARK,
   2961};
   2962static const unsigned int msiof2_rx_pins[] = {
   2963	/* RXD */
   2964	RCAR_GP_PIN(1, 16),
   2965};
   2966static const unsigned int msiof2_rx_mux[] = {
   2967	MSIOF2_RXD_MARK,
   2968};
   2969static const unsigned int msiof2_tx_pins[] = {
   2970	/* TXD */
   2971	RCAR_GP_PIN(1, 15),
   2972};
   2973static const unsigned int msiof2_tx_mux[] = {
   2974	MSIOF2_TXD_MARK,
   2975};
   2976
   2977static const unsigned int msiof2_clk_b_pins[] = {
   2978	/* SCK */
   2979	RCAR_GP_PIN(3, 0),
   2980};
   2981static const unsigned int msiof2_clk_b_mux[] = {
   2982	MSIOF2_SCK_B_MARK,
   2983};
   2984static const unsigned int msiof2_sync_b_pins[] = {
   2985	/* SYNC */
   2986	RCAR_GP_PIN(3, 1),
   2987};
   2988static const unsigned int msiof2_sync_b_mux[] = {
   2989	MSIOF2_SYNC_B_MARK,
   2990};
   2991static const unsigned int msiof2_ss1_b_pins[] = {
   2992	/* SS1 */
   2993	RCAR_GP_PIN(3, 8),
   2994};
   2995static const unsigned int msiof2_ss1_b_mux[] = {
   2996	MSIOF2_SS1_B_MARK,
   2997};
   2998static const unsigned int msiof2_ss2_b_pins[] = {
   2999	/* SS2 */
   3000	RCAR_GP_PIN(3, 9),
   3001};
   3002static const unsigned int msiof2_ss2_b_mux[] = {
   3003	MSIOF2_SS2_B_MARK,
   3004};
   3005static const unsigned int msiof2_rx_b_pins[] = {
   3006	/* RXD */
   3007	RCAR_GP_PIN(3, 17),
   3008};
   3009static const unsigned int msiof2_rx_b_mux[] = {
   3010	MSIOF2_RXD_B_MARK,
   3011};
   3012static const unsigned int msiof2_tx_b_pins[] = {
   3013	/* TXD */
   3014	RCAR_GP_PIN(3, 16),
   3015};
   3016static const unsigned int msiof2_tx_b_mux[] = {
   3017	MSIOF2_TXD_B_MARK,
   3018};
   3019
   3020static const unsigned int msiof2_clk_c_pins[] = {
   3021	/* SCK */
   3022	RCAR_GP_PIN(2, 2),
   3023};
   3024static const unsigned int msiof2_clk_c_mux[] = {
   3025	MSIOF2_SCK_C_MARK,
   3026};
   3027static const unsigned int msiof2_sync_c_pins[] = {
   3028	/* SYNC */
   3029	RCAR_GP_PIN(2, 3),
   3030};
   3031static const unsigned int msiof2_sync_c_mux[] = {
   3032	MSIOF2_SYNC_C_MARK,
   3033};
   3034static const unsigned int msiof2_rx_c_pins[] = {
   3035	/* RXD */
   3036	RCAR_GP_PIN(2, 5),
   3037};
   3038static const unsigned int msiof2_rx_c_mux[] = {
   3039	MSIOF2_RXD_C_MARK,
   3040};
   3041static const unsigned int msiof2_tx_c_pins[] = {
   3042	/* TXD */
   3043	RCAR_GP_PIN(2, 4),
   3044};
   3045static const unsigned int msiof2_tx_c_mux[] = {
   3046	MSIOF2_TXD_C_MARK,
   3047};
   3048
   3049static const unsigned int msiof2_clk_d_pins[] = {
   3050	/* SCK */
   3051	RCAR_GP_PIN(2, 14),
   3052};
   3053static const unsigned int msiof2_clk_d_mux[] = {
   3054	MSIOF2_SCK_D_MARK,
   3055};
   3056static const unsigned int msiof2_sync_d_pins[] = {
   3057	/* SYNC */
   3058	RCAR_GP_PIN(2, 15),
   3059};
   3060static const unsigned int msiof2_sync_d_mux[] = {
   3061	MSIOF2_SYNC_D_MARK,
   3062};
   3063static const unsigned int msiof2_ss1_d_pins[] = {
   3064	/* SS1 */
   3065	RCAR_GP_PIN(2, 17),
   3066};
   3067static const unsigned int msiof2_ss1_d_mux[] = {
   3068	MSIOF2_SS1_D_MARK,
   3069};
   3070static const unsigned int msiof2_ss2_d_pins[] = {
   3071	/* SS2 */
   3072	RCAR_GP_PIN(2, 19),
   3073};
   3074static const unsigned int msiof2_ss2_d_mux[] = {
   3075	MSIOF2_SS2_D_MARK,
   3076};
   3077static const unsigned int msiof2_rx_d_pins[] = {
   3078	/* RXD */
   3079	RCAR_GP_PIN(2, 18),
   3080};
   3081static const unsigned int msiof2_rx_d_mux[] = {
   3082	MSIOF2_RXD_D_MARK,
   3083};
   3084static const unsigned int msiof2_tx_d_pins[] = {
   3085	/* TXD */
   3086	RCAR_GP_PIN(2, 16),
   3087};
   3088static const unsigned int msiof2_tx_d_mux[] = {
   3089	MSIOF2_TXD_D_MARK,
   3090};
   3091
   3092static const unsigned int msiof2_clk_e_pins[] = {
   3093	/* SCK */
   3094	RCAR_GP_PIN(7, 15),
   3095};
   3096static const unsigned int msiof2_clk_e_mux[] = {
   3097	MSIOF2_SCK_E_MARK,
   3098};
   3099static const unsigned int msiof2_sync_e_pins[] = {
   3100	/* SYNC */
   3101	RCAR_GP_PIN(7, 16),
   3102};
   3103static const unsigned int msiof2_sync_e_mux[] = {
   3104	MSIOF2_SYNC_E_MARK,
   3105};
   3106static const unsigned int msiof2_rx_e_pins[] = {
   3107	/* RXD */
   3108	RCAR_GP_PIN(7, 14),
   3109};
   3110static const unsigned int msiof2_rx_e_mux[] = {
   3111	MSIOF2_RXD_E_MARK,
   3112};
   3113static const unsigned int msiof2_tx_e_pins[] = {
   3114	/* TXD */
   3115	RCAR_GP_PIN(7, 13),
   3116};
   3117static const unsigned int msiof2_tx_e_mux[] = {
   3118	MSIOF2_TXD_E_MARK,
   3119};
   3120/* - PWM -------------------------------------------------------------------- */
   3121static const unsigned int pwm0_pins[] = {
   3122	RCAR_GP_PIN(6, 14),
   3123};
   3124static const unsigned int pwm0_mux[] = {
   3125	PWM0_MARK,
   3126};
   3127static const unsigned int pwm0_b_pins[] = {
   3128	RCAR_GP_PIN(5, 30),
   3129};
   3130static const unsigned int pwm0_b_mux[] = {
   3131	PWM0_B_MARK,
   3132};
   3133static const unsigned int pwm1_pins[] = {
   3134	RCAR_GP_PIN(1, 17),
   3135};
   3136static const unsigned int pwm1_mux[] = {
   3137	PWM1_MARK,
   3138};
   3139static const unsigned int pwm1_b_pins[] = {
   3140	RCAR_GP_PIN(6, 15),
   3141};
   3142static const unsigned int pwm1_b_mux[] = {
   3143	PWM1_B_MARK,
   3144};
   3145static const unsigned int pwm2_pins[] = {
   3146	RCAR_GP_PIN(1, 18),
   3147};
   3148static const unsigned int pwm2_mux[] = {
   3149	PWM2_MARK,
   3150};
   3151static const unsigned int pwm2_b_pins[] = {
   3152	RCAR_GP_PIN(0, 16),
   3153};
   3154static const unsigned int pwm2_b_mux[] = {
   3155	PWM2_B_MARK,
   3156};
   3157static const unsigned int pwm3_pins[] = {
   3158	RCAR_GP_PIN(1, 24),
   3159};
   3160static const unsigned int pwm3_mux[] = {
   3161	PWM3_MARK,
   3162};
   3163static const unsigned int pwm4_pins[] = {
   3164	RCAR_GP_PIN(3, 26),
   3165};
   3166static const unsigned int pwm4_mux[] = {
   3167	PWM4_MARK,
   3168};
   3169static const unsigned int pwm4_b_pins[] = {
   3170	RCAR_GP_PIN(3, 31),
   3171};
   3172static const unsigned int pwm4_b_mux[] = {
   3173	PWM4_B_MARK,
   3174};
   3175static const unsigned int pwm5_pins[] = {
   3176	RCAR_GP_PIN(7, 21),
   3177};
   3178static const unsigned int pwm5_mux[] = {
   3179	PWM5_MARK,
   3180};
   3181static const unsigned int pwm5_b_pins[] = {
   3182	RCAR_GP_PIN(7, 20),
   3183};
   3184static const unsigned int pwm5_b_mux[] = {
   3185	PWM5_B_MARK,
   3186};
   3187static const unsigned int pwm6_pins[] = {
   3188	RCAR_GP_PIN(7, 22),
   3189};
   3190static const unsigned int pwm6_mux[] = {
   3191	PWM6_MARK,
   3192};
   3193/* - QSPI ------------------------------------------------------------------- */
   3194static const unsigned int qspi_ctrl_pins[] = {
   3195	/* SPCLK, SSL */
   3196	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
   3197};
   3198static const unsigned int qspi_ctrl_mux[] = {
   3199	SPCLK_MARK, SSL_MARK,
   3200};
   3201static const unsigned int qspi_data_pins[] = {
   3202	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
   3203	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
   3204	RCAR_GP_PIN(1, 8),
   3205};
   3206static const unsigned int qspi_data_mux[] = {
   3207	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
   3208};
   3209
   3210static const unsigned int qspi_ctrl_b_pins[] = {
   3211	/* SPCLK, SSL */
   3212	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
   3213};
   3214static const unsigned int qspi_ctrl_b_mux[] = {
   3215	SPCLK_B_MARK, SSL_B_MARK,
   3216};
   3217static const unsigned int qspi_data_b_pins[] = {
   3218	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
   3219	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
   3220	RCAR_GP_PIN(6, 4),
   3221};
   3222static const unsigned int qspi_data_b_mux[] = {
   3223	MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
   3224};
   3225/* - SCIF0 ------------------------------------------------------------------ */
   3226static const unsigned int scif0_data_pins[] = {
   3227	/* RX, TX */
   3228	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
   3229};
   3230static const unsigned int scif0_data_mux[] = {
   3231	RX0_MARK, TX0_MARK,
   3232};
   3233static const unsigned int scif0_data_b_pins[] = {
   3234	/* RX, TX */
   3235	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
   3236};
   3237static const unsigned int scif0_data_b_mux[] = {
   3238	RX0_B_MARK, TX0_B_MARK,
   3239};
   3240static const unsigned int scif0_data_c_pins[] = {
   3241	/* RX, TX */
   3242	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
   3243};
   3244static const unsigned int scif0_data_c_mux[] = {
   3245	RX0_C_MARK, TX0_C_MARK,
   3246};
   3247static const unsigned int scif0_data_d_pins[] = {
   3248	/* RX, TX */
   3249	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
   3250};
   3251static const unsigned int scif0_data_d_mux[] = {
   3252	RX0_D_MARK, TX0_D_MARK,
   3253};
   3254static const unsigned int scif0_data_e_pins[] = {
   3255	/* RX, TX */
   3256	RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
   3257};
   3258static const unsigned int scif0_data_e_mux[] = {
   3259	RX0_E_MARK, TX0_E_MARK,
   3260};
   3261/* - SCIF1 ------------------------------------------------------------------ */
   3262static const unsigned int scif1_data_pins[] = {
   3263	/* RX, TX */
   3264	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
   3265};
   3266static const unsigned int scif1_data_mux[] = {
   3267	RX1_MARK, TX1_MARK,
   3268};
   3269static const unsigned int scif1_data_b_pins[] = {
   3270	/* RX, TX */
   3271	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
   3272};
   3273static const unsigned int scif1_data_b_mux[] = {
   3274	RX1_B_MARK, TX1_B_MARK,
   3275};
   3276static const unsigned int scif1_clk_b_pins[] = {
   3277	/* SCK */
   3278	RCAR_GP_PIN(3, 10),
   3279};
   3280static const unsigned int scif1_clk_b_mux[] = {
   3281	SCIF1_SCK_B_MARK,
   3282};
   3283static const unsigned int scif1_data_c_pins[] = {
   3284	/* RX, TX */
   3285	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
   3286};
   3287static const unsigned int scif1_data_c_mux[] = {
   3288	RX1_C_MARK, TX1_C_MARK,
   3289};
   3290static const unsigned int scif1_data_d_pins[] = {
   3291	/* RX, TX */
   3292	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
   3293};
   3294static const unsigned int scif1_data_d_mux[] = {
   3295	RX1_D_MARK, TX1_D_MARK,
   3296};
   3297/* - SCIF2 ------------------------------------------------------------------ */
   3298static const unsigned int scif2_data_pins[] = {
   3299	/* RX, TX */
   3300	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
   3301};
   3302static const unsigned int scif2_data_mux[] = {
   3303	RX2_MARK, TX2_MARK,
   3304};
   3305static const unsigned int scif2_data_b_pins[] = {
   3306	/* RX, TX */
   3307	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
   3308};
   3309static const unsigned int scif2_data_b_mux[] = {
   3310	RX2_B_MARK, TX2_B_MARK,
   3311};
   3312static const unsigned int scif2_clk_b_pins[] = {
   3313	/* SCK */
   3314	RCAR_GP_PIN(3, 18),
   3315};
   3316static const unsigned int scif2_clk_b_mux[] = {
   3317	SCIF2_SCK_B_MARK,
   3318};
   3319static const unsigned int scif2_data_c_pins[] = {
   3320	/* RX, TX */
   3321	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
   3322};
   3323static const unsigned int scif2_data_c_mux[] = {
   3324	RX2_C_MARK, TX2_C_MARK,
   3325};
   3326static const unsigned int scif2_data_e_pins[] = {
   3327	/* RX, TX */
   3328	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
   3329};
   3330static const unsigned int scif2_data_e_mux[] = {
   3331	RX2_E_MARK, TX2_E_MARK,
   3332};
   3333/* - SCIF3 ------------------------------------------------------------------ */
   3334static const unsigned int scif3_data_pins[] = {
   3335	/* RX, TX */
   3336	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
   3337};
   3338static const unsigned int scif3_data_mux[] = {
   3339	RX3_MARK, TX3_MARK,
   3340};
   3341static const unsigned int scif3_clk_pins[] = {
   3342	/* SCK */
   3343	RCAR_GP_PIN(3, 23),
   3344};
   3345static const unsigned int scif3_clk_mux[] = {
   3346	SCIF3_SCK_MARK,
   3347};
   3348static const unsigned int scif3_data_b_pins[] = {
   3349	/* RX, TX */
   3350	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
   3351};
   3352static const unsigned int scif3_data_b_mux[] = {
   3353	RX3_B_MARK, TX3_B_MARK,
   3354};
   3355static const unsigned int scif3_clk_b_pins[] = {
   3356	/* SCK */
   3357	RCAR_GP_PIN(4, 8),
   3358};
   3359static const unsigned int scif3_clk_b_mux[] = {
   3360	SCIF3_SCK_B_MARK,
   3361};
   3362static const unsigned int scif3_data_c_pins[] = {
   3363	/* RX, TX */
   3364	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
   3365};
   3366static const unsigned int scif3_data_c_mux[] = {
   3367	RX3_C_MARK, TX3_C_MARK,
   3368};
   3369static const unsigned int scif3_data_d_pins[] = {
   3370	/* RX, TX */
   3371	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
   3372};
   3373static const unsigned int scif3_data_d_mux[] = {
   3374	RX3_D_MARK, TX3_D_MARK,
   3375};
   3376/* - SCIF4 ------------------------------------------------------------------ */
   3377static const unsigned int scif4_data_pins[] = {
   3378	/* RX, TX */
   3379	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
   3380};
   3381static const unsigned int scif4_data_mux[] = {
   3382	RX4_MARK, TX4_MARK,
   3383};
   3384static const unsigned int scif4_data_b_pins[] = {
   3385	/* RX, TX */
   3386	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
   3387};
   3388static const unsigned int scif4_data_b_mux[] = {
   3389	RX4_B_MARK, TX4_B_MARK,
   3390};
   3391static const unsigned int scif4_data_c_pins[] = {
   3392	/* RX, TX */
   3393	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
   3394};
   3395static const unsigned int scif4_data_c_mux[] = {
   3396	RX4_C_MARK, TX4_C_MARK,
   3397};
   3398/* - SCIF5 ------------------------------------------------------------------ */
   3399static const unsigned int scif5_data_pins[] = {
   3400	/* RX, TX */
   3401	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
   3402};
   3403static const unsigned int scif5_data_mux[] = {
   3404	RX5_MARK, TX5_MARK,
   3405};
   3406static const unsigned int scif5_data_b_pins[] = {
   3407	/* RX, TX */
   3408	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
   3409};
   3410static const unsigned int scif5_data_b_mux[] = {
   3411	RX5_B_MARK, TX5_B_MARK,
   3412};
   3413/* - SCIFA0 ----------------------------------------------------------------- */
   3414static const unsigned int scifa0_data_pins[] = {
   3415	/* RXD, TXD */
   3416	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
   3417};
   3418static const unsigned int scifa0_data_mux[] = {
   3419	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
   3420};
   3421static const unsigned int scifa0_data_b_pins[] = {
   3422	/* RXD, TXD */
   3423	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
   3424};
   3425static const unsigned int scifa0_data_b_mux[] = {
   3426	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
   3427};
   3428/* - SCIFA1 ----------------------------------------------------------------- */
   3429static const unsigned int scifa1_data_pins[] = {
   3430	/* RXD, TXD */
   3431	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
   3432};
   3433static const unsigned int scifa1_data_mux[] = {
   3434	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
   3435};
   3436static const unsigned int scifa1_clk_pins[] = {
   3437	/* SCK */
   3438	RCAR_GP_PIN(3, 10),
   3439};
   3440static const unsigned int scifa1_clk_mux[] = {
   3441	SCIFA1_SCK_MARK,
   3442};
   3443static const unsigned int scifa1_data_b_pins[] = {
   3444	/* RXD, TXD */
   3445	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
   3446};
   3447static const unsigned int scifa1_data_b_mux[] = {
   3448	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
   3449};
   3450static const unsigned int scifa1_clk_b_pins[] = {
   3451	/* SCK */
   3452	RCAR_GP_PIN(1, 0),
   3453};
   3454static const unsigned int scifa1_clk_b_mux[] = {
   3455	SCIFA1_SCK_B_MARK,
   3456};
   3457static const unsigned int scifa1_data_c_pins[] = {
   3458	/* RXD, TXD */
   3459	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
   3460};
   3461static const unsigned int scifa1_data_c_mux[] = {
   3462	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
   3463};
   3464/* - SCIFA2 ----------------------------------------------------------------- */
   3465static const unsigned int scifa2_data_pins[] = {
   3466	/* RXD, TXD */
   3467	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
   3468};
   3469static const unsigned int scifa2_data_mux[] = {
   3470	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
   3471};
   3472static const unsigned int scifa2_clk_pins[] = {
   3473	/* SCK */
   3474	RCAR_GP_PIN(3, 18),
   3475};
   3476static const unsigned int scifa2_clk_mux[] = {
   3477	SCIFA2_SCK_MARK,
   3478};
   3479static const unsigned int scifa2_data_b_pins[] = {
   3480	/* RXD, TXD */
   3481	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
   3482};
   3483static const unsigned int scifa2_data_b_mux[] = {
   3484	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
   3485};
   3486/* - SCIFA3 ----------------------------------------------------------------- */
   3487static const unsigned int scifa3_data_pins[] = {
   3488	/* RXD, TXD */
   3489	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
   3490};
   3491static const unsigned int scifa3_data_mux[] = {
   3492	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
   3493};
   3494static const unsigned int scifa3_clk_pins[] = {
   3495	/* SCK */
   3496	RCAR_GP_PIN(3, 23),
   3497};
   3498static const unsigned int scifa3_clk_mux[] = {
   3499	SCIFA3_SCK_MARK,
   3500};
   3501static const unsigned int scifa3_data_b_pins[] = {
   3502	/* RXD, TXD */
   3503	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
   3504};
   3505static const unsigned int scifa3_data_b_mux[] = {
   3506	SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
   3507};
   3508static const unsigned int scifa3_clk_b_pins[] = {
   3509	/* SCK */
   3510	RCAR_GP_PIN(4, 8),
   3511};
   3512static const unsigned int scifa3_clk_b_mux[] = {
   3513	SCIFA3_SCK_B_MARK,
   3514};
   3515static const unsigned int scifa3_data_c_pins[] = {
   3516	/* RXD, TXD */
   3517	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
   3518};
   3519static const unsigned int scifa3_data_c_mux[] = {
   3520	SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
   3521};
   3522static const unsigned int scifa3_clk_c_pins[] = {
   3523	/* SCK */
   3524	RCAR_GP_PIN(7, 22),
   3525};
   3526static const unsigned int scifa3_clk_c_mux[] = {
   3527	SCIFA3_SCK_C_MARK,
   3528};
   3529/* - SCIFA4 ----------------------------------------------------------------- */
   3530static const unsigned int scifa4_data_pins[] = {
   3531	/* RXD, TXD */
   3532	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
   3533};
   3534static const unsigned int scifa4_data_mux[] = {
   3535	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
   3536};
   3537static const unsigned int scifa4_data_b_pins[] = {
   3538	/* RXD, TXD */
   3539	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
   3540};
   3541static const unsigned int scifa4_data_b_mux[] = {
   3542	SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
   3543};
   3544static const unsigned int scifa4_data_c_pins[] = {
   3545	/* RXD, TXD */
   3546	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
   3547};
   3548static const unsigned int scifa4_data_c_mux[] = {
   3549	SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
   3550};
   3551/* - SCIFA5 ----------------------------------------------------------------- */
   3552static const unsigned int scifa5_data_pins[] = {
   3553	/* RXD, TXD */
   3554	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
   3555};
   3556static const unsigned int scifa5_data_mux[] = {
   3557	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
   3558};
   3559static const unsigned int scifa5_data_b_pins[] = {
   3560	/* RXD, TXD */
   3561	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
   3562};
   3563static const unsigned int scifa5_data_b_mux[] = {
   3564	SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
   3565};
   3566static const unsigned int scifa5_data_c_pins[] = {
   3567	/* RXD, TXD */
   3568	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
   3569};
   3570static const unsigned int scifa5_data_c_mux[] = {
   3571	SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
   3572};
   3573/* - SCIFB0 ----------------------------------------------------------------- */
   3574static const unsigned int scifb0_data_pins[] = {
   3575	/* RXD, TXD */
   3576	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
   3577};
   3578static const unsigned int scifb0_data_mux[] = {
   3579	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
   3580};
   3581static const unsigned int scifb0_clk_pins[] = {
   3582	/* SCK */
   3583	RCAR_GP_PIN(7, 2),
   3584};
   3585static const unsigned int scifb0_clk_mux[] = {
   3586	SCIFB0_SCK_MARK,
   3587};
   3588static const unsigned int scifb0_ctrl_pins[] = {
   3589	/* RTS, CTS */
   3590	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
   3591};
   3592static const unsigned int scifb0_ctrl_mux[] = {
   3593	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
   3594};
   3595static const unsigned int scifb0_data_b_pins[] = {
   3596	/* RXD, TXD */
   3597	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
   3598};
   3599static const unsigned int scifb0_data_b_mux[] = {
   3600	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
   3601};
   3602static const unsigned int scifb0_clk_b_pins[] = {
   3603	/* SCK */
   3604	RCAR_GP_PIN(5, 31),
   3605};
   3606static const unsigned int scifb0_clk_b_mux[] = {
   3607	SCIFB0_SCK_B_MARK,
   3608};
   3609static const unsigned int scifb0_ctrl_b_pins[] = {
   3610	/* RTS, CTS */
   3611	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
   3612};
   3613static const unsigned int scifb0_ctrl_b_mux[] = {
   3614	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
   3615};
   3616static const unsigned int scifb0_data_c_pins[] = {
   3617	/* RXD, TXD */
   3618	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
   3619};
   3620static const unsigned int scifb0_data_c_mux[] = {
   3621	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
   3622};
   3623static const unsigned int scifb0_clk_c_pins[] = {
   3624	/* SCK */
   3625	RCAR_GP_PIN(2, 30),
   3626};
   3627static const unsigned int scifb0_clk_c_mux[] = {
   3628	SCIFB0_SCK_C_MARK,
   3629};
   3630static const unsigned int scifb0_data_d_pins[] = {
   3631	/* RXD, TXD */
   3632	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
   3633};
   3634static const unsigned int scifb0_data_d_mux[] = {
   3635	SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
   3636};
   3637static const unsigned int scifb0_clk_d_pins[] = {
   3638	/* SCK */
   3639	RCAR_GP_PIN(4, 17),
   3640};
   3641static const unsigned int scifb0_clk_d_mux[] = {
   3642	SCIFB0_SCK_D_MARK,
   3643};
   3644/* - SCIFB1 ----------------------------------------------------------------- */
   3645static const unsigned int scifb1_data_pins[] = {
   3646	/* RXD, TXD */
   3647	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
   3648};
   3649static const unsigned int scifb1_data_mux[] = {
   3650	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
   3651};
   3652static const unsigned int scifb1_clk_pins[] = {
   3653	/* SCK */
   3654	RCAR_GP_PIN(7, 7),
   3655};
   3656static const unsigned int scifb1_clk_mux[] = {
   3657	SCIFB1_SCK_MARK,
   3658};
   3659static const unsigned int scifb1_ctrl_pins[] = {
   3660	/* RTS, CTS */
   3661	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
   3662};
   3663static const unsigned int scifb1_ctrl_mux[] = {
   3664	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
   3665};
   3666static const unsigned int scifb1_data_b_pins[] = {
   3667	/* RXD, TXD */
   3668	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
   3669};
   3670static const unsigned int scifb1_data_b_mux[] = {
   3671	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
   3672};
   3673static const unsigned int scifb1_clk_b_pins[] = {
   3674	/* SCK */
   3675	RCAR_GP_PIN(1, 3),
   3676};
   3677static const unsigned int scifb1_clk_b_mux[] = {
   3678	SCIFB1_SCK_B_MARK,
   3679};
   3680static const unsigned int scifb1_data_c_pins[] = {
   3681	/* RXD, TXD */
   3682	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
   3683};
   3684static const unsigned int scifb1_data_c_mux[] = {
   3685	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
   3686};
   3687static const unsigned int scifb1_clk_c_pins[] = {
   3688	/* SCK */
   3689	RCAR_GP_PIN(7, 11),
   3690};
   3691static const unsigned int scifb1_clk_c_mux[] = {
   3692	SCIFB1_SCK_C_MARK,
   3693};
   3694static const unsigned int scifb1_data_d_pins[] = {
   3695	/* RXD, TXD */
   3696	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
   3697};
   3698static const unsigned int scifb1_data_d_mux[] = {
   3699	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
   3700};
   3701/* - SCIFB2 ----------------------------------------------------------------- */
   3702static const unsigned int scifb2_data_pins[] = {
   3703	/* RXD, TXD */
   3704	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
   3705};
   3706static const unsigned int scifb2_data_mux[] = {
   3707	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
   3708};
   3709static const unsigned int scifb2_clk_pins[] = {
   3710	/* SCK */
   3711	RCAR_GP_PIN(4, 15),
   3712};
   3713static const unsigned int scifb2_clk_mux[] = {
   3714	SCIFB2_SCK_MARK,
   3715};
   3716static const unsigned int scifb2_ctrl_pins[] = {
   3717	/* RTS, CTS */
   3718	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
   3719};
   3720static const unsigned int scifb2_ctrl_mux[] = {
   3721	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
   3722};
   3723static const unsigned int scifb2_data_b_pins[] = {
   3724	/* RXD, TXD */
   3725	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
   3726};
   3727static const unsigned int scifb2_data_b_mux[] = {
   3728	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
   3729};
   3730static const unsigned int scifb2_clk_b_pins[] = {
   3731	/* SCK */
   3732	RCAR_GP_PIN(5, 31),
   3733};
   3734static const unsigned int scifb2_clk_b_mux[] = {
   3735	SCIFB2_SCK_B_MARK,
   3736};
   3737static const unsigned int scifb2_ctrl_b_pins[] = {
   3738	/* RTS, CTS */
   3739	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
   3740};
   3741static const unsigned int scifb2_ctrl_b_mux[] = {
   3742	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
   3743};
   3744static const unsigned int scifb2_data_c_pins[] = {
   3745	/* RXD, TXD */
   3746	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
   3747};
   3748static const unsigned int scifb2_data_c_mux[] = {
   3749	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
   3750};
   3751static const unsigned int scifb2_clk_c_pins[] = {
   3752	/* SCK */
   3753	RCAR_GP_PIN(5, 27),
   3754};
   3755static const unsigned int scifb2_clk_c_mux[] = {
   3756	SCIFB2_SCK_C_MARK,
   3757};
   3758static const unsigned int scifb2_data_d_pins[] = {
   3759	/* RXD, TXD */
   3760	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
   3761};
   3762static const unsigned int scifb2_data_d_mux[] = {
   3763	SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
   3764};
   3765
   3766/* - SCIF Clock ------------------------------------------------------------- */
   3767static const unsigned int scif_clk_pins[] = {
   3768	/* SCIF_CLK */
   3769	RCAR_GP_PIN(2, 29),
   3770};
   3771static const unsigned int scif_clk_mux[] = {
   3772	SCIF_CLK_MARK,
   3773};
   3774static const unsigned int scif_clk_b_pins[] = {
   3775	/* SCIF_CLK */
   3776	RCAR_GP_PIN(7, 19),
   3777};
   3778static const unsigned int scif_clk_b_mux[] = {
   3779	SCIF_CLK_B_MARK,
   3780};
   3781
   3782/* - SDHI0 ------------------------------------------------------------------ */
   3783static const unsigned int sdhi0_data_pins[] = {
   3784	/* D[0:3] */
   3785	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
   3786	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
   3787};
   3788static const unsigned int sdhi0_data_mux[] = {
   3789	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
   3790};
   3791static const unsigned int sdhi0_ctrl_pins[] = {
   3792	/* CLK, CMD */
   3793	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
   3794};
   3795static const unsigned int sdhi0_ctrl_mux[] = {
   3796	SD0_CLK_MARK, SD0_CMD_MARK,
   3797};
   3798static const unsigned int sdhi0_cd_pins[] = {
   3799	/* CD */
   3800	RCAR_GP_PIN(6, 6),
   3801};
   3802static const unsigned int sdhi0_cd_mux[] = {
   3803	SD0_CD_MARK,
   3804};
   3805static const unsigned int sdhi0_wp_pins[] = {
   3806	/* WP */
   3807	RCAR_GP_PIN(6, 7),
   3808};
   3809static const unsigned int sdhi0_wp_mux[] = {
   3810	SD0_WP_MARK,
   3811};
   3812/* - SDHI1 ------------------------------------------------------------------ */
   3813static const unsigned int sdhi1_data_pins[] = {
   3814	/* D[0:3] */
   3815	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
   3816	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
   3817};
   3818static const unsigned int sdhi1_data_mux[] = {
   3819	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
   3820};
   3821static const unsigned int sdhi1_ctrl_pins[] = {
   3822	/* CLK, CMD */
   3823	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
   3824};
   3825static const unsigned int sdhi1_ctrl_mux[] = {
   3826	SD1_CLK_MARK, SD1_CMD_MARK,
   3827};
   3828static const unsigned int sdhi1_cd_pins[] = {
   3829	/* CD */
   3830	RCAR_GP_PIN(6, 14),
   3831};
   3832static const unsigned int sdhi1_cd_mux[] = {
   3833	SD1_CD_MARK,
   3834};
   3835static const unsigned int sdhi1_wp_pins[] = {
   3836	/* WP */
   3837	RCAR_GP_PIN(6, 15),
   3838};
   3839static const unsigned int sdhi1_wp_mux[] = {
   3840	SD1_WP_MARK,
   3841};
   3842/* - SDHI2 ------------------------------------------------------------------ */
   3843static const unsigned int sdhi2_data_pins[] = {
   3844	/* D[0:3] */
   3845	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
   3846	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
   3847};
   3848static const unsigned int sdhi2_data_mux[] = {
   3849	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
   3850};
   3851static const unsigned int sdhi2_ctrl_pins[] = {
   3852	/* CLK, CMD */
   3853	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
   3854};
   3855static const unsigned int sdhi2_ctrl_mux[] = {
   3856	SD2_CLK_MARK, SD2_CMD_MARK,
   3857};
   3858static const unsigned int sdhi2_cd_pins[] = {
   3859	/* CD */
   3860	RCAR_GP_PIN(6, 22),
   3861};
   3862static const unsigned int sdhi2_cd_mux[] = {
   3863	SD2_CD_MARK,
   3864};
   3865static const unsigned int sdhi2_wp_pins[] = {
   3866	/* WP */
   3867	RCAR_GP_PIN(6, 23),
   3868};
   3869static const unsigned int sdhi2_wp_mux[] = {
   3870	SD2_WP_MARK,
   3871};
   3872
   3873/* - SSI -------------------------------------------------------------------- */
   3874static const unsigned int ssi0_data_pins[] = {
   3875	/* SDATA */
   3876	RCAR_GP_PIN(2, 2),
   3877};
   3878
   3879static const unsigned int ssi0_data_mux[] = {
   3880	SSI_SDATA0_MARK,
   3881};
   3882
   3883static const unsigned int ssi0_data_b_pins[] = {
   3884	/* SDATA */
   3885	RCAR_GP_PIN(3, 4),
   3886};
   3887
   3888static const unsigned int ssi0_data_b_mux[] = {
   3889	SSI_SDATA0_B_MARK,
   3890};
   3891
   3892static const unsigned int ssi0129_ctrl_pins[] = {
   3893	/* SCK, WS */
   3894	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
   3895};
   3896
   3897static const unsigned int ssi0129_ctrl_mux[] = {
   3898	SSI_SCK0129_MARK, SSI_WS0129_MARK,
   3899};
   3900
   3901static const unsigned int ssi0129_ctrl_b_pins[] = {
   3902	/* SCK, WS */
   3903	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
   3904};
   3905
   3906static const unsigned int ssi0129_ctrl_b_mux[] = {
   3907	SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
   3908};
   3909
   3910static const unsigned int ssi1_data_pins[] = {
   3911	/* SDATA */
   3912	RCAR_GP_PIN(2, 5),
   3913};
   3914
   3915static const unsigned int ssi1_data_mux[] = {
   3916	SSI_SDATA1_MARK,
   3917};
   3918
   3919static const unsigned int ssi1_data_b_pins[] = {
   3920	/* SDATA */
   3921	RCAR_GP_PIN(3, 7),
   3922};
   3923
   3924static const unsigned int ssi1_data_b_mux[] = {
   3925	SSI_SDATA1_B_MARK,
   3926};
   3927
   3928static const unsigned int ssi1_ctrl_pins[] = {
   3929	/* SCK, WS */
   3930	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
   3931};
   3932
   3933static const unsigned int ssi1_ctrl_mux[] = {
   3934	SSI_SCK1_MARK, SSI_WS1_MARK,
   3935};
   3936
   3937static const unsigned int ssi1_ctrl_b_pins[] = {
   3938	/* SCK, WS */
   3939	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
   3940};
   3941
   3942static const unsigned int ssi1_ctrl_b_mux[] = {
   3943	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
   3944};
   3945
   3946static const unsigned int ssi2_data_pins[] = {
   3947	/* SDATA */
   3948	RCAR_GP_PIN(2, 8),
   3949};
   3950
   3951static const unsigned int ssi2_data_mux[] = {
   3952	SSI_SDATA2_MARK,
   3953};
   3954
   3955static const unsigned int ssi2_ctrl_pins[] = {
   3956	/* SCK, WS */
   3957	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
   3958};
   3959
   3960static const unsigned int ssi2_ctrl_mux[] = {
   3961	SSI_SCK2_MARK, SSI_WS2_MARK,
   3962};
   3963
   3964static const unsigned int ssi3_data_pins[] = {
   3965	/* SDATA */
   3966	RCAR_GP_PIN(2, 11),
   3967};
   3968
   3969static const unsigned int ssi3_data_mux[] = {
   3970	SSI_SDATA3_MARK,
   3971};
   3972
   3973static const unsigned int ssi34_ctrl_pins[] = {
   3974	/* SCK, WS */
   3975	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
   3976};
   3977
   3978static const unsigned int ssi34_ctrl_mux[] = {
   3979	SSI_SCK34_MARK, SSI_WS34_MARK,
   3980};
   3981
   3982static const unsigned int ssi4_data_pins[] = {
   3983	/* SDATA */
   3984	RCAR_GP_PIN(2, 14),
   3985};
   3986
   3987static const unsigned int ssi4_data_mux[] = {
   3988	SSI_SDATA4_MARK,
   3989};
   3990
   3991static const unsigned int ssi4_ctrl_pins[] = {
   3992	/* SCK, WS */
   3993	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
   3994};
   3995
   3996static const unsigned int ssi4_ctrl_mux[] = {
   3997	SSI_SCK4_MARK, SSI_WS4_MARK,
   3998};
   3999
   4000static const unsigned int ssi5_data_pins[] = {
   4001	/* SDATA */
   4002	RCAR_GP_PIN(2, 17),
   4003};
   4004
   4005static const unsigned int ssi5_data_mux[] = {
   4006	SSI_SDATA5_MARK,
   4007};
   4008
   4009static const unsigned int ssi5_ctrl_pins[] = {
   4010	/* SCK, WS */
   4011	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
   4012};
   4013
   4014static const unsigned int ssi5_ctrl_mux[] = {
   4015	SSI_SCK5_MARK, SSI_WS5_MARK,
   4016};
   4017
   4018static const unsigned int ssi6_data_pins[] = {
   4019	/* SDATA */
   4020	RCAR_GP_PIN(2, 20),
   4021};
   4022
   4023static const unsigned int ssi6_data_mux[] = {
   4024	SSI_SDATA6_MARK,
   4025};
   4026
   4027static const unsigned int ssi6_ctrl_pins[] = {
   4028	/* SCK, WS */
   4029	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
   4030};
   4031
   4032static const unsigned int ssi6_ctrl_mux[] = {
   4033	SSI_SCK6_MARK, SSI_WS6_MARK,
   4034};
   4035
   4036static const unsigned int ssi7_data_pins[] = {
   4037	/* SDATA */
   4038	RCAR_GP_PIN(2, 23),
   4039};
   4040
   4041static const unsigned int ssi7_data_mux[] = {
   4042	SSI_SDATA7_MARK,
   4043};
   4044
   4045static const unsigned int ssi7_data_b_pins[] = {
   4046	/* SDATA */
   4047	RCAR_GP_PIN(3, 12),
   4048};
   4049
   4050static const unsigned int ssi7_data_b_mux[] = {
   4051	SSI_SDATA7_B_MARK,
   4052};
   4053
   4054static const unsigned int ssi78_ctrl_pins[] = {
   4055	/* SCK, WS */
   4056	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
   4057};
   4058
   4059static const unsigned int ssi78_ctrl_mux[] = {
   4060	SSI_SCK78_MARK, SSI_WS78_MARK,
   4061};
   4062
   4063static const unsigned int ssi78_ctrl_b_pins[] = {
   4064	/* SCK, WS */
   4065	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
   4066};
   4067
   4068static const unsigned int ssi78_ctrl_b_mux[] = {
   4069	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
   4070};
   4071
   4072static const unsigned int ssi8_data_pins[] = {
   4073	/* SDATA */
   4074	RCAR_GP_PIN(2, 24),
   4075};
   4076
   4077static const unsigned int ssi8_data_mux[] = {
   4078	SSI_SDATA8_MARK,
   4079};
   4080
   4081static const unsigned int ssi8_data_b_pins[] = {
   4082	/* SDATA */
   4083	RCAR_GP_PIN(3, 13),
   4084};
   4085
   4086static const unsigned int ssi8_data_b_mux[] = {
   4087	SSI_SDATA8_B_MARK,
   4088};
   4089
   4090static const unsigned int ssi9_data_pins[] = {
   4091	/* SDATA */
   4092	RCAR_GP_PIN(2, 27),
   4093};
   4094
   4095static const unsigned int ssi9_data_mux[] = {
   4096	SSI_SDATA9_MARK,
   4097};
   4098
   4099static const unsigned int ssi9_data_b_pins[] = {
   4100	/* SDATA */
   4101	RCAR_GP_PIN(3, 18),
   4102};
   4103
   4104static const unsigned int ssi9_data_b_mux[] = {
   4105	SSI_SDATA9_B_MARK,
   4106};
   4107
   4108static const unsigned int ssi9_ctrl_pins[] = {
   4109	/* SCK, WS */
   4110	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
   4111};
   4112
   4113static const unsigned int ssi9_ctrl_mux[] = {
   4114	SSI_SCK9_MARK, SSI_WS9_MARK,
   4115};
   4116
   4117static const unsigned int ssi9_ctrl_b_pins[] = {
   4118	/* SCK, WS */
   4119	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
   4120};
   4121
   4122static const unsigned int ssi9_ctrl_b_mux[] = {
   4123	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
   4124};
   4125
   4126/* - TPU -------------------------------------------------------------------- */
   4127static const unsigned int tpu_to0_pins[] = {
   4128	RCAR_GP_PIN(6, 14),
   4129};
   4130static const unsigned int tpu_to0_mux[] = {
   4131	TPU_TO0_MARK,
   4132};
   4133static const unsigned int tpu_to1_pins[] = {
   4134	RCAR_GP_PIN(1, 17),
   4135};
   4136static const unsigned int tpu_to1_mux[] = {
   4137	TPU_TO1_MARK,
   4138};
   4139static const unsigned int tpu_to2_pins[] = {
   4140	RCAR_GP_PIN(1, 18),
   4141};
   4142static const unsigned int tpu_to2_mux[] = {
   4143	TPU_TO2_MARK,
   4144};
   4145static const unsigned int tpu_to3_pins[] = {
   4146	RCAR_GP_PIN(1, 24),
   4147};
   4148static const unsigned int tpu_to3_mux[] = {
   4149	TPU_TO3_MARK,
   4150};
   4151
   4152/* - USB0 ------------------------------------------------------------------- */
   4153static const unsigned int usb0_pins[] = {
   4154	RCAR_GP_PIN(7, 23), /* PWEN */
   4155	RCAR_GP_PIN(7, 24), /* OVC */
   4156};
   4157static const unsigned int usb0_mux[] = {
   4158	USB0_PWEN_MARK,
   4159	USB0_OVC_MARK,
   4160};
   4161/* - USB1 ------------------------------------------------------------------- */
   4162static const unsigned int usb1_pins[] = {
   4163	RCAR_GP_PIN(7, 25), /* PWEN */
   4164	RCAR_GP_PIN(6, 30), /* OVC */
   4165};
   4166static const unsigned int usb1_mux[] = {
   4167	USB1_PWEN_MARK,
   4168	USB1_OVC_MARK,
   4169};
   4170/* - VIN0 ------------------------------------------------------------------- */
   4171static const unsigned int vin0_data_pins[] = {
   4172	/* B */
   4173	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
   4174	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
   4175	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
   4176	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
   4177	/* G */
   4178	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
   4179	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
   4180	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
   4181	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
   4182	/* R */
   4183	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
   4184	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
   4185	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
   4186	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
   4187};
   4188static const unsigned int vin0_data_mux[] = {
   4189	/* B */
   4190	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
   4191	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
   4192	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
   4193	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
   4194	/* G */
   4195	VI0_G0_MARK, VI0_G1_MARK,
   4196	VI0_G2_MARK, VI0_G3_MARK,
   4197	VI0_G4_MARK, VI0_G5_MARK,
   4198	VI0_G6_MARK, VI0_G7_MARK,
   4199	/* R */
   4200	VI0_R0_MARK, VI0_R1_MARK,
   4201	VI0_R2_MARK, VI0_R3_MARK,
   4202	VI0_R4_MARK, VI0_R5_MARK,
   4203	VI0_R6_MARK, VI0_R7_MARK,
   4204};
   4205static const unsigned int vin0_data18_pins[] = {
   4206	/* B */
   4207	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
   4208	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
   4209	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
   4210	/* G */
   4211	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
   4212	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
   4213	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
   4214	/* R */
   4215	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
   4216	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
   4217	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
   4218};
   4219static const unsigned int vin0_data18_mux[] = {
   4220	/* B */
   4221	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
   4222	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
   4223	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
   4224	/* G */
   4225	VI0_G2_MARK, VI0_G3_MARK,
   4226	VI0_G4_MARK, VI0_G5_MARK,
   4227	VI0_G6_MARK, VI0_G7_MARK,
   4228	/* R */
   4229	VI0_R2_MARK, VI0_R3_MARK,
   4230	VI0_R4_MARK, VI0_R5_MARK,
   4231	VI0_R6_MARK, VI0_R7_MARK,
   4232};
   4233static const unsigned int vin0_sync_pins[] = {
   4234	RCAR_GP_PIN(4, 3), /* HSYNC */
   4235	RCAR_GP_PIN(4, 4), /* VSYNC */
   4236};
   4237static const unsigned int vin0_sync_mux[] = {
   4238	VI0_HSYNC_N_MARK,
   4239	VI0_VSYNC_N_MARK,
   4240};
   4241static const unsigned int vin0_field_pins[] = {
   4242	RCAR_GP_PIN(4, 2),
   4243};
   4244static const unsigned int vin0_field_mux[] = {
   4245	VI0_FIELD_MARK,
   4246};
   4247static const unsigned int vin0_clkenb_pins[] = {
   4248	RCAR_GP_PIN(4, 1),
   4249};
   4250static const unsigned int vin0_clkenb_mux[] = {
   4251	VI0_CLKENB_MARK,
   4252};
   4253static const unsigned int vin0_clk_pins[] = {
   4254	RCAR_GP_PIN(4, 0),
   4255};
   4256static const unsigned int vin0_clk_mux[] = {
   4257	VI0_CLK_MARK,
   4258};
   4259/* - VIN1 ----------------------------------------------------------------- */
   4260static const unsigned int vin1_data8_pins[] = {
   4261	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
   4262	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
   4263	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
   4264	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
   4265};
   4266static const unsigned int vin1_data8_mux[] = {
   4267	VI1_DATA0_MARK, VI1_DATA1_MARK,
   4268	VI1_DATA2_MARK, VI1_DATA3_MARK,
   4269	VI1_DATA4_MARK, VI1_DATA5_MARK,
   4270	VI1_DATA6_MARK, VI1_DATA7_MARK,
   4271};
   4272static const unsigned int vin1_sync_pins[] = {
   4273	RCAR_GP_PIN(5, 0), /* HSYNC */
   4274	RCAR_GP_PIN(5, 1), /* VSYNC */
   4275};
   4276static const unsigned int vin1_sync_mux[] = {
   4277	VI1_HSYNC_N_MARK,
   4278	VI1_VSYNC_N_MARK,
   4279};
   4280static const unsigned int vin1_field_pins[] = {
   4281	RCAR_GP_PIN(5, 3),
   4282};
   4283static const unsigned int vin1_field_mux[] = {
   4284	VI1_FIELD_MARK,
   4285};
   4286static const unsigned int vin1_clkenb_pins[] = {
   4287	RCAR_GP_PIN(5, 2),
   4288};
   4289static const unsigned int vin1_clkenb_mux[] = {
   4290	VI1_CLKENB_MARK,
   4291};
   4292static const unsigned int vin1_clk_pins[] = {
   4293	RCAR_GP_PIN(5, 4),
   4294};
   4295static const unsigned int vin1_clk_mux[] = {
   4296	VI1_CLK_MARK,
   4297};
   4298static const unsigned int vin1_data_b_pins[] = {
   4299	/* B */
   4300	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
   4301	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
   4302	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
   4303	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
   4304	/* G */
   4305	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
   4306	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
   4307	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
   4308	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
   4309	/* R */
   4310	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
   4311	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
   4312	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
   4313	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
   4314};
   4315static const unsigned int vin1_data_b_mux[] = {
   4316	/* B */
   4317	VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
   4318	VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
   4319	VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
   4320	VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
   4321	/* G */
   4322	VI1_G0_B_MARK, VI1_G1_B_MARK,
   4323	VI1_G2_B_MARK, VI1_G3_B_MARK,
   4324	VI1_G4_B_MARK, VI1_G5_B_MARK,
   4325	VI1_G6_B_MARK, VI1_G7_B_MARK,
   4326	/* R */
   4327	VI1_R0_B_MARK, VI1_R1_B_MARK,
   4328	VI1_R2_B_MARK, VI1_R3_B_MARK,
   4329	VI1_R4_B_MARK, VI1_R5_B_MARK,
   4330	VI1_R6_B_MARK, VI1_R7_B_MARK,
   4331};
   4332static const unsigned int vin1_data18_b_pins[] = {
   4333	/* B */
   4334	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
   4335	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
   4336	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
   4337	/* G */
   4338	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
   4339	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
   4340	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
   4341	/* R */
   4342	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
   4343	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
   4344	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
   4345};
   4346static const unsigned int vin1_data18_b_mux[] = {
   4347	/* B */
   4348	VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
   4349	VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
   4350	VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
   4351	/* G */
   4352	VI1_G2_B_MARK, VI1_G3_B_MARK,
   4353	VI1_G4_B_MARK, VI1_G5_B_MARK,
   4354	VI1_G6_B_MARK, VI1_G7_B_MARK,
   4355	/* R */
   4356	VI1_R2_B_MARK, VI1_R3_B_MARK,
   4357	VI1_R4_B_MARK, VI1_R5_B_MARK,
   4358	VI1_R6_B_MARK, VI1_R7_B_MARK,
   4359};
   4360static const unsigned int vin1_sync_b_pins[] = {
   4361	RCAR_GP_PIN(3, 17), /* HSYNC */
   4362	RCAR_GP_PIN(3, 18), /* VSYNC */
   4363};
   4364static const unsigned int vin1_sync_b_mux[] = {
   4365	VI1_HSYNC_N_B_MARK,
   4366	VI1_VSYNC_N_B_MARK,
   4367};
   4368static const unsigned int vin1_field_b_pins[] = {
   4369	RCAR_GP_PIN(3, 20),
   4370};
   4371static const unsigned int vin1_field_b_mux[] = {
   4372	VI1_FIELD_B_MARK,
   4373};
   4374static const unsigned int vin1_clkenb_b_pins[] = {
   4375	RCAR_GP_PIN(3, 19),
   4376};
   4377static const unsigned int vin1_clkenb_b_mux[] = {
   4378	VI1_CLKENB_B_MARK,
   4379};
   4380static const unsigned int vin1_clk_b_pins[] = {
   4381	RCAR_GP_PIN(3, 16),
   4382};
   4383static const unsigned int vin1_clk_b_mux[] = {
   4384	VI1_CLK_B_MARK,
   4385};
   4386/* - VIN2 ----------------------------------------------------------------- */
   4387static const unsigned int vin2_data8_pins[] = {
   4388	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
   4389	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
   4390	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
   4391	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
   4392};
   4393static const unsigned int vin2_data8_mux[] = {
   4394	VI2_DATA0_MARK, VI2_DATA1_MARK,
   4395	VI2_DATA2_MARK, VI2_DATA3_MARK,
   4396	VI2_DATA4_MARK, VI2_DATA5_MARK,
   4397	VI2_DATA6_MARK, VI2_DATA7_MARK,
   4398};
   4399static const unsigned int vin2_sync_pins[] = {
   4400	RCAR_GP_PIN(4, 15), /* HSYNC */
   4401	RCAR_GP_PIN(4, 16), /* VSYNC */
   4402};
   4403static const unsigned int vin2_sync_mux[] = {
   4404	VI2_HSYNC_N_MARK,
   4405	VI2_VSYNC_N_MARK,
   4406};
   4407static const unsigned int vin2_field_pins[] = {
   4408	RCAR_GP_PIN(4, 18),
   4409};
   4410static const unsigned int vin2_field_mux[] = {
   4411	VI2_FIELD_MARK,
   4412};
   4413static const unsigned int vin2_clkenb_pins[] = {
   4414	RCAR_GP_PIN(4, 17),
   4415};
   4416static const unsigned int vin2_clkenb_mux[] = {
   4417	VI2_CLKENB_MARK,
   4418};
   4419static const unsigned int vin2_clk_pins[] = {
   4420	RCAR_GP_PIN(4, 19),
   4421};
   4422static const unsigned int vin2_clk_mux[] = {
   4423	VI2_CLK_MARK,
   4424};
   4425
   4426static const struct {
   4427	struct sh_pfc_pin_group common[346];
   4428#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   4429	struct sh_pfc_pin_group automotive[9];
   4430#endif
   4431} pinmux_groups = {
   4432	.common = {
   4433		SH_PFC_PIN_GROUP(audio_clk_a),
   4434		SH_PFC_PIN_GROUP(audio_clk_b),
   4435		SH_PFC_PIN_GROUP(audio_clk_b_b),
   4436		SH_PFC_PIN_GROUP(audio_clk_c),
   4437		SH_PFC_PIN_GROUP(audio_clkout),
   4438		SH_PFC_PIN_GROUP(avb_link),
   4439		SH_PFC_PIN_GROUP(avb_magic),
   4440		SH_PFC_PIN_GROUP(avb_phy_int),
   4441		SH_PFC_PIN_GROUP(avb_mdio),
   4442		SH_PFC_PIN_GROUP(avb_mii),
   4443		SH_PFC_PIN_GROUP(avb_gmii),
   4444		SH_PFC_PIN_GROUP(can0_data),
   4445		SH_PFC_PIN_GROUP(can0_data_b),
   4446		SH_PFC_PIN_GROUP(can0_data_c),
   4447		SH_PFC_PIN_GROUP(can0_data_d),
   4448		SH_PFC_PIN_GROUP(can0_data_e),
   4449		SH_PFC_PIN_GROUP(can0_data_f),
   4450		SH_PFC_PIN_GROUP(can1_data),
   4451		SH_PFC_PIN_GROUP(can1_data_b),
   4452		SH_PFC_PIN_GROUP(can1_data_c),
   4453		SH_PFC_PIN_GROUP(can1_data_d),
   4454		SH_PFC_PIN_GROUP(can_clk),
   4455		SH_PFC_PIN_GROUP(can_clk_b),
   4456		SH_PFC_PIN_GROUP(can_clk_c),
   4457		SH_PFC_PIN_GROUP(can_clk_d),
   4458		SH_PFC_PIN_GROUP(du_rgb666),
   4459		SH_PFC_PIN_GROUP(du_rgb888),
   4460		SH_PFC_PIN_GROUP(du_clk_out_0),
   4461		SH_PFC_PIN_GROUP(du_clk_out_1),
   4462		SH_PFC_PIN_GROUP(du_sync),
   4463		SH_PFC_PIN_GROUP(du_oddf),
   4464		SH_PFC_PIN_GROUP(du_cde),
   4465		SH_PFC_PIN_GROUP(du_disp),
   4466		SH_PFC_PIN_GROUP(du0_clk_in),
   4467		SH_PFC_PIN_GROUP(du1_clk_in),
   4468		SH_PFC_PIN_GROUP(du1_clk_in_b),
   4469		SH_PFC_PIN_GROUP(du1_clk_in_c),
   4470		SH_PFC_PIN_GROUP(eth_link),
   4471		SH_PFC_PIN_GROUP(eth_magic),
   4472		SH_PFC_PIN_GROUP(eth_mdio),
   4473		SH_PFC_PIN_GROUP(eth_rmii),
   4474		SH_PFC_PIN_GROUP(hscif0_data),
   4475		SH_PFC_PIN_GROUP(hscif0_clk),
   4476		SH_PFC_PIN_GROUP(hscif0_ctrl),
   4477		SH_PFC_PIN_GROUP(hscif0_data_b),
   4478		SH_PFC_PIN_GROUP(hscif0_ctrl_b),
   4479		SH_PFC_PIN_GROUP(hscif0_data_c),
   4480		SH_PFC_PIN_GROUP(hscif0_clk_c),
   4481		SH_PFC_PIN_GROUP(hscif1_data),
   4482		SH_PFC_PIN_GROUP(hscif1_clk),
   4483		SH_PFC_PIN_GROUP(hscif1_ctrl),
   4484		SH_PFC_PIN_GROUP(hscif1_data_b),
   4485		SH_PFC_PIN_GROUP(hscif1_data_c),
   4486		SH_PFC_PIN_GROUP(hscif1_clk_c),
   4487		SH_PFC_PIN_GROUP(hscif1_ctrl_c),
   4488		SH_PFC_PIN_GROUP(hscif1_data_d),
   4489		SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
   4490		SH_PFC_PIN_GROUP(hscif1_clk_e),
   4491		SH_PFC_PIN_GROUP(hscif1_ctrl_e),
   4492		SH_PFC_PIN_GROUP(hscif2_data),
   4493		SH_PFC_PIN_GROUP(hscif2_clk),
   4494		SH_PFC_PIN_GROUP(hscif2_ctrl),
   4495		SH_PFC_PIN_GROUP(hscif2_data_b),
   4496		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
   4497		SH_PFC_PIN_GROUP(hscif2_data_c),
   4498		SH_PFC_PIN_GROUP(hscif2_clk_c),
   4499		SH_PFC_PIN_GROUP(hscif2_data_d),
   4500		SH_PFC_PIN_GROUP(i2c0),
   4501		SH_PFC_PIN_GROUP(i2c0_b),
   4502		SH_PFC_PIN_GROUP(i2c0_c),
   4503		SH_PFC_PIN_GROUP(i2c1),
   4504		SH_PFC_PIN_GROUP(i2c1_b),
   4505		SH_PFC_PIN_GROUP(i2c1_c),
   4506		SH_PFC_PIN_GROUP(i2c1_d),
   4507		SH_PFC_PIN_GROUP(i2c1_e),
   4508		SH_PFC_PIN_GROUP(i2c2),
   4509		SH_PFC_PIN_GROUP(i2c2_b),
   4510		SH_PFC_PIN_GROUP(i2c2_c),
   4511		SH_PFC_PIN_GROUP(i2c2_d),
   4512		SH_PFC_PIN_GROUP(i2c3),
   4513		SH_PFC_PIN_GROUP(i2c3_b),
   4514		SH_PFC_PIN_GROUP(i2c3_c),
   4515		SH_PFC_PIN_GROUP(i2c3_d),
   4516		SH_PFC_PIN_GROUP(i2c4),
   4517		SH_PFC_PIN_GROUP(i2c4_b),
   4518		SH_PFC_PIN_GROUP(i2c4_c),
   4519		SH_PFC_PIN_GROUP(i2c7),
   4520		SH_PFC_PIN_GROUP(i2c7_b),
   4521		SH_PFC_PIN_GROUP(i2c7_c),
   4522		SH_PFC_PIN_GROUP(i2c8),
   4523		SH_PFC_PIN_GROUP(i2c8_b),
   4524		SH_PFC_PIN_GROUP(i2c8_c),
   4525		SH_PFC_PIN_GROUP(intc_irq0),
   4526		SH_PFC_PIN_GROUP(intc_irq1),
   4527		SH_PFC_PIN_GROUP(intc_irq2),
   4528		SH_PFC_PIN_GROUP(intc_irq3),
   4529		BUS_DATA_PIN_GROUP(mmc_data, 1),
   4530		BUS_DATA_PIN_GROUP(mmc_data, 4),
   4531		BUS_DATA_PIN_GROUP(mmc_data, 8),
   4532		BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
   4533		SH_PFC_PIN_GROUP(mmc_ctrl),
   4534		SH_PFC_PIN_GROUP(msiof0_clk),
   4535		SH_PFC_PIN_GROUP(msiof0_sync),
   4536		SH_PFC_PIN_GROUP(msiof0_ss1),
   4537		SH_PFC_PIN_GROUP(msiof0_ss2),
   4538		SH_PFC_PIN_GROUP(msiof0_rx),
   4539		SH_PFC_PIN_GROUP(msiof0_tx),
   4540		SH_PFC_PIN_GROUP(msiof0_clk_b),
   4541		SH_PFC_PIN_GROUP(msiof0_sync_b),
   4542		SH_PFC_PIN_GROUP(msiof0_ss1_b),
   4543		SH_PFC_PIN_GROUP(msiof0_ss2_b),
   4544		SH_PFC_PIN_GROUP(msiof0_rx_b),
   4545		SH_PFC_PIN_GROUP(msiof0_tx_b),
   4546		SH_PFC_PIN_GROUP(msiof0_clk_c),
   4547		SH_PFC_PIN_GROUP(msiof0_sync_c),
   4548		SH_PFC_PIN_GROUP(msiof0_ss1_c),
   4549		SH_PFC_PIN_GROUP(msiof0_ss2_c),
   4550		SH_PFC_PIN_GROUP(msiof0_rx_c),
   4551		SH_PFC_PIN_GROUP(msiof0_tx_c),
   4552		SH_PFC_PIN_GROUP(msiof1_clk),
   4553		SH_PFC_PIN_GROUP(msiof1_sync),
   4554		SH_PFC_PIN_GROUP(msiof1_ss1),
   4555		SH_PFC_PIN_GROUP(msiof1_ss2),
   4556		SH_PFC_PIN_GROUP(msiof1_rx),
   4557		SH_PFC_PIN_GROUP(msiof1_tx),
   4558		SH_PFC_PIN_GROUP(msiof1_clk_b),
   4559		SH_PFC_PIN_GROUP(msiof1_sync_b),
   4560		SH_PFC_PIN_GROUP(msiof1_ss1_b),
   4561		SH_PFC_PIN_GROUP(msiof1_ss2_b),
   4562		SH_PFC_PIN_GROUP(msiof1_rx_b),
   4563		SH_PFC_PIN_GROUP(msiof1_tx_b),
   4564		SH_PFC_PIN_GROUP(msiof1_clk_c),
   4565		SH_PFC_PIN_GROUP(msiof1_sync_c),
   4566		SH_PFC_PIN_GROUP(msiof1_rx_c),
   4567		SH_PFC_PIN_GROUP(msiof1_tx_c),
   4568		SH_PFC_PIN_GROUP(msiof1_clk_d),
   4569		SH_PFC_PIN_GROUP(msiof1_sync_d),
   4570		SH_PFC_PIN_GROUP(msiof1_ss1_d),
   4571		SH_PFC_PIN_GROUP(msiof1_rx_d),
   4572		SH_PFC_PIN_GROUP(msiof1_tx_d),
   4573		SH_PFC_PIN_GROUP(msiof1_clk_e),
   4574		SH_PFC_PIN_GROUP(msiof1_sync_e),
   4575		SH_PFC_PIN_GROUP(msiof1_rx_e),
   4576		SH_PFC_PIN_GROUP(msiof1_tx_e),
   4577		SH_PFC_PIN_GROUP(msiof2_clk),
   4578		SH_PFC_PIN_GROUP(msiof2_sync),
   4579		SH_PFC_PIN_GROUP(msiof2_ss1),
   4580		SH_PFC_PIN_GROUP(msiof2_ss2),
   4581		SH_PFC_PIN_GROUP(msiof2_rx),
   4582		SH_PFC_PIN_GROUP(msiof2_tx),
   4583		SH_PFC_PIN_GROUP(msiof2_clk_b),
   4584		SH_PFC_PIN_GROUP(msiof2_sync_b),
   4585		SH_PFC_PIN_GROUP(msiof2_ss1_b),
   4586		SH_PFC_PIN_GROUP(msiof2_ss2_b),
   4587		SH_PFC_PIN_GROUP(msiof2_rx_b),
   4588		SH_PFC_PIN_GROUP(msiof2_tx_b),
   4589		SH_PFC_PIN_GROUP(msiof2_clk_c),
   4590		SH_PFC_PIN_GROUP(msiof2_sync_c),
   4591		SH_PFC_PIN_GROUP(msiof2_rx_c),
   4592		SH_PFC_PIN_GROUP(msiof2_tx_c),
   4593		SH_PFC_PIN_GROUP(msiof2_clk_d),
   4594		SH_PFC_PIN_GROUP(msiof2_sync_d),
   4595		SH_PFC_PIN_GROUP(msiof2_ss1_d),
   4596		SH_PFC_PIN_GROUP(msiof2_ss2_d),
   4597		SH_PFC_PIN_GROUP(msiof2_rx_d),
   4598		SH_PFC_PIN_GROUP(msiof2_tx_d),
   4599		SH_PFC_PIN_GROUP(msiof2_clk_e),
   4600		SH_PFC_PIN_GROUP(msiof2_sync_e),
   4601		SH_PFC_PIN_GROUP(msiof2_rx_e),
   4602		SH_PFC_PIN_GROUP(msiof2_tx_e),
   4603		SH_PFC_PIN_GROUP(pwm0),
   4604		SH_PFC_PIN_GROUP(pwm0_b),
   4605		SH_PFC_PIN_GROUP(pwm1),
   4606		SH_PFC_PIN_GROUP(pwm1_b),
   4607		SH_PFC_PIN_GROUP(pwm2),
   4608		SH_PFC_PIN_GROUP(pwm2_b),
   4609		SH_PFC_PIN_GROUP(pwm3),
   4610		SH_PFC_PIN_GROUP(pwm4),
   4611		SH_PFC_PIN_GROUP(pwm4_b),
   4612		SH_PFC_PIN_GROUP(pwm5),
   4613		SH_PFC_PIN_GROUP(pwm5_b),
   4614		SH_PFC_PIN_GROUP(pwm6),
   4615		SH_PFC_PIN_GROUP(qspi_ctrl),
   4616		BUS_DATA_PIN_GROUP(qspi_data, 2),
   4617		BUS_DATA_PIN_GROUP(qspi_data, 4),
   4618		SH_PFC_PIN_GROUP(qspi_ctrl_b),
   4619		BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
   4620		BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
   4621		SH_PFC_PIN_GROUP(scif0_data),
   4622		SH_PFC_PIN_GROUP(scif0_data_b),
   4623		SH_PFC_PIN_GROUP(scif0_data_c),
   4624		SH_PFC_PIN_GROUP(scif0_data_d),
   4625		SH_PFC_PIN_GROUP(scif0_data_e),
   4626		SH_PFC_PIN_GROUP(scif1_data),
   4627		SH_PFC_PIN_GROUP(scif1_data_b),
   4628		SH_PFC_PIN_GROUP(scif1_clk_b),
   4629		SH_PFC_PIN_GROUP(scif1_data_c),
   4630		SH_PFC_PIN_GROUP(scif1_data_d),
   4631		SH_PFC_PIN_GROUP(scif2_data),
   4632		SH_PFC_PIN_GROUP(scif2_data_b),
   4633		SH_PFC_PIN_GROUP(scif2_clk_b),
   4634		SH_PFC_PIN_GROUP(scif2_data_c),
   4635		SH_PFC_PIN_GROUP(scif2_data_e),
   4636		SH_PFC_PIN_GROUP(scif3_data),
   4637		SH_PFC_PIN_GROUP(scif3_clk),
   4638		SH_PFC_PIN_GROUP(scif3_data_b),
   4639		SH_PFC_PIN_GROUP(scif3_clk_b),
   4640		SH_PFC_PIN_GROUP(scif3_data_c),
   4641		SH_PFC_PIN_GROUP(scif3_data_d),
   4642		SH_PFC_PIN_GROUP(scif4_data),
   4643		SH_PFC_PIN_GROUP(scif4_data_b),
   4644		SH_PFC_PIN_GROUP(scif4_data_c),
   4645		SH_PFC_PIN_GROUP(scif5_data),
   4646		SH_PFC_PIN_GROUP(scif5_data_b),
   4647		SH_PFC_PIN_GROUP(scifa0_data),
   4648		SH_PFC_PIN_GROUP(scifa0_data_b),
   4649		SH_PFC_PIN_GROUP(scifa1_data),
   4650		SH_PFC_PIN_GROUP(scifa1_clk),
   4651		SH_PFC_PIN_GROUP(scifa1_data_b),
   4652		SH_PFC_PIN_GROUP(scifa1_clk_b),
   4653		SH_PFC_PIN_GROUP(scifa1_data_c),
   4654		SH_PFC_PIN_GROUP(scifa2_data),
   4655		SH_PFC_PIN_GROUP(scifa2_clk),
   4656		SH_PFC_PIN_GROUP(scifa2_data_b),
   4657		SH_PFC_PIN_GROUP(scifa3_data),
   4658		SH_PFC_PIN_GROUP(scifa3_clk),
   4659		SH_PFC_PIN_GROUP(scifa3_data_b),
   4660		SH_PFC_PIN_GROUP(scifa3_clk_b),
   4661		SH_PFC_PIN_GROUP(scifa3_data_c),
   4662		SH_PFC_PIN_GROUP(scifa3_clk_c),
   4663		SH_PFC_PIN_GROUP(scifa4_data),
   4664		SH_PFC_PIN_GROUP(scifa4_data_b),
   4665		SH_PFC_PIN_GROUP(scifa4_data_c),
   4666		SH_PFC_PIN_GROUP(scifa5_data),
   4667		SH_PFC_PIN_GROUP(scifa5_data_b),
   4668		SH_PFC_PIN_GROUP(scifa5_data_c),
   4669		SH_PFC_PIN_GROUP(scifb0_data),
   4670		SH_PFC_PIN_GROUP(scifb0_clk),
   4671		SH_PFC_PIN_GROUP(scifb0_ctrl),
   4672		SH_PFC_PIN_GROUP(scifb0_data_b),
   4673		SH_PFC_PIN_GROUP(scifb0_clk_b),
   4674		SH_PFC_PIN_GROUP(scifb0_ctrl_b),
   4675		SH_PFC_PIN_GROUP(scifb0_data_c),
   4676		SH_PFC_PIN_GROUP(scifb0_clk_c),
   4677		SH_PFC_PIN_GROUP(scifb0_data_d),
   4678		SH_PFC_PIN_GROUP(scifb0_clk_d),
   4679		SH_PFC_PIN_GROUP(scifb1_data),
   4680		SH_PFC_PIN_GROUP(scifb1_clk),
   4681		SH_PFC_PIN_GROUP(scifb1_ctrl),
   4682		SH_PFC_PIN_GROUP(scifb1_data_b),
   4683		SH_PFC_PIN_GROUP(scifb1_clk_b),
   4684		SH_PFC_PIN_GROUP(scifb1_data_c),
   4685		SH_PFC_PIN_GROUP(scifb1_clk_c),
   4686		SH_PFC_PIN_GROUP(scifb1_data_d),
   4687		SH_PFC_PIN_GROUP(scifb2_data),
   4688		SH_PFC_PIN_GROUP(scifb2_clk),
   4689		SH_PFC_PIN_GROUP(scifb2_ctrl),
   4690		SH_PFC_PIN_GROUP(scifb2_data_b),
   4691		SH_PFC_PIN_GROUP(scifb2_clk_b),
   4692		SH_PFC_PIN_GROUP(scifb2_ctrl_b),
   4693		SH_PFC_PIN_GROUP(scifb2_data_c),
   4694		SH_PFC_PIN_GROUP(scifb2_clk_c),
   4695		SH_PFC_PIN_GROUP(scifb2_data_d),
   4696		SH_PFC_PIN_GROUP(scif_clk),
   4697		SH_PFC_PIN_GROUP(scif_clk_b),
   4698		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
   4699		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
   4700		SH_PFC_PIN_GROUP(sdhi0_ctrl),
   4701		SH_PFC_PIN_GROUP(sdhi0_cd),
   4702		SH_PFC_PIN_GROUP(sdhi0_wp),
   4703		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
   4704		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
   4705		SH_PFC_PIN_GROUP(sdhi1_ctrl),
   4706		SH_PFC_PIN_GROUP(sdhi1_cd),
   4707		SH_PFC_PIN_GROUP(sdhi1_wp),
   4708		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
   4709		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
   4710		SH_PFC_PIN_GROUP(sdhi2_ctrl),
   4711		SH_PFC_PIN_GROUP(sdhi2_cd),
   4712		SH_PFC_PIN_GROUP(sdhi2_wp),
   4713		SH_PFC_PIN_GROUP(ssi0_data),
   4714		SH_PFC_PIN_GROUP(ssi0_data_b),
   4715		SH_PFC_PIN_GROUP(ssi0129_ctrl),
   4716		SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
   4717		SH_PFC_PIN_GROUP(ssi1_data),
   4718		SH_PFC_PIN_GROUP(ssi1_data_b),
   4719		SH_PFC_PIN_GROUP(ssi1_ctrl),
   4720		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
   4721		SH_PFC_PIN_GROUP(ssi2_data),
   4722		SH_PFC_PIN_GROUP(ssi2_ctrl),
   4723		SH_PFC_PIN_GROUP(ssi3_data),
   4724		SH_PFC_PIN_GROUP(ssi34_ctrl),
   4725		SH_PFC_PIN_GROUP(ssi4_data),
   4726		SH_PFC_PIN_GROUP(ssi4_ctrl),
   4727		SH_PFC_PIN_GROUP(ssi5_data),
   4728		SH_PFC_PIN_GROUP(ssi5_ctrl),
   4729		SH_PFC_PIN_GROUP(ssi6_data),
   4730		SH_PFC_PIN_GROUP(ssi6_ctrl),
   4731		SH_PFC_PIN_GROUP(ssi7_data),
   4732		SH_PFC_PIN_GROUP(ssi7_data_b),
   4733		SH_PFC_PIN_GROUP(ssi78_ctrl),
   4734		SH_PFC_PIN_GROUP(ssi78_ctrl_b),
   4735		SH_PFC_PIN_GROUP(ssi8_data),
   4736		SH_PFC_PIN_GROUP(ssi8_data_b),
   4737		SH_PFC_PIN_GROUP(ssi9_data),
   4738		SH_PFC_PIN_GROUP(ssi9_data_b),
   4739		SH_PFC_PIN_GROUP(ssi9_ctrl),
   4740		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
   4741		SH_PFC_PIN_GROUP(tpu_to0),
   4742		SH_PFC_PIN_GROUP(tpu_to1),
   4743		SH_PFC_PIN_GROUP(tpu_to2),
   4744		SH_PFC_PIN_GROUP(tpu_to3),
   4745		SH_PFC_PIN_GROUP(usb0),
   4746		SH_PFC_PIN_GROUP(usb1),
   4747		BUS_DATA_PIN_GROUP(vin0_data, 24),
   4748		BUS_DATA_PIN_GROUP(vin0_data, 20),
   4749		SH_PFC_PIN_GROUP(vin0_data18),
   4750		BUS_DATA_PIN_GROUP(vin0_data, 16),
   4751		BUS_DATA_PIN_GROUP(vin0_data, 12),
   4752		BUS_DATA_PIN_GROUP(vin0_data, 10),
   4753		BUS_DATA_PIN_GROUP(vin0_data, 8),
   4754		SH_PFC_PIN_GROUP(vin0_sync),
   4755		SH_PFC_PIN_GROUP(vin0_field),
   4756		SH_PFC_PIN_GROUP(vin0_clkenb),
   4757		SH_PFC_PIN_GROUP(vin0_clk),
   4758		SH_PFC_PIN_GROUP(vin1_data8),
   4759		SH_PFC_PIN_GROUP(vin1_sync),
   4760		SH_PFC_PIN_GROUP(vin1_field),
   4761		SH_PFC_PIN_GROUP(vin1_clkenb),
   4762		SH_PFC_PIN_GROUP(vin1_clk),
   4763		BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
   4764		BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
   4765		SH_PFC_PIN_GROUP(vin1_data18_b),
   4766		BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
   4767		BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
   4768		BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
   4769		BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
   4770		SH_PFC_PIN_GROUP(vin1_sync_b),
   4771		SH_PFC_PIN_GROUP(vin1_field_b),
   4772		SH_PFC_PIN_GROUP(vin1_clkenb_b),
   4773		SH_PFC_PIN_GROUP(vin1_clk_b),
   4774		SH_PFC_PIN_GROUP(vin2_data8),
   4775		SH_PFC_PIN_GROUP(vin2_sync),
   4776		SH_PFC_PIN_GROUP(vin2_field),
   4777		SH_PFC_PIN_GROUP(vin2_clkenb),
   4778		SH_PFC_PIN_GROUP(vin2_clk),
   4779	},
   4780#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   4781	.automotive = {
   4782		SH_PFC_PIN_GROUP(adi_common),
   4783		SH_PFC_PIN_GROUP(adi_chsel0),
   4784		SH_PFC_PIN_GROUP(adi_chsel1),
   4785		SH_PFC_PIN_GROUP(adi_chsel2),
   4786		SH_PFC_PIN_GROUP(adi_common_b),
   4787		SH_PFC_PIN_GROUP(adi_chsel0_b),
   4788		SH_PFC_PIN_GROUP(adi_chsel1_b),
   4789		SH_PFC_PIN_GROUP(adi_chsel2_b),
   4790		SH_PFC_PIN_GROUP(mlb_3pin),
   4791	}
   4792#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   4793};
   4794
   4795#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   4796static const char * const adi_groups[] = {
   4797	"adi_common",
   4798	"adi_chsel0",
   4799	"adi_chsel1",
   4800	"adi_chsel2",
   4801	"adi_common_b",
   4802	"adi_chsel0_b",
   4803	"adi_chsel1_b",
   4804	"adi_chsel2_b",
   4805};
   4806#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   4807
   4808static const char * const audio_clk_groups[] = {
   4809	"audio_clk_a",
   4810	"audio_clk_b",
   4811	"audio_clk_b_b",
   4812	"audio_clk_c",
   4813	"audio_clkout",
   4814};
   4815
   4816static const char * const avb_groups[] = {
   4817	"avb_link",
   4818	"avb_magic",
   4819	"avb_phy_int",
   4820	"avb_mdio",
   4821	"avb_mii",
   4822	"avb_gmii",
   4823};
   4824
   4825static const char * const can0_groups[] = {
   4826	"can0_data",
   4827	"can0_data_b",
   4828	"can0_data_c",
   4829	"can0_data_d",
   4830	"can0_data_e",
   4831	"can0_data_f",
   4832	/*
   4833	 * Retained for backwards compatibility, use can_clk_groups in new
   4834	 * designs.
   4835	 */
   4836	"can_clk",
   4837	"can_clk_b",
   4838	"can_clk_c",
   4839	"can_clk_d",
   4840};
   4841
   4842static const char * const can1_groups[] = {
   4843	"can1_data",
   4844	"can1_data_b",
   4845	"can1_data_c",
   4846	"can1_data_d",
   4847	/*
   4848	 * Retained for backwards compatibility, use can_clk_groups in new
   4849	 * designs.
   4850	 */
   4851	"can_clk",
   4852	"can_clk_b",
   4853	"can_clk_c",
   4854	"can_clk_d",
   4855};
   4856
   4857/*
   4858 * can_clk_groups allows for independent configuration, use can_clk function
   4859 * in new designs.
   4860 */
   4861static const char * const can_clk_groups[] = {
   4862	"can_clk",
   4863	"can_clk_b",
   4864	"can_clk_c",
   4865	"can_clk_d",
   4866};
   4867
   4868static const char * const du_groups[] = {
   4869	"du_rgb666",
   4870	"du_rgb888",
   4871	"du_clk_out_0",
   4872	"du_clk_out_1",
   4873	"du_sync",
   4874	"du_oddf",
   4875	"du_cde",
   4876	"du_disp",
   4877};
   4878
   4879static const char * const du0_groups[] = {
   4880	"du0_clk_in",
   4881};
   4882
   4883static const char * const du1_groups[] = {
   4884	"du1_clk_in",
   4885	"du1_clk_in_b",
   4886	"du1_clk_in_c",
   4887};
   4888
   4889static const char * const eth_groups[] = {
   4890	"eth_link",
   4891	"eth_magic",
   4892	"eth_mdio",
   4893	"eth_rmii",
   4894};
   4895
   4896static const char * const hscif0_groups[] = {
   4897	"hscif0_data",
   4898	"hscif0_clk",
   4899	"hscif0_ctrl",
   4900	"hscif0_data_b",
   4901	"hscif0_ctrl_b",
   4902	"hscif0_data_c",
   4903	"hscif0_clk_c",
   4904};
   4905
   4906static const char * const hscif1_groups[] = {
   4907	"hscif1_data",
   4908	"hscif1_clk",
   4909	"hscif1_ctrl",
   4910	"hscif1_data_b",
   4911	"hscif1_data_c",
   4912	"hscif1_clk_c",
   4913	"hscif1_ctrl_c",
   4914	"hscif1_data_d",
   4915	"hscif1_data_e",
   4916	"hscif1_clk_e",
   4917	"hscif1_ctrl_e",
   4918};
   4919
   4920static const char * const hscif2_groups[] = {
   4921	"hscif2_data",
   4922	"hscif2_clk",
   4923	"hscif2_ctrl",
   4924	"hscif2_data_b",
   4925	"hscif2_ctrl_b",
   4926	"hscif2_data_c",
   4927	"hscif2_clk_c",
   4928	"hscif2_data_d",
   4929};
   4930
   4931static const char * const i2c0_groups[] = {
   4932	"i2c0",
   4933	"i2c0_b",
   4934	"i2c0_c",
   4935};
   4936
   4937static const char * const i2c1_groups[] = {
   4938	"i2c1",
   4939	"i2c1_b",
   4940	"i2c1_c",
   4941	"i2c1_d",
   4942	"i2c1_e",
   4943};
   4944
   4945static const char * const i2c2_groups[] = {
   4946	"i2c2",
   4947	"i2c2_b",
   4948	"i2c2_c",
   4949	"i2c2_d",
   4950};
   4951
   4952static const char * const i2c3_groups[] = {
   4953	"i2c3",
   4954	"i2c3_b",
   4955	"i2c3_c",
   4956	"i2c3_d",
   4957};
   4958
   4959static const char * const i2c4_groups[] = {
   4960	"i2c4",
   4961	"i2c4_b",
   4962	"i2c4_c",
   4963};
   4964
   4965static const char * const i2c7_groups[] = {
   4966	"i2c7",
   4967	"i2c7_b",
   4968	"i2c7_c",
   4969};
   4970
   4971static const char * const i2c8_groups[] = {
   4972	"i2c8",
   4973	"i2c8_b",
   4974	"i2c8_c",
   4975};
   4976
   4977static const char * const intc_groups[] = {
   4978	"intc_irq0",
   4979	"intc_irq1",
   4980	"intc_irq2",
   4981	"intc_irq3",
   4982};
   4983
   4984#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   4985static const char * const mlb_groups[] = {
   4986	"mlb_3pin",
   4987};
   4988#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   4989
   4990static const char * const mmc_groups[] = {
   4991	"mmc_data1",
   4992	"mmc_data4",
   4993	"mmc_data8",
   4994	"mmc_data8_b",
   4995	"mmc_ctrl",
   4996};
   4997
   4998static const char * const msiof0_groups[] = {
   4999	"msiof0_clk",
   5000	"msiof0_sync",
   5001	"msiof0_ss1",
   5002	"msiof0_ss2",
   5003	"msiof0_rx",
   5004	"msiof0_tx",
   5005	"msiof0_clk_b",
   5006	"msiof0_sync_b",
   5007	"msiof0_ss1_b",
   5008	"msiof0_ss2_b",
   5009	"msiof0_rx_b",
   5010	"msiof0_tx_b",
   5011	"msiof0_clk_c",
   5012	"msiof0_sync_c",
   5013	"msiof0_ss1_c",
   5014	"msiof0_ss2_c",
   5015	"msiof0_rx_c",
   5016	"msiof0_tx_c",
   5017};
   5018
   5019static const char * const msiof1_groups[] = {
   5020	"msiof1_clk",
   5021	"msiof1_sync",
   5022	"msiof1_ss1",
   5023	"msiof1_ss2",
   5024	"msiof1_rx",
   5025	"msiof1_tx",
   5026	"msiof1_clk_b",
   5027	"msiof1_sync_b",
   5028	"msiof1_ss1_b",
   5029	"msiof1_ss2_b",
   5030	"msiof1_rx_b",
   5031	"msiof1_tx_b",
   5032	"msiof1_clk_c",
   5033	"msiof1_sync_c",
   5034	"msiof1_rx_c",
   5035	"msiof1_tx_c",
   5036	"msiof1_clk_d",
   5037	"msiof1_sync_d",
   5038	"msiof1_ss1_d",
   5039	"msiof1_rx_d",
   5040	"msiof1_tx_d",
   5041	"msiof1_clk_e",
   5042	"msiof1_sync_e",
   5043	"msiof1_rx_e",
   5044	"msiof1_tx_e",
   5045};
   5046
   5047static const char * const msiof2_groups[] = {
   5048	"msiof2_clk",
   5049	"msiof2_sync",
   5050	"msiof2_ss1",
   5051	"msiof2_ss2",
   5052	"msiof2_rx",
   5053	"msiof2_tx",
   5054	"msiof2_clk_b",
   5055	"msiof2_sync_b",
   5056	"msiof2_ss1_b",
   5057	"msiof2_ss2_b",
   5058	"msiof2_rx_b",
   5059	"msiof2_tx_b",
   5060	"msiof2_clk_c",
   5061	"msiof2_sync_c",
   5062	"msiof2_rx_c",
   5063	"msiof2_tx_c",
   5064	"msiof2_clk_d",
   5065	"msiof2_sync_d",
   5066	"msiof2_ss1_d",
   5067	"msiof2_ss2_d",
   5068	"msiof2_rx_d",
   5069	"msiof2_tx_d",
   5070	"msiof2_clk_e",
   5071	"msiof2_sync_e",
   5072	"msiof2_rx_e",
   5073	"msiof2_tx_e",
   5074};
   5075
   5076static const char * const pwm0_groups[] = {
   5077	"pwm0",
   5078	"pwm0_b",
   5079};
   5080
   5081static const char * const pwm1_groups[] = {
   5082	"pwm1",
   5083	"pwm1_b",
   5084};
   5085
   5086static const char * const pwm2_groups[] = {
   5087	"pwm2",
   5088	"pwm2_b",
   5089};
   5090
   5091static const char * const pwm3_groups[] = {
   5092	"pwm3",
   5093};
   5094
   5095static const char * const pwm4_groups[] = {
   5096	"pwm4",
   5097	"pwm4_b",
   5098};
   5099
   5100static const char * const pwm5_groups[] = {
   5101	"pwm5",
   5102	"pwm5_b",
   5103};
   5104
   5105static const char * const pwm6_groups[] = {
   5106	"pwm6",
   5107};
   5108
   5109static const char * const qspi_groups[] = {
   5110	"qspi_ctrl",
   5111	"qspi_data2",
   5112	"qspi_data4",
   5113	"qspi_ctrl_b",
   5114	"qspi_data2_b",
   5115	"qspi_data4_b",
   5116};
   5117
   5118static const char * const scif0_groups[] = {
   5119	"scif0_data",
   5120	"scif0_data_b",
   5121	"scif0_data_c",
   5122	"scif0_data_d",
   5123	"scif0_data_e",
   5124};
   5125
   5126static const char * const scif1_groups[] = {
   5127	"scif1_data",
   5128	"scif1_data_b",
   5129	"scif1_clk_b",
   5130	"scif1_data_c",
   5131	"scif1_data_d",
   5132};
   5133
   5134static const char * const scif2_groups[] = {
   5135	"scif2_data",
   5136	"scif2_data_b",
   5137	"scif2_clk_b",
   5138	"scif2_data_c",
   5139	"scif2_data_e",
   5140};
   5141static const char * const scif3_groups[] = {
   5142	"scif3_data",
   5143	"scif3_clk",
   5144	"scif3_data_b",
   5145	"scif3_clk_b",
   5146	"scif3_data_c",
   5147	"scif3_data_d",
   5148};
   5149static const char * const scif4_groups[] = {
   5150	"scif4_data",
   5151	"scif4_data_b",
   5152	"scif4_data_c",
   5153};
   5154static const char * const scif5_groups[] = {
   5155	"scif5_data",
   5156	"scif5_data_b",
   5157};
   5158static const char * const scifa0_groups[] = {
   5159	"scifa0_data",
   5160	"scifa0_data_b",
   5161};
   5162static const char * const scifa1_groups[] = {
   5163	"scifa1_data",
   5164	"scifa1_clk",
   5165	"scifa1_data_b",
   5166	"scifa1_clk_b",
   5167	"scifa1_data_c",
   5168};
   5169static const char * const scifa2_groups[] = {
   5170	"scifa2_data",
   5171	"scifa2_clk",
   5172	"scifa2_data_b",
   5173};
   5174static const char * const scifa3_groups[] = {
   5175	"scifa3_data",
   5176	"scifa3_clk",
   5177	"scifa3_data_b",
   5178	"scifa3_clk_b",
   5179	"scifa3_data_c",
   5180	"scifa3_clk_c",
   5181};
   5182static const char * const scifa4_groups[] = {
   5183	"scifa4_data",
   5184	"scifa4_data_b",
   5185	"scifa4_data_c",
   5186};
   5187static const char * const scifa5_groups[] = {
   5188	"scifa5_data",
   5189	"scifa5_data_b",
   5190	"scifa5_data_c",
   5191};
   5192static const char * const scifb0_groups[] = {
   5193	"scifb0_data",
   5194	"scifb0_clk",
   5195	"scifb0_ctrl",
   5196	"scifb0_data_b",
   5197	"scifb0_clk_b",
   5198	"scifb0_ctrl_b",
   5199	"scifb0_data_c",
   5200	"scifb0_clk_c",
   5201	"scifb0_data_d",
   5202	"scifb0_clk_d",
   5203};
   5204static const char * const scifb1_groups[] = {
   5205	"scifb1_data",
   5206	"scifb1_clk",
   5207	"scifb1_ctrl",
   5208	"scifb1_data_b",
   5209	"scifb1_clk_b",
   5210	"scifb1_data_c",
   5211	"scifb1_clk_c",
   5212	"scifb1_data_d",
   5213};
   5214static const char * const scifb2_groups[] = {
   5215	"scifb2_data",
   5216	"scifb2_clk",
   5217	"scifb2_ctrl",
   5218	"scifb2_data_b",
   5219	"scifb2_clk_b",
   5220	"scifb2_ctrl_b",
   5221	"scifb2_data_c",
   5222	"scifb2_clk_c",
   5223	"scifb2_data_d",
   5224};
   5225
   5226static const char * const scif_clk_groups[] = {
   5227	"scif_clk",
   5228	"scif_clk_b",
   5229};
   5230
   5231static const char * const sdhi0_groups[] = {
   5232	"sdhi0_data1",
   5233	"sdhi0_data4",
   5234	"sdhi0_ctrl",
   5235	"sdhi0_cd",
   5236	"sdhi0_wp",
   5237};
   5238
   5239static const char * const sdhi1_groups[] = {
   5240	"sdhi1_data1",
   5241	"sdhi1_data4",
   5242	"sdhi1_ctrl",
   5243	"sdhi1_cd",
   5244	"sdhi1_wp",
   5245};
   5246
   5247static const char * const sdhi2_groups[] = {
   5248	"sdhi2_data1",
   5249	"sdhi2_data4",
   5250	"sdhi2_ctrl",
   5251	"sdhi2_cd",
   5252	"sdhi2_wp",
   5253};
   5254
   5255static const char * const ssi_groups[] = {
   5256	"ssi0_data",
   5257	"ssi0_data_b",
   5258	"ssi0129_ctrl",
   5259	"ssi0129_ctrl_b",
   5260	"ssi1_data",
   5261	"ssi1_data_b",
   5262	"ssi1_ctrl",
   5263	"ssi1_ctrl_b",
   5264	"ssi2_data",
   5265	"ssi2_ctrl",
   5266	"ssi3_data",
   5267	"ssi34_ctrl",
   5268	"ssi4_data",
   5269	"ssi4_ctrl",
   5270	"ssi5_data",
   5271	"ssi5_ctrl",
   5272	"ssi6_data",
   5273	"ssi6_ctrl",
   5274	"ssi7_data",
   5275	"ssi7_data_b",
   5276	"ssi78_ctrl",
   5277	"ssi78_ctrl_b",
   5278	"ssi8_data",
   5279	"ssi8_data_b",
   5280	"ssi9_data",
   5281	"ssi9_data_b",
   5282	"ssi9_ctrl",
   5283	"ssi9_ctrl_b",
   5284};
   5285
   5286static const char * const tpu_groups[] = {
   5287	"tpu_to0",
   5288	"tpu_to1",
   5289	"tpu_to2",
   5290	"tpu_to3",
   5291};
   5292
   5293static const char * const usb0_groups[] = {
   5294	"usb0",
   5295};
   5296static const char * const usb1_groups[] = {
   5297	"usb1",
   5298};
   5299
   5300static const char * const vin0_groups[] = {
   5301	"vin0_data24",
   5302	"vin0_data20",
   5303	"vin0_data18",
   5304	"vin0_data16",
   5305	"vin0_data12",
   5306	"vin0_data10",
   5307	"vin0_data8",
   5308	"vin0_sync",
   5309	"vin0_field",
   5310	"vin0_clkenb",
   5311	"vin0_clk",
   5312};
   5313
   5314static const char * const vin1_groups[] = {
   5315	"vin1_data8",
   5316	"vin1_sync",
   5317	"vin1_field",
   5318	"vin1_clkenb",
   5319	"vin1_clk",
   5320	"vin1_data24_b",
   5321	"vin1_data20_b",
   5322	"vin1_data18_b",
   5323	"vin1_data16_b",
   5324	"vin1_data12_b",
   5325	"vin1_data10_b",
   5326	"vin1_data8_b",
   5327	"vin1_sync_b",
   5328	"vin1_field_b",
   5329	"vin1_clkenb_b",
   5330	"vin1_clk_b",
   5331};
   5332
   5333static const char * const vin2_groups[] = {
   5334	"vin2_data8",
   5335	"vin2_sync",
   5336	"vin2_field",
   5337	"vin2_clkenb",
   5338	"vin2_clk",
   5339};
   5340
   5341static const struct {
   5342	struct sh_pfc_function common[58];
   5343#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   5344	struct sh_pfc_function automotive[2];
   5345#endif
   5346} pinmux_functions = {
   5347	.common = {
   5348		SH_PFC_FUNCTION(audio_clk),
   5349		SH_PFC_FUNCTION(avb),
   5350		SH_PFC_FUNCTION(can0),
   5351		SH_PFC_FUNCTION(can1),
   5352		SH_PFC_FUNCTION(can_clk),
   5353		SH_PFC_FUNCTION(du),
   5354		SH_PFC_FUNCTION(du0),
   5355		SH_PFC_FUNCTION(du1),
   5356		SH_PFC_FUNCTION(eth),
   5357		SH_PFC_FUNCTION(hscif0),
   5358		SH_PFC_FUNCTION(hscif1),
   5359		SH_PFC_FUNCTION(hscif2),
   5360		SH_PFC_FUNCTION(i2c0),
   5361		SH_PFC_FUNCTION(i2c1),
   5362		SH_PFC_FUNCTION(i2c2),
   5363		SH_PFC_FUNCTION(i2c3),
   5364		SH_PFC_FUNCTION(i2c4),
   5365		SH_PFC_FUNCTION(i2c7),
   5366		SH_PFC_FUNCTION(i2c8),
   5367		SH_PFC_FUNCTION(intc),
   5368		SH_PFC_FUNCTION(mmc),
   5369		SH_PFC_FUNCTION(msiof0),
   5370		SH_PFC_FUNCTION(msiof1),
   5371		SH_PFC_FUNCTION(msiof2),
   5372		SH_PFC_FUNCTION(pwm0),
   5373		SH_PFC_FUNCTION(pwm1),
   5374		SH_PFC_FUNCTION(pwm2),
   5375		SH_PFC_FUNCTION(pwm3),
   5376		SH_PFC_FUNCTION(pwm4),
   5377		SH_PFC_FUNCTION(pwm5),
   5378		SH_PFC_FUNCTION(pwm6),
   5379		SH_PFC_FUNCTION(qspi),
   5380		SH_PFC_FUNCTION(scif0),
   5381		SH_PFC_FUNCTION(scif1),
   5382		SH_PFC_FUNCTION(scif2),
   5383		SH_PFC_FUNCTION(scif3),
   5384		SH_PFC_FUNCTION(scif4),
   5385		SH_PFC_FUNCTION(scif5),
   5386		SH_PFC_FUNCTION(scifa0),
   5387		SH_PFC_FUNCTION(scifa1),
   5388		SH_PFC_FUNCTION(scifa2),
   5389		SH_PFC_FUNCTION(scifa3),
   5390		SH_PFC_FUNCTION(scifa4),
   5391		SH_PFC_FUNCTION(scifa5),
   5392		SH_PFC_FUNCTION(scifb0),
   5393		SH_PFC_FUNCTION(scifb1),
   5394		SH_PFC_FUNCTION(scifb2),
   5395		SH_PFC_FUNCTION(scif_clk),
   5396		SH_PFC_FUNCTION(sdhi0),
   5397		SH_PFC_FUNCTION(sdhi1),
   5398		SH_PFC_FUNCTION(sdhi2),
   5399		SH_PFC_FUNCTION(ssi),
   5400		SH_PFC_FUNCTION(tpu),
   5401		SH_PFC_FUNCTION(usb0),
   5402		SH_PFC_FUNCTION(usb1),
   5403		SH_PFC_FUNCTION(vin0),
   5404		SH_PFC_FUNCTION(vin1),
   5405		SH_PFC_FUNCTION(vin2),
   5406	},
   5407#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
   5408	.automotive = {
   5409		SH_PFC_FUNCTION(adi),
   5410		SH_PFC_FUNCTION(mlb),
   5411	}
   5412#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
   5413};
   5414
   5415static const struct pinmux_cfg_reg pinmux_config_regs[] = {
   5416	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
   5417		GP_0_31_FN, FN_IP1_22_20,
   5418		GP_0_30_FN, FN_IP1_19_17,
   5419		GP_0_29_FN, FN_IP1_16_14,
   5420		GP_0_28_FN, FN_IP1_13_11,
   5421		GP_0_27_FN, FN_IP1_10_8,
   5422		GP_0_26_FN, FN_IP1_7_6,
   5423		GP_0_25_FN, FN_IP1_5_4,
   5424		GP_0_24_FN, FN_IP1_3_2,
   5425		GP_0_23_FN, FN_IP1_1_0,
   5426		GP_0_22_FN, FN_IP0_30_29,
   5427		GP_0_21_FN, FN_IP0_28_27,
   5428		GP_0_20_FN, FN_IP0_26_25,
   5429		GP_0_19_FN, FN_IP0_24_23,
   5430		GP_0_18_FN, FN_IP0_22_21,
   5431		GP_0_17_FN, FN_IP0_20_19,
   5432		GP_0_16_FN, FN_IP0_18_16,
   5433		GP_0_15_FN, FN_IP0_15,
   5434		GP_0_14_FN, FN_IP0_14,
   5435		GP_0_13_FN, FN_IP0_13,
   5436		GP_0_12_FN, FN_IP0_12,
   5437		GP_0_11_FN, FN_IP0_11,
   5438		GP_0_10_FN, FN_IP0_10,
   5439		GP_0_9_FN, FN_IP0_9,
   5440		GP_0_8_FN, FN_IP0_8,
   5441		GP_0_7_FN, FN_IP0_7,
   5442		GP_0_6_FN, FN_IP0_6,
   5443		GP_0_5_FN, FN_IP0_5,
   5444		GP_0_4_FN, FN_IP0_4,
   5445		GP_0_3_FN, FN_IP0_3,
   5446		GP_0_2_FN, FN_IP0_2,
   5447		GP_0_1_FN, FN_IP0_1,
   5448		GP_0_0_FN, FN_IP0_0, ))
   5449	},
   5450	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
   5451		0, 0,
   5452		0, 0,
   5453		0, 0,
   5454		0, 0,
   5455		0, 0,
   5456		0, 0,
   5457		GP_1_25_FN, FN_IP3_21_20,
   5458		GP_1_24_FN, FN_IP3_19_18,
   5459		GP_1_23_FN, FN_IP3_17_16,
   5460		GP_1_22_FN, FN_IP3_15_14,
   5461		GP_1_21_FN, FN_IP3_13_12,
   5462		GP_1_20_FN, FN_IP3_11_9,
   5463		GP_1_19_FN, FN_RD_N,
   5464		GP_1_18_FN, FN_IP3_8_6,
   5465		GP_1_17_FN, FN_IP3_5_3,
   5466		GP_1_16_FN, FN_IP3_2_0,
   5467		GP_1_15_FN, FN_IP2_29_27,
   5468		GP_1_14_FN, FN_IP2_26_25,
   5469		GP_1_13_FN, FN_IP2_24_23,
   5470		GP_1_12_FN, FN_EX_CS0_N,
   5471		GP_1_11_FN, FN_IP2_22_21,
   5472		GP_1_10_FN, FN_IP2_20_19,
   5473		GP_1_9_FN, FN_IP2_18_16,
   5474		GP_1_8_FN, FN_IP2_15_13,
   5475		GP_1_7_FN, FN_IP2_12_10,
   5476		GP_1_6_FN, FN_IP2_9_7,
   5477		GP_1_5_FN, FN_IP2_6_5,
   5478		GP_1_4_FN, FN_IP2_4_3,
   5479		GP_1_3_FN, FN_IP2_2_0,
   5480		GP_1_2_FN, FN_IP1_31_29,
   5481		GP_1_1_FN, FN_IP1_28_26,
   5482		GP_1_0_FN, FN_IP1_25_23, ))
   5483	},
   5484	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
   5485		GP_2_31_FN, FN_IP6_7_6,
   5486		GP_2_30_FN, FN_IP6_5_3,
   5487		GP_2_29_FN, FN_IP6_2_0,
   5488		GP_2_28_FN, FN_AUDIO_CLKA,
   5489		GP_2_27_FN, FN_IP5_31_29,
   5490		GP_2_26_FN, FN_IP5_28_26,
   5491		GP_2_25_FN, FN_IP5_25_24,
   5492		GP_2_24_FN, FN_IP5_23_22,
   5493		GP_2_23_FN, FN_IP5_21_20,
   5494		GP_2_22_FN, FN_IP5_19_17,
   5495		GP_2_21_FN, FN_IP5_16_15,
   5496		GP_2_20_FN, FN_IP5_14_12,
   5497		GP_2_19_FN, FN_IP5_11_9,
   5498		GP_2_18_FN, FN_IP5_8_6,
   5499		GP_2_17_FN, FN_IP5_5_3,
   5500		GP_2_16_FN, FN_IP5_2_0,
   5501		GP_2_15_FN, FN_IP4_30_28,
   5502		GP_2_14_FN, FN_IP4_27_26,
   5503		GP_2_13_FN, FN_IP4_25_24,
   5504		GP_2_12_FN, FN_IP4_23_22,
   5505		GP_2_11_FN, FN_IP4_21,
   5506		GP_2_10_FN, FN_IP4_20,
   5507		GP_2_9_FN, FN_IP4_19,
   5508		GP_2_8_FN, FN_IP4_18_16,
   5509		GP_2_7_FN, FN_IP4_15_13,
   5510		GP_2_6_FN, FN_IP4_12_10,
   5511		GP_2_5_FN, FN_IP4_9_8,
   5512		GP_2_4_FN, FN_IP4_7_5,
   5513		GP_2_3_FN, FN_IP4_4_2,
   5514		GP_2_2_FN, FN_IP4_1_0,
   5515		GP_2_1_FN, FN_IP3_30_28,
   5516		GP_2_0_FN, FN_IP3_27_25 ))
   5517	},
   5518	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
   5519		GP_3_31_FN, FN_IP9_18_17,
   5520		GP_3_30_FN, FN_IP9_16,
   5521		GP_3_29_FN, FN_IP9_15_13,
   5522		GP_3_28_FN, FN_IP9_12,
   5523		GP_3_27_FN, FN_IP9_11,
   5524		GP_3_26_FN, FN_IP9_10_8,
   5525		GP_3_25_FN, FN_IP9_7,
   5526		GP_3_24_FN, FN_IP9_6,
   5527		GP_3_23_FN, FN_IP9_5_3,
   5528		GP_3_22_FN, FN_IP9_2_0,
   5529		GP_3_21_FN, FN_IP8_30_28,
   5530		GP_3_20_FN, FN_IP8_27_26,
   5531		GP_3_19_FN, FN_IP8_25_24,
   5532		GP_3_18_FN, FN_IP8_23_21,
   5533		GP_3_17_FN, FN_IP8_20_18,
   5534		GP_3_16_FN, FN_IP8_17_15,
   5535		GP_3_15_FN, FN_IP8_14_12,
   5536		GP_3_14_FN, FN_IP8_11_9,
   5537		GP_3_13_FN, FN_IP8_8_6,
   5538		GP_3_12_FN, FN_IP8_5_3,
   5539		GP_3_11_FN, FN_IP8_2_0,
   5540		GP_3_10_FN, FN_IP7_29_27,
   5541		GP_3_9_FN, FN_IP7_26_24,
   5542		GP_3_8_FN, FN_IP7_23_21,
   5543		GP_3_7_FN, FN_IP7_20_19,
   5544		GP_3_6_FN, FN_IP7_18_17,
   5545		GP_3_5_FN, FN_IP7_16_15,
   5546		GP_3_4_FN, FN_IP7_14_13,
   5547		GP_3_3_FN, FN_IP7_12_11,
   5548		GP_3_2_FN, FN_IP7_10_9,
   5549		GP_3_1_FN, FN_IP7_8_6,
   5550		GP_3_0_FN, FN_IP7_5_3 ))
   5551	},
   5552	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
   5553		GP_4_31_FN, FN_IP15_5_4,
   5554		GP_4_30_FN, FN_IP15_3_2,
   5555		GP_4_29_FN, FN_IP15_1_0,
   5556		GP_4_28_FN, FN_IP11_8_6,
   5557		GP_4_27_FN, FN_IP11_5_3,
   5558		GP_4_26_FN, FN_IP11_2_0,
   5559		GP_4_25_FN, FN_IP10_31_29,
   5560		GP_4_24_FN, FN_IP10_28_27,
   5561		GP_4_23_FN, FN_IP10_26_25,
   5562		GP_4_22_FN, FN_IP10_24_22,
   5563		GP_4_21_FN, FN_IP10_21_19,
   5564		GP_4_20_FN, FN_IP10_18_17,
   5565		GP_4_19_FN, FN_IP10_16_15,
   5566		GP_4_18_FN, FN_IP10_14_12,
   5567		GP_4_17_FN, FN_IP10_11_9,
   5568		GP_4_16_FN, FN_IP10_8_6,
   5569		GP_4_15_FN, FN_IP10_5_3,
   5570		GP_4_14_FN, FN_IP10_2_0,
   5571		GP_4_13_FN, FN_IP9_31_29,
   5572		GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
   5573		GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
   5574		GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
   5575		GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
   5576		GP_4_8_FN, FN_IP9_28_27,
   5577		GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
   5578		GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
   5579		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
   5580		GP_4_4_FN, FN_IP9_26_25,
   5581		GP_4_3_FN, FN_IP9_24_23,
   5582		GP_4_2_FN, FN_IP9_22_21,
   5583		GP_4_1_FN, FN_IP9_20_19,
   5584		GP_4_0_FN, FN_VI0_CLK ))
   5585	},
   5586	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
   5587		GP_5_31_FN, FN_IP3_24_22,
   5588		GP_5_30_FN, FN_IP13_9_7,
   5589		GP_5_29_FN, FN_IP13_6_5,
   5590		GP_5_28_FN, FN_IP13_4_3,
   5591		GP_5_27_FN, FN_IP13_2_0,
   5592		GP_5_26_FN, FN_IP12_29_27,
   5593		GP_5_25_FN, FN_IP12_26_24,
   5594		GP_5_24_FN, FN_IP12_23_22,
   5595		GP_5_23_FN, FN_IP12_21_20,
   5596		GP_5_22_FN, FN_IP12_19_18,
   5597		GP_5_21_FN, FN_IP12_17_16,
   5598		GP_5_20_FN, FN_IP12_15_13,
   5599		GP_5_19_FN, FN_IP12_12_10,
   5600		GP_5_18_FN, FN_IP12_9_7,
   5601		GP_5_17_FN, FN_IP12_6_4,
   5602		GP_5_16_FN, FN_IP12_3_2,
   5603		GP_5_15_FN, FN_IP12_1_0,
   5604		GP_5_14_FN, FN_IP11_31_30,
   5605		GP_5_13_FN, FN_IP11_29_28,
   5606		GP_5_12_FN, FN_IP11_27,
   5607		GP_5_11_FN, FN_IP11_26,
   5608		GP_5_10_FN, FN_IP11_25,
   5609		GP_5_9_FN, FN_IP11_24,
   5610		GP_5_8_FN, FN_IP11_23,
   5611		GP_5_7_FN, FN_IP11_22,
   5612		GP_5_6_FN, FN_IP11_21,
   5613		GP_5_5_FN, FN_IP11_20,
   5614		GP_5_4_FN, FN_IP11_19,
   5615		GP_5_3_FN, FN_IP11_18_17,
   5616		GP_5_2_FN, FN_IP11_16_15,
   5617		GP_5_1_FN, FN_IP11_14_12,
   5618		GP_5_0_FN, FN_IP11_11_9 ))
   5619	},
   5620	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
   5621		GP_6_31_FN, FN_DU0_DOTCLKIN,
   5622		GP_6_30_FN, FN_USB1_OVC,
   5623		GP_6_29_FN, FN_IP14_31_29,
   5624		GP_6_28_FN, FN_IP14_28_26,
   5625		GP_6_27_FN, FN_IP14_25_23,
   5626		GP_6_26_FN, FN_IP14_22_20,
   5627		GP_6_25_FN, FN_IP14_19_17,
   5628		GP_6_24_FN, FN_IP14_16_14,
   5629		GP_6_23_FN, FN_IP14_13_11,
   5630		GP_6_22_FN, FN_IP14_10_8,
   5631		GP_6_21_FN, FN_IP14_7,
   5632		GP_6_20_FN, FN_IP14_6,
   5633		GP_6_19_FN, FN_IP14_5,
   5634		GP_6_18_FN, FN_IP14_4,
   5635		GP_6_17_FN, FN_IP14_3,
   5636		GP_6_16_FN, FN_IP14_2,
   5637		GP_6_15_FN, FN_IP14_1_0,
   5638		GP_6_14_FN, FN_IP13_30_28,
   5639		GP_6_13_FN, FN_IP13_27,
   5640		GP_6_12_FN, FN_IP13_26,
   5641		GP_6_11_FN, FN_IP13_25,
   5642		GP_6_10_FN, FN_IP13_24_23,
   5643		GP_6_9_FN, FN_IP13_22,
   5644		GP_6_8_FN, FN_SD1_CLK,
   5645		GP_6_7_FN, FN_IP13_21_19,
   5646		GP_6_6_FN, FN_IP13_18_16,
   5647		GP_6_5_FN, FN_IP13_15,
   5648		GP_6_4_FN, FN_IP13_14,
   5649		GP_6_3_FN, FN_IP13_13,
   5650		GP_6_2_FN, FN_IP13_12,
   5651		GP_6_1_FN, FN_IP13_11,
   5652		GP_6_0_FN, FN_IP13_10 ))
   5653	},
   5654	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
   5655		0, 0,
   5656		0, 0,
   5657		0, 0,
   5658		0, 0,
   5659		0, 0,
   5660		0, 0,
   5661		GP_7_25_FN, FN_USB1_PWEN,
   5662		GP_7_24_FN, FN_USB0_OVC,
   5663		GP_7_23_FN, FN_USB0_PWEN,
   5664		GP_7_22_FN, FN_IP15_14_12,
   5665		GP_7_21_FN, FN_IP15_11_9,
   5666		GP_7_20_FN, FN_IP15_8_6,
   5667		GP_7_19_FN, FN_IP7_2_0,
   5668		GP_7_18_FN, FN_IP6_29_27,
   5669		GP_7_17_FN, FN_IP6_26_24,
   5670		GP_7_16_FN, FN_IP6_23_21,
   5671		GP_7_15_FN, FN_IP6_20_19,
   5672		GP_7_14_FN, FN_IP6_18_16,
   5673		GP_7_13_FN, FN_IP6_15_14,
   5674		GP_7_12_FN, FN_IP6_13_12,
   5675		GP_7_11_FN, FN_IP6_11_10,
   5676		GP_7_10_FN, FN_IP6_9_8,
   5677		GP_7_9_FN, FN_IP16_11_10,
   5678		GP_7_8_FN, FN_IP16_9_8,
   5679		GP_7_7_FN, FN_IP16_7_6,
   5680		GP_7_6_FN, FN_IP16_5_3,
   5681		GP_7_5_FN, FN_IP16_2_0,
   5682		GP_7_4_FN, FN_IP15_29_27,
   5683		GP_7_3_FN, FN_IP15_26_24,
   5684		GP_7_2_FN, FN_IP15_23_21,
   5685		GP_7_1_FN, FN_IP15_20_18,
   5686		GP_7_0_FN, FN_IP15_17_15 ))
   5687	},
   5688	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
   5689			     GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
   5690				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
   5691			     GROUP(
   5692		/* IP0_31 [1] RESERVED */
   5693		/* IP0_30_29 [2] */
   5694		FN_A6, FN_MSIOF1_SCK,
   5695		0, 0,
   5696		/* IP0_28_27 [2] */
   5697		FN_A5, FN_MSIOF0_RXD_B,
   5698		0, 0,
   5699		/* IP0_26_25 [2] */
   5700		FN_A4, FN_MSIOF0_TXD_B,
   5701		0, 0,
   5702		/* IP0_24_23 [2] */
   5703		FN_A3, FN_MSIOF0_SS2_B,
   5704		0, 0,
   5705		/* IP0_22_21 [2] */
   5706		FN_A2, FN_MSIOF0_SS1_B,
   5707		0, 0,
   5708		/* IP0_20_19 [2] */
   5709		FN_A1, FN_MSIOF0_SYNC_B,
   5710		0, 0,
   5711		/* IP0_18_16 [3] */
   5712		FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
   5713		0, 0, 0,
   5714		/* IP0_15 [1] */
   5715		FN_D15, 0,
   5716		/* IP0_14 [1] */
   5717		FN_D14, 0,
   5718		/* IP0_13 [1] */
   5719		FN_D13, 0,
   5720		/* IP0_12 [1] */
   5721		FN_D12, 0,
   5722		/* IP0_11 [1] */
   5723		FN_D11, 0,
   5724		/* IP0_10 [1] */
   5725		FN_D10, 0,
   5726		/* IP0_9 [1] */
   5727		FN_D9, 0,
   5728		/* IP0_8 [1] */
   5729		FN_D8, 0,
   5730		/* IP0_7 [1] */
   5731		FN_D7, 0,
   5732		/* IP0_6 [1] */
   5733		FN_D6, 0,
   5734		/* IP0_5 [1] */
   5735		FN_D5, 0,
   5736		/* IP0_4 [1] */
   5737		FN_D4, 0,
   5738		/* IP0_3 [1] */
   5739		FN_D3, 0,
   5740		/* IP0_2 [1] */
   5741		FN_D2, 0,
   5742		/* IP0_1 [1] */
   5743		FN_D1, 0,
   5744		/* IP0_0 [1] */
   5745		FN_D0, 0, ))
   5746	},
   5747	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
   5748			     GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
   5749			     GROUP(
   5750		/* IP1_31_29 [3] */
   5751		FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
   5752		0, 0, 0,
   5753		/* IP1_28_26 [3] */
   5754		FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
   5755		0, 0, 0, 0,
   5756		/* IP1_25_23 [3] */
   5757		FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
   5758		0, 0, 0,
   5759		/* IP1_22_20 [3] */
   5760		FN_A15, FN_BPFCLK_C,
   5761		0, 0, 0, 0, 0, 0,
   5762		/* IP1_19_17 [3] */
   5763		FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
   5764		0, 0, 0,
   5765		/* IP1_16_14 [3] */
   5766		FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
   5767		0, 0, 0, 0,
   5768		/* IP1_13_11 [3] */
   5769		FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
   5770		0, 0, 0, 0,
   5771		/* IP1_10_8 [3] */
   5772		FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
   5773		0, 0, 0, 0,
   5774		/* IP1_7_6 [2] */
   5775		FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
   5776		/* IP1_5_4 [2] */
   5777		FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
   5778		/* IP1_3_2 [2] */
   5779		FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
   5780		/* IP1_1_0 [2] */
   5781		FN_A7, FN_MSIOF1_SYNC,
   5782		0, 0, ))
   5783	},
   5784	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
   5785			     GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
   5786			     GROUP(
   5787		/* IP2_31_30 [2] RESERVED */
   5788		/* IP2_29_27 [3] */
   5789		FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
   5790		FN_ATAG0_N, 0, FN_EX_WAIT1,
   5791		0, 0,
   5792		/* IP2_26_25 [2] */
   5793		FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
   5794		/* IP2_24_23 [2] */
   5795		FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
   5796		/* IP2_22_21 [2] */
   5797		FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
   5798		/* IP2_20_19 [2] */
   5799		FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
   5800		/* IP2_18_16 [3] */
   5801		FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
   5802		0, 0,
   5803		/* IP2_15_13 [3] */
   5804		FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
   5805		0, 0, 0,
   5806		/* IP2_12_10 [3] */
   5807		FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
   5808		0, 0, 0,
   5809		/* IP2_9_7 [3] */
   5810		FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
   5811		0, 0, 0,
   5812		/* IP2_6_5 [2] */
   5813		FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
   5814		/* IP2_4_3 [2] */
   5815		FN_A20, FN_SPCLK, 0, 0,
   5816		/* IP2_2_0 [3] */
   5817		FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
   5818		FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
   5819	},
   5820	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
   5821			     GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
   5822			     GROUP(
   5823		/* IP3_31 [1] RESERVED */
   5824		/* IP3_30_28 [3] */
   5825		FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
   5826		FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
   5827		0, 0, 0,
   5828		/* IP3_27_25 [3] */
   5829		FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
   5830		FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
   5831		0, 0, 0,
   5832		/* IP3_24_22 [3] */
   5833		FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
   5834		FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
   5835		/* IP3_21_20 [2] */
   5836		FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
   5837		/* IP3_19_18 [2] */
   5838		FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
   5839		/* IP3_17_16 [2] */
   5840		FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
   5841		/* IP3_15_14 [2] */
   5842		FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
   5843		/* IP3_13_12 [2] */
   5844		FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
   5845		/* IP3_11_9 [3] */
   5846		FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
   5847		0, 0, 0,
   5848		/* IP3_8_6 [3] */
   5849		FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
   5850		FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
   5851		/* IP3_5_3 [3] */
   5852		FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
   5853		FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
   5854		/* IP3_2_0 [3] */
   5855		FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
   5856		0, 0, 0, ))
   5857	},
   5858	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
   5859			     GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
   5860				   3, 3, 2),
   5861			     GROUP(
   5862		/* IP4_31 [1] RESERVED */
   5863		/* IP4_30_28 [3] */
   5864		FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
   5865		FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
   5866		0, 0,
   5867		/* IP4_27_26 [2] */
   5868		FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
   5869		/* IP4_25_24 [2] */
   5870		FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
   5871		/* IP4_23_22 [2] */
   5872		FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
   5873		/* IP4_21 [1] */
   5874		FN_SSI_SDATA3, 0,
   5875		/* IP4_20 [1] */
   5876		FN_SSI_WS34, 0,
   5877		/* IP4_19 [1] */
   5878		FN_SSI_SCK34, 0,
   5879		/* IP4_18_16 [3] */
   5880		FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
   5881		0, 0, 0, 0,
   5882		/* IP4_15_13 [3] */
   5883		FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
   5884		FN_GLO_Q1_D, FN_HCTS1_N_E,
   5885		0, 0,
   5886		/* IP4_12_10 [3] */
   5887		FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
   5888		0, 0, 0,
   5889		/* IP4_9_8 [2] */
   5890		FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
   5891		/* IP4_7_5 [3] */
   5892		FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
   5893		FN_GLO_I1_D, 0, 0, 0,
   5894		/* IP4_4_2 [3] */
   5895		FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
   5896		FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
   5897		0, 0, 0,
   5898		/* IP4_1_0 [2] */
   5899		FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
   5900		))
   5901	},
   5902	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
   5903			     GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
   5904			     GROUP(
   5905		/* IP5_31_29 [3] */
   5906		FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
   5907		0, 0, 0, 0, 0,
   5908		/* IP5_28_26 [3] */
   5909		FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
   5910		0, 0, 0, 0,
   5911		/* IP5_25_24 [2] */
   5912		FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
   5913		/* IP5_23_22 [2] */
   5914		FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
   5915		/* IP5_21_20 [2] */
   5916		FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
   5917		/* IP5_19_17 [3] */
   5918		FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
   5919		0, 0, 0, 0,
   5920		/* IP5_16_15 [2] */
   5921		FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
   5922		/* IP5_14_12 [3] */
   5923		FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
   5924		0, 0, 0, 0,
   5925		/* IP5_11_9 [3] */
   5926		FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
   5927		0, 0, 0, 0,
   5928		/* IP5_8_6 [3] */
   5929		FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
   5930		FN_MSIOF2_RXD_D, FN_VI1_R5_B,
   5931		0, 0,
   5932		/* IP5_5_3 [3] */
   5933		FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
   5934		FN_MSIOF2_SS1_D, FN_VI1_R4_B,
   5935		0, 0,
   5936		/* IP5_2_0 [3] */
   5937		FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
   5938		FN_MSIOF2_TXD_D, FN_VI1_R3_B,
   5939		0, 0, ))
   5940	},
   5941	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
   5942			     GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
   5943			     GROUP(
   5944		/* IP6_31_30 [2] RESERVED */
   5945		/* IP6_29_27 [3] */
   5946		FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
   5947		FN_GPS_SIGN_C, FN_GPS_SIGN_D,
   5948		0, 0, 0,
   5949		/* IP6_26_24 [3] */
   5950		FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
   5951		FN_GPS_CLK_C, FN_GPS_CLK_D,
   5952		0, 0, 0,
   5953		/* IP6_23_21 [3] */
   5954		FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
   5955		FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
   5956		0, 0, 0,
   5957		/* IP6_20_19 [2] */
   5958		FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
   5959		/* IP6_18_16 [3] */
   5960		FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
   5961		0, 0, 0, 0,
   5962		/* IP6_15_14 [2] */
   5963		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
   5964		/* IP6_13_12 [2] */
   5965		FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
   5966		/* IP6_11_10 [2] */
   5967		FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
   5968		/* IP6_9_8 [2] */
   5969		FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
   5970		/* IP6_7_6 [2] */
   5971		FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
   5972		/* IP6_5_3 [3] */
   5973		FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
   5974		FN_SCIFA2_RXD, FN_FMIN_E,
   5975		0, 0,
   5976		/* IP6_2_0 [3] */
   5977		FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
   5978		FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
   5979		0, 0, ))
   5980	},
   5981	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
   5982			     GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
   5983			     GROUP(
   5984		/* IP7_31_30 [2] RESERVED */
   5985		/* IP7_29_27 [3] */
   5986		FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
   5987		FN_SCIFA1_SCK, FN_SSI_SCK78_B,
   5988		0, 0,
   5989		/* IP7_26_24 [3] */
   5990		FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
   5991		FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
   5992		0, 0,
   5993		/* IP7_23_21 [3] */
   5994		FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
   5995		FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
   5996		0, 0,
   5997		/* IP7_20_19 [2] */
   5998		FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
   5999		/* IP7_18_17 [2] */
   6000		FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
   6001		/* IP7_16_15 [2] */
   6002		FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
   6003		/* IP7_14_13 [2] */
   6004		FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
   6005		/* IP7_12_11 [2] */
   6006		FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
   6007		/* IP7_10_9 [2] */
   6008		FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
   6009		/* IP7_8_6 [3] */
   6010		FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
   6011		FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
   6012		0, 0,
   6013		/* IP7_5_3 [3] */
   6014		FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
   6015		FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
   6016		0, 0,
   6017		/* IP7_2_0 [3] */
   6018		FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
   6019		FN_SCIF_CLK_B, FN_GPS_MAG_D,
   6020		0, 0, ))
   6021	},
   6022	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
   6023			     GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
   6024			     GROUP(
   6025		/* IP8_31 [1] RESERVED */
   6026		/* IP8_30_28 [3] */
   6027		FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
   6028		0, 0, 0,
   6029		/* IP8_27_26 [2] */
   6030		FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
   6031		/* IP8_25_24 [2] */
   6032		FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
   6033		/* IP8_23_21 [3] */
   6034		FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
   6035		FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
   6036		0, 0,
   6037		/* IP8_20_18 [3] */
   6038		FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
   6039		FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
   6040		0, 0,
   6041		/* IP8_17_15 [3] */
   6042		FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
   6043		FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
   6044		0, 0,
   6045		/* IP8_14_12 [3] */
   6046		FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
   6047		FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
   6048		0, 0, 0,
   6049		/* IP8_11_9 [3] */
   6050		FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
   6051		FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
   6052		0, 0, 0,
   6053		/* IP8_8_6 [3] */
   6054		FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
   6055		FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
   6056		0, 0,
   6057		/* IP8_5_3 [3] */
   6058		FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
   6059		FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
   6060		0, 0,
   6061		/* IP8_2_0 [3] */
   6062		FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
   6063		0, 0, 0, ))
   6064	},
   6065	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
   6066			     GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
   6067				   1, 1, 3, 3),
   6068			     GROUP(
   6069		/* IP9_31_29 [3] */
   6070		FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
   6071		FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
   6072		/* IP9_28_27 [2] */
   6073		FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
   6074		/* IP9_26_25 [2] */
   6075		FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
   6076		/* IP9_24_23 [2] */
   6077		FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
   6078		/* IP9_22_21 [2] */
   6079		FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
   6080		/* IP9_20_19 [2] */
   6081		FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
   6082		/* IP9_18_17 [2] */
   6083		FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
   6084		/* IP9_16 [1] */
   6085		FN_DU1_DISP, FN_QPOLA,
   6086		/* IP9_15_13 [3] */
   6087		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
   6088		FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
   6089		0, 0, 0,
   6090		/* IP9_12 [1] */
   6091		FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
   6092		/* IP9_11 [1] */
   6093		FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
   6094		/* IP9_10_8 [3] */
   6095		FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
   6096		FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
   6097		0, 0,
   6098		/* IP9_7 [1] */
   6099		FN_DU1_DOTCLKOUT0, FN_QCLK,
   6100		/* IP9_6 [1] */
   6101		FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
   6102		/* IP9_5_3 [3] */
   6103		FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
   6104		FN_SCIF3_SCK, FN_SCIFA3_SCK,
   6105		0, 0, 0,
   6106		/* IP9_2_0 [3] */
   6107		FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
   6108		0, 0, 0, ))
   6109	},
   6110	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
   6111			     GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
   6112			     GROUP(
   6113		/* IP10_31_29 [3] */
   6114		FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
   6115		0, 0, 0,
   6116		/* IP10_28_27 [2] */
   6117		FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
   6118		/* IP10_26_25 [2] */
   6119		FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
   6120		/* IP10_24_22 [3] */
   6121		FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
   6122		0, 0, 0,
   6123		/* IP10_21_19 [3] */
   6124		FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
   6125		FN_TS_SDATA0_C, FN_ATACS11_N,
   6126		0, 0, 0,
   6127		/* IP10_18_17 [2] */
   6128		FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
   6129		/* IP10_16_15 [2] */
   6130		FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
   6131		/* IP10_14_12 [3] */
   6132		FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
   6133		FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
   6134		/* IP10_11_9 [3] */
   6135		FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
   6136		FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
   6137		0, 0,
   6138		/* IP10_8_6 [3] */
   6139		FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
   6140		FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
   6141		/* IP10_5_3 [3] */
   6142		FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
   6143		FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
   6144		/* IP10_2_0 [3] */
   6145		FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
   6146		FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
   6147	},
   6148	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
   6149			     GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
   6150				   2, 3, 3, 3, 3, 3),
   6151			     GROUP(
   6152		/* IP11_31_30 [2] */
   6153		FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
   6154		/* IP11_29_28 [2] */
   6155		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
   6156		/* IP11_27 [1] */
   6157		FN_VI1_DATA7, FN_AVB_MDC,
   6158		/* IP11_26 [1] */
   6159		FN_VI1_DATA6, FN_AVB_MAGIC,
   6160		/* IP11_25 [1] */
   6161		FN_VI1_DATA5, FN_AVB_RX_DV,
   6162		/* IP11_24 [1] */
   6163		FN_VI1_DATA4, FN_AVB_MDIO,
   6164		/* IP11_23 [1] */
   6165		FN_VI1_DATA3, FN_AVB_RX_ER,
   6166		/* IP11_22 [1] */
   6167		FN_VI1_DATA2, FN_AVB_RXD7,
   6168		/* IP11_21 [1] */
   6169		FN_VI1_DATA1, FN_AVB_RXD6,
   6170		/* IP11_20 [1] */
   6171		FN_VI1_DATA0, FN_AVB_RXD5,
   6172		/* IP11_19 [1] */
   6173		FN_VI1_CLK, FN_AVB_RXD4,
   6174		/* IP11_18_17 [2] */
   6175		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
   6176		/* IP11_16_15 [2] */
   6177		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
   6178		/* IP11_14_12 [3] */
   6179		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
   6180		FN_RX4_B, FN_SCIFA4_RXD_B,
   6181		0, 0, 0,
   6182		/* IP11_11_9 [3] */
   6183		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
   6184		FN_TX4_B, FN_SCIFA4_TXD_B,
   6185		0, 0, 0,
   6186		/* IP11_8_6 [3] */
   6187		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
   6188		FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
   6189		/* IP11_5_3 [3] */
   6190		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
   6191		0, 0, 0,
   6192		/* IP11_2_0 [3] */
   6193		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
   6194		FN_I2C1_SDA_D, 0, 0, 0, ))
   6195	},
   6196	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
   6197			     GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
   6198			     GROUP(
   6199		/* IP12_31_30 [2] RESERVED */
   6200		/* IP12_29_27 [3] */
   6201		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
   6202		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
   6203		0, 0, 0,
   6204		/* IP12_26_24 [3] */
   6205		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
   6206		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
   6207		0, 0, 0,
   6208		/* IP12_23_22 [2] */
   6209		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
   6210		/* IP12_21_20 [2] */
   6211		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
   6212		/* IP12_19_18 [2] */
   6213		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
   6214		/* IP12_17_16 [2] */
   6215		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
   6216		/* IP12_15_13 [3] */
   6217		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
   6218		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
   6219		0, 0, 0,
   6220		/* IP12_12_10 [3] */
   6221		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
   6222		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
   6223		0, 0, 0,
   6224		/* IP12_9_7 [3] */
   6225		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
   6226		FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
   6227		0, 0, 0,
   6228		/* IP12_6_4 [3] */
   6229		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
   6230		FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
   6231		0, 0, 0,
   6232		/* IP12_3_2 [2] */
   6233		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
   6234		/* IP12_1_0 [2] */
   6235		FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
   6236	},
   6237	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
   6238			     GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
   6239				   1, 1, 1, 3, 2, 2, 3),
   6240			     GROUP(
   6241		/* IP13_31 [1] RESERVED */
   6242		/* IP13_30_28 [3] */
   6243		FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
   6244		0, 0, 0, 0,
   6245		/* IP13_27 [1] */
   6246		FN_SD1_DATA3, FN_IERX_B,
   6247		/* IP13_26 [1] */
   6248		FN_SD1_DATA2, FN_IECLK_B,
   6249		/* IP13_25 [1] */
   6250		FN_SD1_DATA1, FN_IETX_B,
   6251		/* IP13_24_23 [2] */
   6252		FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
   6253		/* IP13_22 [1] */
   6254		FN_SD1_CMD, FN_REMOCON_B,
   6255		/* IP13_21_19 [3] */
   6256		FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
   6257		FN_SCIFA5_RXD_B, FN_RX3_C,
   6258		0, 0,
   6259		/* IP13_18_16 [3] */
   6260		FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
   6261		FN_SCIFA5_TXD_B, FN_TX3_C,
   6262		0, 0,
   6263		/* IP13_15 [1] */
   6264		FN_SD0_DATA3, FN_SSL_B,
   6265		/* IP13_14 [1] */
   6266		FN_SD0_DATA2, FN_IO3_B,
   6267		/* IP13_13 [1] */
   6268		FN_SD0_DATA1, FN_IO2_B,
   6269		/* IP13_12 [1] */
   6270		FN_SD0_DATA0, FN_MISO_IO1_B,
   6271		/* IP13_11 [1] */
   6272		FN_SD0_CMD, FN_MOSI_IO0_B,
   6273		/* IP13_10 [1] */
   6274		FN_SD0_CLK, FN_SPCLK_B,
   6275		/* IP13_9_7 [3] */
   6276		FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
   6277		FN_ADICHS2_B, FN_MSIOF0_TXD_C,
   6278		0, 0, 0,
   6279		/* IP13_6_5 [2] */
   6280		FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
   6281		/* IP13_4_3 [2] */
   6282		FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
   6283		/* IP13_2_0 [3] */
   6284		FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
   6285		FN_ADICLK_B, FN_MSIOF0_SS1_C,
   6286		0, 0, 0, ))
   6287	},
   6288	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
   6289			     GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
   6290				   1, 1, 2),
   6291			     GROUP(
   6292		/* IP14_31_29 [3] */
   6293		FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
   6294		FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
   6295		/* IP14_28_26 [3] */
   6296		FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
   6297		FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
   6298		/* IP14_25_23 [3] */
   6299		FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
   6300		0, 0, 0,
   6301		/* IP14_22_20 [3] */
   6302		FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
   6303		0, 0, 0,
   6304		/* IP14_19_17 [3] */
   6305		FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
   6306		FN_VI1_CLKENB_C, FN_VI1_G1_B,
   6307		0, 0,
   6308		/* IP14_16_14 [3] */
   6309		FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
   6310		FN_VI1_CLK_C, FN_VI1_G0_B,
   6311		0, 0,
   6312		/* IP14_13_11 [3] */
   6313		FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
   6314		0, 0, 0,
   6315		/* IP14_10_8 [3] */
   6316		FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
   6317		0, 0, 0,
   6318		/* IP14_7 [1] */
   6319		FN_SD2_DATA3, FN_MMC_D3,
   6320		/* IP14_6 [1] */
   6321		FN_SD2_DATA2, FN_MMC_D2,
   6322		/* IP14_5 [1] */
   6323		FN_SD2_DATA1, FN_MMC_D1,
   6324		/* IP14_4 [1] */
   6325		FN_SD2_DATA0, FN_MMC_D0,
   6326		/* IP14_3 [1] */
   6327		FN_SD2_CMD, FN_MMC_CMD,
   6328		/* IP14_2 [1] */
   6329		FN_SD2_CLK, FN_MMC_CLK,
   6330		/* IP14_1_0 [2] */
   6331		FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
   6332	},
   6333	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
   6334			     GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
   6335			     GROUP(
   6336		/* IP15_31_30 [2] RESERVED */
   6337		/* IP15_29_27 [3] */
   6338		FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
   6339		FN_CAN0_TX_B, FN_VI1_DATA5_C,
   6340		0, 0,
   6341		/* IP15_26_24 [3] */
   6342		FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
   6343		FN_CAN0_RX_B, FN_VI1_DATA4_C,
   6344		0, 0,
   6345		/* IP15_23_21 [3] */
   6346		FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
   6347		FN_TCLK2, FN_VI1_DATA3_C, 0,
   6348		/* IP15_20_18 [3] */
   6349		FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
   6350		0, 0, 0,
   6351		/* IP15_17_15 [3] */
   6352		FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
   6353		FN_TCLK1, FN_VI1_DATA1_C,
   6354		0, 0,
   6355		/* IP15_14_12 [3] */
   6356		FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
   6357		FN_VI1_G7_B, FN_SCIFA3_SCK_C,
   6358		0, 0,
   6359		/* IP15_11_9 [3] */
   6360		FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
   6361		FN_VI1_G6_B, FN_SCIFA3_RXD_C,
   6362		0, 0,
   6363		/* IP15_8_6 [3] */
   6364		FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
   6365		FN_PWM5_B, FN_SCIFA3_TXD_C,
   6366		0, 0, 0,
   6367		/* IP15_5_4 [2] */
   6368		FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
   6369		/* IP15_3_2 [2] */
   6370		FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
   6371		/* IP15_1_0 [2] */
   6372		FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
   6373	},
   6374	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
   6375			     GROUP(-20, 2, 2, 2, 3, 3),
   6376			     GROUP(
   6377		/* RESERVED [20] */
   6378		/* IP16_11_10 [2] */
   6379		FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
   6380		/* IP16_9_8 [2] */
   6381		FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
   6382		/* IP16_7_6 [2] */
   6383		FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
   6384		/* IP16_5_3 [3] */
   6385		FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
   6386		FN_GLO_SS_C, FN_VI1_DATA7_C,
   6387		0, 0, 0,
   6388		/* IP16_2_0 [3] */
   6389		FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
   6390		FN_GLO_SDATA_C, FN_VI1_DATA6_C,
   6391		0, 0, 0, ))
   6392	},
   6393	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
   6394			     GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2,
   6395				   2, -2, 1, 2, 2, 2),
   6396			     GROUP(
   6397		/* RESERVED [1] */
   6398		/* SEL_SCIF1 [2] */
   6399		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
   6400		/* SEL_SCIFB [2] */
   6401		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
   6402		/* SEL_SCIFB2 [2] */
   6403		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
   6404		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
   6405		/* SEL_SCIFB1 [3] */
   6406		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
   6407		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
   6408		0, 0, 0, 0,
   6409		/* SEL_SCIFA1 [2] */
   6410		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
   6411		/* SEL_SSI9 [1] */
   6412		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
   6413		/* SEL_SCFA [1] */
   6414		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
   6415		/* SEL_QSP [1] */
   6416		FN_SEL_QSP_0, FN_SEL_QSP_1,
   6417		/* SEL_SSI7 [1] */
   6418		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
   6419		/* SEL_HSCIF1 [3] */
   6420		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
   6421		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
   6422		0, 0, 0,
   6423		/* RESERVED [2] */
   6424		/* SEL_VI1 [2] */
   6425		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
   6426		/* RESERVED [2] */
   6427		/* SEL_TMU [1] */
   6428		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
   6429		/* SEL_LBS [2] */
   6430		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
   6431		/* SEL_TSIF0 [2] */
   6432		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
   6433		/* SEL_SOF0 [2] */
   6434		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
   6435	},
   6436	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
   6437			     GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2,
   6438				   -1, 2, 2, 2, 1, -1, 1),
   6439			     GROUP(
   6440		/* SEL_SCIF0 [3] */
   6441		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
   6442		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
   6443		0, 0, 0,
   6444		/* RESERVED [1] */
   6445		/* SEL_SCIF [1] */
   6446		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
   6447		/* SEL_CAN0 [3] */
   6448		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
   6449		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
   6450		0, 0,
   6451		/* SEL_CAN1 [2] */
   6452		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
   6453		/* RESERVED [1] */
   6454		/* SEL_SCIFA2 [1] */
   6455		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
   6456		/* SEL_SCIF4 [2] */
   6457		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
   6458		/* RESERVED [2] */
   6459		/* SEL_ADG [1] */
   6460		FN_SEL_ADG_0, FN_SEL_ADG_1,
   6461		/* SEL_FM [3] */
   6462		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
   6463		FN_SEL_FM_3, FN_SEL_FM_4,
   6464		0, 0, 0,
   6465		/* SEL_SCIFA5 [2] */
   6466		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
   6467		/* RESERVED [1] */
   6468		/* SEL_GPS [2] */
   6469		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
   6470		/* SEL_SCIFA4 [2] */
   6471		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
   6472		/* SEL_SCIFA3 [2] */
   6473		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
   6474		/* SEL_SIM [1] */
   6475		FN_SEL_SIM_0, FN_SEL_SIM_1,
   6476		/* RESERVED [1] */
   6477		/* SEL_SSI8 [1] */
   6478		FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
   6479	},
   6480	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
   6481			     GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2,
   6482				   3, 2, -5),
   6483			     GROUP(
   6484		/* SEL_HSCIF2 [2] */
   6485		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
   6486		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
   6487		/* SEL_CANCLK [2] */
   6488		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
   6489		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
   6490		/* SEL_IIC1 [2] */
   6491		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
   6492		/* SEL_IIC0 [2] */
   6493		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
   6494		/* SEL_I2C4 [2] */
   6495		FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
   6496		/* SEL_I2C3 [2] */
   6497		FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
   6498		/* SEL_SCIF3 [2] */
   6499		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
   6500		/* SEL_IEB [2] */
   6501		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
   6502		/* SEL_MMC [1] */
   6503		FN_SEL_MMC_0, FN_SEL_MMC_1,
   6504		/* SEL_SCIF5 [1] */
   6505		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
   6506		/* RESERVED [2] */
   6507		/* SEL_I2C2 [2] */
   6508		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
   6509		/* SEL_I2C1 [3] */
   6510		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
   6511		FN_SEL_I2C1_4,
   6512		0, 0, 0,
   6513		/* SEL_I2C0 [2] */
   6514		FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
   6515		/* RESERVED [5] */ ))
   6516	},
   6517	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
   6518			     GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1,
   6519				   1, 1, 2, -6),
   6520			     GROUP(
   6521		/* SEL_SOF1 [3] */
   6522		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
   6523		FN_SEL_SOF1_4,
   6524		0, 0, 0,
   6525		/* SEL_HSCIF0 [2] */
   6526		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
   6527		/* SEL_DIS [2] */
   6528		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
   6529		/* RESERVED [1] */
   6530		/* SEL_RAD [1] */
   6531		FN_SEL_RAD_0, FN_SEL_RAD_1,
   6532		/* SEL_RCN [1] */
   6533		FN_SEL_RCN_0, FN_SEL_RCN_1,
   6534		/* SEL_RSP [1] */
   6535		FN_SEL_RSP_0, FN_SEL_RSP_1,
   6536		/* SEL_SCIF2 [3] */
   6537		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
   6538		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
   6539		0, 0, 0,
   6540		/* RESERVED [2] */
   6541		/* RESERVED [2] */
   6542		/* SEL_SOF2 [3] */
   6543		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
   6544		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
   6545		0, 0, 0,
   6546		/* RESERVED [1] */
   6547		/* SEL_SSI1 [1] */
   6548		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
   6549		/* SEL_SSI0 [1] */
   6550		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
   6551		/* SEL_SSP [2] */
   6552		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
   6553		/* RESERVED [6] */ ))
   6554	},
   6555	{ },
   6556};
   6557
   6558static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
   6559{
   6560	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
   6561		return -EINVAL;
   6562
   6563	*pocctrl = 0xe606008c;
   6564
   6565	return 31 - (pin & 0x1f);
   6566}
   6567
   6568static const struct pinmux_bias_reg pinmux_bias_regs[] = {
   6569	{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
   6570		[ 0] = RCAR_GP_PIN(1,  4),	/* A20 */
   6571		[ 1] = RCAR_GP_PIN(1,  5),	/* A21 */
   6572		[ 2] = RCAR_GP_PIN(1,  6),	/* A22 */
   6573		[ 3] = RCAR_GP_PIN(1,  7),	/* A23 */
   6574		[ 4] = RCAR_GP_PIN(1,  8),	/* A24 */
   6575		[ 5] = RCAR_GP_PIN(6, 31),	/* DU0_DOTCLKIN */
   6576		[ 6] = RCAR_GP_PIN(0,  0),	/* D0 */
   6577		[ 7] = RCAR_GP_PIN(0,  1),	/* D1 */
   6578		[ 8] = RCAR_GP_PIN(0,  2),	/* D2 */
   6579		[ 9] = RCAR_GP_PIN(0,  3),	/* D3 */
   6580		[10] = RCAR_GP_PIN(0,  4),	/* D4 */
   6581		[11] = RCAR_GP_PIN(0,  5),	/* D5 */
   6582		[12] = RCAR_GP_PIN(0,  6),	/* D6 */
   6583		[13] = RCAR_GP_PIN(0,  7),	/* D7 */
   6584		[14] = RCAR_GP_PIN(0,  8),	/* D8 */
   6585		[15] = RCAR_GP_PIN(0,  9),	/* D9 */
   6586		[16] = RCAR_GP_PIN(0, 10),	/* D10 */
   6587		[17] = RCAR_GP_PIN(0, 11),	/* D11 */
   6588		[18] = RCAR_GP_PIN(0, 12),	/* D12 */
   6589		[19] = RCAR_GP_PIN(0, 13),	/* D13 */
   6590		[20] = RCAR_GP_PIN(0, 14),	/* D14 */
   6591		[21] = RCAR_GP_PIN(0, 15),	/* D15 */
   6592		[22] = RCAR_GP_PIN(0, 16),	/* A0 */
   6593		[23] = RCAR_GP_PIN(0, 17),	/* A1 */
   6594		[24] = RCAR_GP_PIN(0, 18),	/* A2 */
   6595		[25] = RCAR_GP_PIN(0, 19),	/* A3 */
   6596		[26] = RCAR_GP_PIN(0, 20),	/* A4 */
   6597		[27] = RCAR_GP_PIN(0, 21),	/* A5 */
   6598		[28] = RCAR_GP_PIN(0, 22),	/* A6 */
   6599		[29] = RCAR_GP_PIN(0, 23),	/* A7 */
   6600		[30] = RCAR_GP_PIN(0, 24),	/* A8 */
   6601		[31] = RCAR_GP_PIN(0, 25),	/* A9 */
   6602	} },
   6603	{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
   6604		[ 0] = RCAR_GP_PIN(0, 26),	/* A10 */
   6605		[ 1] = RCAR_GP_PIN(0, 27),	/* A11 */
   6606		[ 2] = RCAR_GP_PIN(0, 28),	/* A12 */
   6607		[ 3] = RCAR_GP_PIN(0, 29),	/* A13 */
   6608		[ 4] = RCAR_GP_PIN(0, 30),	/* A14 */
   6609		[ 5] = RCAR_GP_PIN(0, 31),	/* A15 */
   6610		[ 6] = RCAR_GP_PIN(1,  0),	/* A16 */
   6611		[ 7] = RCAR_GP_PIN(1,  1),	/* A17 */
   6612		[ 8] = RCAR_GP_PIN(1,  2),	/* A18 */
   6613		[ 9] = RCAR_GP_PIN(1,  3),	/* A19 */
   6614		[10] = PIN_TRST_N,		/* TRST# */
   6615		[11] = PIN_TCK,			/* TCK */
   6616		[12] = PIN_TMS,			/* TMS */
   6617		[13] = PIN_TDI,			/* TDI */
   6618		[14] = RCAR_GP_PIN(1, 11),	/* CS1#/A26 */
   6619		[15] = RCAR_GP_PIN(1, 12),	/* EX_CS0# */
   6620		[16] = RCAR_GP_PIN(1, 13),	/* EX_CS1# */
   6621		[17] = RCAR_GP_PIN(1, 14),	/* EX_CS2# */
   6622		[18] = RCAR_GP_PIN(1, 15),	/* EX_CS3# */
   6623		[19] = RCAR_GP_PIN(1, 16),	/* EX_CS4# */
   6624		[20] = RCAR_GP_PIN(1, 17),	/* EX_CS5# */
   6625		[21] = RCAR_GP_PIN(1, 18),	/* BS# */
   6626		[22] = RCAR_GP_PIN(1, 19),	/* RD# */
   6627		[23] = RCAR_GP_PIN(1, 20),	/* RD/WR# */
   6628		[24] = RCAR_GP_PIN(1, 21),	/* WE0# */
   6629		[25] = RCAR_GP_PIN(1, 22),	/* WE1# */
   6630		[26] = RCAR_GP_PIN(1, 23),	/* EX_WAIT0 */
   6631		[27] = RCAR_GP_PIN(1, 24),	/* DREQ0 */
   6632		[28] = RCAR_GP_PIN(1, 25),	/* DACK0 */
   6633		[29] = RCAR_GP_PIN(5, 31),	/* SPEEDIN */
   6634		[30] = RCAR_GP_PIN(2,  0),	/* SSI_SCK0129 */
   6635		[31] = RCAR_GP_PIN(2,  1),	/* SSI_WS0129 */
   6636	} },
   6637	{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
   6638		[ 0] = RCAR_GP_PIN(2,  2),	/* SSI_SDATA0 */
   6639		[ 1] = RCAR_GP_PIN(2,  3),	/* SSI_SCK1 */
   6640		[ 2] = RCAR_GP_PIN(2,  4),	/* SSI_WS1 */
   6641		[ 3] = RCAR_GP_PIN(2,  5),	/* SSI_SDATA1 */
   6642		[ 4] = RCAR_GP_PIN(2,  6),	/* SSI_SCK2 */
   6643		[ 5] = RCAR_GP_PIN(2,  7),	/* SSI_WS2 */
   6644		[ 6] = RCAR_GP_PIN(2,  8),	/* SSI_SDATA2 */
   6645		[ 7] = RCAR_GP_PIN(2,  9),	/* SSI_SCK34 */
   6646		[ 8] = RCAR_GP_PIN(2, 10),	/* SSI_WS34 */
   6647		[ 9] = RCAR_GP_PIN(2, 11),	/* SSI_SDATA3 */
   6648		[10] = RCAR_GP_PIN(2, 12),	/* SSI_SCK4 */
   6649		[11] = RCAR_GP_PIN(2, 13),	/* SSI_WS4 */
   6650		[12] = RCAR_GP_PIN(2, 14),	/* SSI_SDATA4 */
   6651		[13] = RCAR_GP_PIN(2, 15),	/* SSI_SCK5 */
   6652		[14] = RCAR_GP_PIN(2, 16),	/* SSI_WS5 */
   6653		[15] = RCAR_GP_PIN(2, 17),	/* SSI_SDATA5 */
   6654		[16] = RCAR_GP_PIN(2, 18),	/* SSI_SCK6 */
   6655		[17] = RCAR_GP_PIN(2, 19),	/* SSI_WS6 */
   6656		[18] = RCAR_GP_PIN(2, 20),	/* SSI_SDATA6 */
   6657		[19] = RCAR_GP_PIN(2, 21),	/* SSI_SCK78 */
   6658		[20] = RCAR_GP_PIN(2, 22),	/* SSI_WS78 */
   6659		[21] = RCAR_GP_PIN(2, 23),	/* SSI_SDATA7 */
   6660		[22] = RCAR_GP_PIN(2, 24),	/* SSI_SDATA8 */
   6661		[23] = RCAR_GP_PIN(2, 25),	/* SSI_SCK9 */
   6662		[24] = RCAR_GP_PIN(2, 26),	/* SSI_WS9 */
   6663		[25] = RCAR_GP_PIN(2, 27),	/* SSI_SDATA9 */
   6664		[26] = RCAR_GP_PIN(2, 28),	/* AUDIO_CLKA */
   6665		[27] = RCAR_GP_PIN(2, 29),	/* AUDIO_CLKB */
   6666		[28] = RCAR_GP_PIN(2, 30),	/* AUDIO_CLKC */
   6667		[29] = RCAR_GP_PIN(2, 31),	/* AUDIO_CLKOUT */
   6668		[30] = RCAR_GP_PIN(7, 10),	/* IRQ0 */
   6669		[31] = RCAR_GP_PIN(7, 11),	/* IRQ1 */
   6670	} },
   6671	{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
   6672		[ 0] = RCAR_GP_PIN(7, 12),	/* IRQ2 */
   6673		[ 1] = RCAR_GP_PIN(7, 13),	/* IRQ3 */
   6674		[ 2] = RCAR_GP_PIN(7, 14),	/* IRQ4 */
   6675		[ 3] = RCAR_GP_PIN(7, 15),	/* IRQ5 */
   6676		[ 4] = RCAR_GP_PIN(7, 16),	/* IRQ6 */
   6677		[ 5] = RCAR_GP_PIN(7, 17),	/* IRQ7 */
   6678		[ 6] = RCAR_GP_PIN(7, 18),	/* IRQ8 */
   6679		[ 7] = RCAR_GP_PIN(7, 19),	/* IRQ9 */
   6680		[ 8] = RCAR_GP_PIN(3,  0),	/* DU1_DR0 */
   6681		[ 9] = RCAR_GP_PIN(3,  1),	/* DU1_DR1 */
   6682		[10] = RCAR_GP_PIN(3,  2),	/* DU1_DR2 */
   6683		[11] = RCAR_GP_PIN(3,  3),	/* DU1_DR3 */
   6684		[12] = RCAR_GP_PIN(3,  4),	/* DU1_DR4 */
   6685		[13] = RCAR_GP_PIN(3,  5),	/* DU1_DR5 */
   6686		[14] = RCAR_GP_PIN(3,  6),	/* DU1_DR6 */
   6687		[15] = RCAR_GP_PIN(3,  7),	/* DU1_DR7 */
   6688		[16] = RCAR_GP_PIN(3,  8),	/* DU1_DG0 */
   6689		[17] = RCAR_GP_PIN(3,  9),	/* DU1_DG1 */
   6690		[18] = RCAR_GP_PIN(3, 10),	/* DU1_DG2 */
   6691		[19] = RCAR_GP_PIN(3, 11),	/* DU1_DG3 */
   6692		[20] = RCAR_GP_PIN(3, 12),	/* DU1_DG4 */
   6693		[21] = RCAR_GP_PIN(3, 13),	/* DU1_DG5 */
   6694		[22] = RCAR_GP_PIN(3, 14),	/* DU1_DG6 */
   6695		[23] = RCAR_GP_PIN(3, 15),	/* DU1_DG7 */
   6696		[24] = RCAR_GP_PIN(3, 16),	/* DU1_DB0 */
   6697		[25] = RCAR_GP_PIN(3, 17),	/* DU1_DB1 */
   6698		[26] = RCAR_GP_PIN(3, 18),	/* DU1_DB2 */
   6699		[27] = RCAR_GP_PIN(3, 19),	/* DU1_DB3 */
   6700		[28] = RCAR_GP_PIN(3, 20),	/* DU1_DB4 */
   6701		[29] = RCAR_GP_PIN(3, 21),	/* DU1_DB5 */
   6702		[30] = RCAR_GP_PIN(3, 22),	/* DU1_DB6 */
   6703		[31] = RCAR_GP_PIN(3, 23),	/* DU1_DB7 */
   6704	} },
   6705	{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
   6706		[ 0] = RCAR_GP_PIN(3, 24),	/* DU1_DOTCLKIN */
   6707		[ 1] = RCAR_GP_PIN(3, 25),	/* DU1_DOTCLKOUT0 */
   6708		[ 2] = RCAR_GP_PIN(3, 26),	/* DU1_DOTCLKOUT1 */
   6709		[ 3] = RCAR_GP_PIN(3, 27),	/* DU1_EXHSYNC_DU1_HSYNC */
   6710		[ 4] = RCAR_GP_PIN(3, 28),	/* DU1_EXVSYNC_DU1_VSYNC */
   6711		[ 5] = RCAR_GP_PIN(3, 29),	/* DU1_EXODDF_DU1_ODDF_DISP_CDE */
   6712		[ 6] = RCAR_GP_PIN(3, 30),	/* DU1_DISP */
   6713		[ 7] = RCAR_GP_PIN(3, 31),	/* DU1_CDE */
   6714		[ 8] = RCAR_GP_PIN(4,  0),	/* VI0_CLK */
   6715		[ 9] = RCAR_GP_PIN(4,  1),	/* VI0_CLKENB */
   6716		[10] = RCAR_GP_PIN(4,  2),	/* VI0_FIELD */
   6717		[11] = RCAR_GP_PIN(4,  3),	/* VI0_HSYNC# */
   6718		[12] = RCAR_GP_PIN(4,  4),	/* VI0_VSYNC# */
   6719		[13] = RCAR_GP_PIN(4,  5),	/* VI0_DATA0_VI0_B0 */
   6720		[14] = RCAR_GP_PIN(4,  6),	/* VI0_DATA1_VI0_B1 */
   6721		[15] = RCAR_GP_PIN(4,  7),	/* VI0_DATA2_VI0_B2 */
   6722		[16] = RCAR_GP_PIN(4,  8),	/* VI0_DATA3_VI0_B3 */
   6723		[17] = RCAR_GP_PIN(4,  9),	/* VI0_DATA4_VI0_B4 */
   6724		[18] = RCAR_GP_PIN(4, 10),	/* VI0_DATA5_VI0_B5 */
   6725		[19] = RCAR_GP_PIN(4, 11),	/* VI0_DATA6_VI0_B6 */
   6726		[20] = RCAR_GP_PIN(4, 12),	/* VI0_DATA7_VI0_B7 */
   6727		[21] = RCAR_GP_PIN(4, 13),	/* VI0_G0 */
   6728		[22] = RCAR_GP_PIN(4, 14),	/* VI0_G1 */
   6729		[23] = RCAR_GP_PIN(4, 15),	/* VI0_G2 */
   6730		[24] = RCAR_GP_PIN(4, 16),	/* VI0_G3 */
   6731		[25] = RCAR_GP_PIN(4, 17),	/* VI0_G4 */
   6732		[26] = RCAR_GP_PIN(4, 18),	/* VI0_G5 */
   6733		[27] = RCAR_GP_PIN(4, 19),	/* VI0_G6 */
   6734		[28] = RCAR_GP_PIN(4, 20),	/* VI0_G7 */
   6735		[29] = RCAR_GP_PIN(4, 21),	/* VI0_R0 */
   6736		[30] = RCAR_GP_PIN(4, 22),	/* VI0_R1 */
   6737		[31] = RCAR_GP_PIN(4, 23),	/* VI0_R2 */
   6738	} },
   6739	{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
   6740		[ 0] = RCAR_GP_PIN(4, 24),	/* VI0_R3 */
   6741		[ 1] = RCAR_GP_PIN(4, 25),	/* VI0_R4 */
   6742		[ 2] = RCAR_GP_PIN(4, 26),	/* VI0_R5 */
   6743		[ 3] = RCAR_GP_PIN(4, 27),	/* VI0_R6 */
   6744		[ 4] = RCAR_GP_PIN(4, 28),	/* VI0_R7 */
   6745		[ 5] = RCAR_GP_PIN(5,  0),	/* VI1_HSYNC# */
   6746		[ 6] = RCAR_GP_PIN(5,  1),	/* VI1_VSYNC# */
   6747		[ 7] = RCAR_GP_PIN(5,  2),	/* VI1_CLKENB */
   6748		[ 8] = RCAR_GP_PIN(5,  3),	/* VI1_FIELD */
   6749		[ 9] = RCAR_GP_PIN(5,  4),	/* VI1_CLK */
   6750		[10] = RCAR_GP_PIN(5,  5),	/* VI1_DATA0 */
   6751		[11] = RCAR_GP_PIN(5,  6),	/* VI1_DATA1 */
   6752		[12] = RCAR_GP_PIN(5,  7),	/* VI1_DATA2 */
   6753		[13] = RCAR_GP_PIN(5,  8),	/* VI1_DATA3 */
   6754		[14] = RCAR_GP_PIN(5,  9),	/* VI1_DATA4 */
   6755		[15] = RCAR_GP_PIN(5, 10),	/* VI1_DATA5 */
   6756		[16] = RCAR_GP_PIN(5, 11),	/* VI1_DATA6 */
   6757		[17] = RCAR_GP_PIN(5, 12),	/* VI1_DATA7 */
   6758		[18] = RCAR_GP_PIN(5, 13),	/* ETH_MDIO */
   6759		[19] = RCAR_GP_PIN(5, 14),	/* ETH_CRS_DV */
   6760		[20] = RCAR_GP_PIN(5, 15),	/* ETH_RX_ER */
   6761		[21] = RCAR_GP_PIN(5, 16),	/* ETH_RXD0 */
   6762		[22] = RCAR_GP_PIN(5, 17),	/* ETH_RXD1 */
   6763		[23] = RCAR_GP_PIN(5, 18),	/* ETH_LINK */
   6764		[24] = RCAR_GP_PIN(5, 19),	/* ETH_REFCLK */
   6765		[25] = RCAR_GP_PIN(5, 20),	/* ETH_TXD1 */
   6766		[26] = RCAR_GP_PIN(5, 21),	/* ETH_TX_EN */
   6767		[27] = RCAR_GP_PIN(5, 22),	/* ETH_MAGIC */
   6768		[28] = RCAR_GP_PIN(5, 23),	/* ETH_TXD0 */
   6769		[29] = RCAR_GP_PIN(5, 24),	/* ETH_MDC */
   6770		[30] = RCAR_GP_PIN(5, 25),	/* STP_IVCXO27_0 */
   6771		[31] = RCAR_GP_PIN(5, 26),	/* STP_ISCLK_0 */
   6772	} },
   6773	{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
   6774		[ 0] = RCAR_GP_PIN(5, 27),	/* STP_ISD_0 */
   6775		[ 1] = RCAR_GP_PIN(5, 28),	/* STP_ISEN_0 */
   6776		[ 2] = RCAR_GP_PIN(5, 29),	/* STP_ISSYNC_0 */
   6777		[ 3] = RCAR_GP_PIN(5, 30),	/* STP_OPWM_0 */
   6778		[ 4] = RCAR_GP_PIN(6,  0),	/* SD0_CLK */
   6779		[ 5] = RCAR_GP_PIN(6,  1),	/* SD0_CMD */
   6780		[ 6] = RCAR_GP_PIN(6,  2),	/* SD0_DATA0 */
   6781		[ 7] = RCAR_GP_PIN(6,  3),	/* SD0_DATA1 */
   6782		[ 8] = RCAR_GP_PIN(6,  4),	/* SD0_DATA2 */
   6783		[ 9] = RCAR_GP_PIN(6,  5),	/* SD0_DATA3 */
   6784		[10] = RCAR_GP_PIN(6,  6),	/* SD0_CD */
   6785		[11] = RCAR_GP_PIN(6,  7),	/* SD0_WP */
   6786		[12] = RCAR_GP_PIN(6,  8),	/* SD2_CLK */
   6787		[13] = RCAR_GP_PIN(6,  9),	/* SD2_CMD */
   6788		[14] = RCAR_GP_PIN(6, 10),	/* SD2_DATA0 */
   6789		[15] = RCAR_GP_PIN(6, 11),	/* SD2_DATA1 */
   6790		[16] = RCAR_GP_PIN(6, 12),	/* SD2_DATA2 */
   6791		[17] = RCAR_GP_PIN(6, 13),	/* SD2_DATA3 */
   6792		[18] = RCAR_GP_PIN(6, 14),	/* SD2_CD */
   6793		[19] = RCAR_GP_PIN(6, 15),	/* SD2_WP */
   6794		[20] = RCAR_GP_PIN(6, 16),	/* SD3_CLK */
   6795		[21] = RCAR_GP_PIN(6, 17),	/* SD3_CMD */
   6796		[22] = RCAR_GP_PIN(6, 18),	/* SD3_DATA0 */
   6797		[23] = RCAR_GP_PIN(6, 19),	/* SD3_DATA1 */
   6798		[24] = RCAR_GP_PIN(6, 20),	/* SD3_DATA2 */
   6799		[25] = RCAR_GP_PIN(6, 21),	/* SD3_DATA3 */
   6800		[26] = RCAR_GP_PIN(6, 22),	/* SD3_CD */
   6801		[27] = RCAR_GP_PIN(6, 23),	/* SD3_WP */
   6802		[28] = RCAR_GP_PIN(6, 24),	/* MSIOF0_SCK */
   6803		[29] = RCAR_GP_PIN(6, 25),	/* MSIOF0_SYNC */
   6804		[30] = RCAR_GP_PIN(6, 26),	/* MSIOF0_TXD */
   6805		[31] = RCAR_GP_PIN(6, 27),	/* MSIOF0_RXD */
   6806	} },
   6807	{ PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
   6808		/* PUPR7 pull-up pins */
   6809		[ 0] = RCAR_GP_PIN(6, 28),	/* MSIOF0_SS1 */
   6810		[ 1] = RCAR_GP_PIN(6, 29),	/* MSIOF0_SS2 */
   6811		[ 2] = RCAR_GP_PIN(4, 29),	/* SIM0_RST */
   6812		[ 3] = RCAR_GP_PIN(4, 30),	/* SIM0_CLK */
   6813		[ 4] = RCAR_GP_PIN(4, 31),	/* SIM0_D */
   6814		[ 5] = RCAR_GP_PIN(7, 20),	/* GPS_CLK */
   6815		[ 6] = RCAR_GP_PIN(7, 21),	/* GPS_SIGN */
   6816		[ 7] = RCAR_GP_PIN(7, 22),	/* GPS_MAG */
   6817		[ 8] = RCAR_GP_PIN(7,  0),	/* HCTS0# */
   6818		[ 9] = RCAR_GP_PIN(7,  1),	/* HRTS0# */
   6819		[10] = RCAR_GP_PIN(7,  2),	/* HSCK0 */
   6820		[11] = RCAR_GP_PIN(7,  3),	/* HRX0 */
   6821		[12] = RCAR_GP_PIN(7,  4),	/* HTX0 */
   6822		[13] = RCAR_GP_PIN(7,  5),	/* HRX1 */
   6823		[14] = RCAR_GP_PIN(7,  6),	/* HTX1 */
   6824		[15] = SH_PFC_PIN_NONE,
   6825		[16] = SH_PFC_PIN_NONE,
   6826		[17] = SH_PFC_PIN_NONE,
   6827		[18] = RCAR_GP_PIN(1,  9),	/* A25 */
   6828		[19] = SH_PFC_PIN_NONE,
   6829		[20] = RCAR_GP_PIN(1, 10),	/* CS0# */
   6830		[21] = RCAR_GP_PIN(7, 23),	/* USB0_PWEN */
   6831		[22] = RCAR_GP_PIN(7, 24),	/* USB0_OVC */
   6832		[23] = RCAR_GP_PIN(7, 25),	/* USB1_PWEN */
   6833		[24] = RCAR_GP_PIN(6, 30),	/* USB1_OVC */
   6834		[25] = PIN_AVS1,		/* AVS1 */
   6835		[26] = PIN_AVS2,		/* AVS2 */
   6836		[27] = SH_PFC_PIN_NONE,
   6837		[28] = SH_PFC_PIN_NONE,
   6838		[29] = SH_PFC_PIN_NONE,
   6839		[30] = SH_PFC_PIN_NONE,
   6840		[31] = SH_PFC_PIN_NONE,
   6841	} },
   6842	{ PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
   6843		/* PUPR7 pull-down pins */
   6844		[ 0] = SH_PFC_PIN_NONE,
   6845		[ 1] = SH_PFC_PIN_NONE,
   6846		[ 2] = SH_PFC_PIN_NONE,
   6847		[ 3] = SH_PFC_PIN_NONE,
   6848		[ 4] = SH_PFC_PIN_NONE,
   6849		[ 5] = SH_PFC_PIN_NONE,
   6850		[ 6] = SH_PFC_PIN_NONE,
   6851		[ 7] = SH_PFC_PIN_NONE,
   6852		[ 8] = SH_PFC_PIN_NONE,
   6853		[ 9] = SH_PFC_PIN_NONE,
   6854		[10] = SH_PFC_PIN_NONE,
   6855		[11] = SH_PFC_PIN_NONE,
   6856		[12] = SH_PFC_PIN_NONE,
   6857		[13] = SH_PFC_PIN_NONE,
   6858		[14] = SH_PFC_PIN_NONE,
   6859		[15] = SH_PFC_PIN_NONE,
   6860		[16] = SH_PFC_PIN_NONE,
   6861		[17] = SH_PFC_PIN_NONE,
   6862		[18] = SH_PFC_PIN_NONE,
   6863		[19] = PIN_ASEBRK_N_ACK,	/* ASEBRK#/ACK */
   6864		[20] = SH_PFC_PIN_NONE,
   6865		[21] = SH_PFC_PIN_NONE,
   6866		[22] = SH_PFC_PIN_NONE,
   6867		[23] = SH_PFC_PIN_NONE,
   6868		[24] = SH_PFC_PIN_NONE,
   6869		[25] = SH_PFC_PIN_NONE,
   6870		[26] = SH_PFC_PIN_NONE,
   6871		[27] = SH_PFC_PIN_NONE,
   6872		[28] = SH_PFC_PIN_NONE,
   6873		[29] = SH_PFC_PIN_NONE,
   6874		[30] = SH_PFC_PIN_NONE,
   6875		[31] = SH_PFC_PIN_NONE,
   6876	} },
   6877	{ /* sentinel */ },
   6878};
   6879
   6880static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
   6881	.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
   6882	.get_bias = rcar_pinmux_get_bias,
   6883	.set_bias = rcar_pinmux_set_bias,
   6884};
   6885
   6886#ifdef CONFIG_PINCTRL_PFC_R8A7743
   6887const struct sh_pfc_soc_info r8a7743_pinmux_info = {
   6888	.name = "r8a77430_pfc",
   6889	.ops = &r8a7791_pfc_ops,
   6890	.unlock_reg = 0xe6060000, /* PMMR */
   6891
   6892	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
   6893
   6894	.pins = pinmux_pins,
   6895	.nr_pins = ARRAY_SIZE(pinmux_pins),
   6896	.groups = pinmux_groups.common,
   6897	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
   6898	.functions = pinmux_functions.common,
   6899	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
   6900
   6901	.cfg_regs = pinmux_config_regs,
   6902	.bias_regs = pinmux_bias_regs,
   6903
   6904	.pinmux_data = pinmux_data,
   6905	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
   6906};
   6907#endif
   6908
   6909#ifdef CONFIG_PINCTRL_PFC_R8A7744
   6910const struct sh_pfc_soc_info r8a7744_pinmux_info = {
   6911	.name = "r8a77440_pfc",
   6912	.ops = &r8a7791_pfc_ops,
   6913	.unlock_reg = 0xe6060000, /* PMMR */
   6914
   6915	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
   6916
   6917	.pins = pinmux_pins,
   6918	.nr_pins = ARRAY_SIZE(pinmux_pins),
   6919	.groups = pinmux_groups.common,
   6920	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
   6921	.functions = pinmux_functions.common,
   6922	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
   6923
   6924	.cfg_regs = pinmux_config_regs,
   6925	.bias_regs = pinmux_bias_regs,
   6926
   6927	.pinmux_data = pinmux_data,
   6928	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
   6929};
   6930#endif
   6931
   6932#ifdef CONFIG_PINCTRL_PFC_R8A7791
   6933const struct sh_pfc_soc_info r8a7791_pinmux_info = {
   6934	.name = "r8a77910_pfc",
   6935	.ops = &r8a7791_pfc_ops,
   6936	.unlock_reg = 0xe6060000, /* PMMR */
   6937
   6938	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
   6939
   6940	.pins = pinmux_pins,
   6941	.nr_pins = ARRAY_SIZE(pinmux_pins),
   6942	.groups = pinmux_groups.common,
   6943	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
   6944		     ARRAY_SIZE(pinmux_groups.automotive),
   6945	.functions = pinmux_functions.common,
   6946	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
   6947			ARRAY_SIZE(pinmux_functions.automotive),
   6948
   6949	.cfg_regs = pinmux_config_regs,
   6950	.bias_regs = pinmux_bias_regs,
   6951
   6952	.pinmux_data = pinmux_data,
   6953	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
   6954};
   6955#endif
   6956
   6957#ifdef CONFIG_PINCTRL_PFC_R8A7793
   6958const struct sh_pfc_soc_info r8a7793_pinmux_info = {
   6959	.name = "r8a77930_pfc",
   6960	.ops = &r8a7791_pfc_ops,
   6961	.unlock_reg = 0xe6060000, /* PMMR */
   6962
   6963	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
   6964
   6965	.pins = pinmux_pins,
   6966	.nr_pins = ARRAY_SIZE(pinmux_pins),
   6967	.groups = pinmux_groups.common,
   6968	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
   6969		     ARRAY_SIZE(pinmux_groups.automotive),
   6970	.functions = pinmux_functions.common,
   6971	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
   6972			ARRAY_SIZE(pinmux_functions.automotive),
   6973
   6974	.cfg_regs = pinmux_config_regs,
   6975	.bias_regs = pinmux_bias_regs,
   6976
   6977	.pinmux_data = pinmux_data,
   6978	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
   6979};
   6980#endif