cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-sun8i-a83t-r.c (4396B)


      1/*
      2 * Allwinner A83T SoCs special pins pinctrl driver.
      3 *
      4 * Copyright (C) 2017 Chen-Yu Tsai
      5 * Chen-Yu Tsai <wens@csie.org>
      6 *
      7 * Based on pinctrl-sun50i-a64-r.c
      8 *
      9 * Copyright (C) 2016 Icenowy Zheng
     10 * Icenowy Zheng <icenowy@aosc.xyz>
     11 *
     12 * Copyright (C) 2014 Chen-Yu Tsai
     13 * Chen-Yu Tsai <wens@csie.org>
     14 *
     15 * Copyright (C) 2014 Boris Brezillon
     16 * Boris Brezillon <boris.brezillon@free-electrons.com>
     17 *
     18 * Copyright (C) 2014 Maxime Ripard
     19 * Maxime Ripard <maxime.ripard@free-electrons.com>
     20 *
     21 * This file is licensed under the terms of the GNU General Public
     22 * License version 2.  This program is licensed "as is" without any
     23 * warranty of any kind, whether express or implied.
     24 */
     25
     26#include <linux/of.h>
     27#include <linux/of_device.h>
     28#include <linux/pinctrl/pinctrl.h>
     29#include <linux/platform_device.h>
     30#include <linux/reset.h>
     31
     32#include "pinctrl-sunxi.h"
     33
     34static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
     35	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
     36		  SUNXI_FUNCTION(0x0, "gpio_in"),
     37		  SUNXI_FUNCTION(0x1, "gpio_out"),
     38		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
     39		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SCK */
     40		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
     41	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
     42		  SUNXI_FUNCTION(0x0, "gpio_in"),
     43		  SUNXI_FUNCTION(0x1, "gpio_out"),
     44		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
     45		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SDA */
     46		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
     47	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
     48		  SUNXI_FUNCTION(0x0, "gpio_in"),
     49		  SUNXI_FUNCTION(0x1, "gpio_out"),
     50		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
     51		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
     52	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
     53		  SUNXI_FUNCTION(0x0, "gpio_in"),
     54		  SUNXI_FUNCTION(0x1, "gpio_out"),
     55		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
     56		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
     57	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
     58		  SUNXI_FUNCTION(0x0, "gpio_in"),
     59		  SUNXI_FUNCTION(0x1, "gpio_out"),
     60		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* MS */
     61		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
     62	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
     63		  SUNXI_FUNCTION(0x0, "gpio_in"),
     64		  SUNXI_FUNCTION(0x1, "gpio_out"),
     65		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* CK */
     66		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
     67	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
     68		  SUNXI_FUNCTION(0x0, "gpio_in"),
     69		  SUNXI_FUNCTION(0x1, "gpio_out"),
     70		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* DO */
     71		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
     72	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
     73		  SUNXI_FUNCTION(0x0, "gpio_in"),
     74		  SUNXI_FUNCTION(0x1, "gpio_out"),
     75		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* DI */
     76		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
     77	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
     78		  SUNXI_FUNCTION(0x0, "gpio_in"),
     79		  SUNXI_FUNCTION(0x1, "gpio_out"),
     80		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SCK */
     81		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
     82	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
     83		  SUNXI_FUNCTION(0x0, "gpio_in"),
     84		  SUNXI_FUNCTION(0x1, "gpio_out"),
     85		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SDA */
     86		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
     87	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
     88		  SUNXI_FUNCTION(0x0, "gpio_in"),
     89		  SUNXI_FUNCTION(0x1, "gpio_out"),
     90		  SUNXI_FUNCTION(0x2, "s_pwm"),
     91		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
     92	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
     93		  SUNXI_FUNCTION(0x0, "gpio_in"),
     94		  SUNXI_FUNCTION(0x1, "gpio_out"),
     95		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
     96	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
     97		  SUNXI_FUNCTION(0x0, "gpio_in"),
     98		  SUNXI_FUNCTION(0x1, "gpio_out"),
     99		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
    100		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PL_EINT12 */
    101};
    102
    103static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = {
    104	.pins = sun8i_a83t_r_pins,
    105	.npins = ARRAY_SIZE(sun8i_a83t_r_pins),
    106	.pin_base = PL_BASE,
    107	.irq_banks = 1,
    108};
    109
    110static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev)
    111{
    112	return sunxi_pinctrl_init(pdev,
    113				  &sun8i_a83t_r_pinctrl_data);
    114}
    115
    116static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
    117	{ .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
    118	{}
    119};
    120
    121static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
    122	.probe	= sun8i_a83t_r_pinctrl_probe,
    123	.driver	= {
    124		.name		= "sun8i-a83t-r-pinctrl",
    125		.of_match_table	= sun8i_a83t_r_pinctrl_match,
    126	},
    127};
    128builtin_platform_driver(sun8i_a83t_r_pinctrl_driver);