cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcdbas.h (2807B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  dcdbas.h: Definitions for Dell Systems Management Base driver
      4 *
      5 *  Copyright (C) 1995-2005 Dell Inc.
      6 */
      7
      8#ifndef _DCDBAS_H_
      9#define _DCDBAS_H_
     10
     11#include <linux/device.h>
     12#include <linux/sysfs.h>
     13#include <linux/types.h>
     14
     15#define MAX_SMI_DATA_BUF_SIZE			(256 * 1024)
     16
     17#define HC_ACTION_NONE				(0)
     18#define HC_ACTION_HOST_CONTROL_POWEROFF		BIT(1)
     19#define HC_ACTION_HOST_CONTROL_POWERCYCLE	BIT(2)
     20
     21#define HC_SMITYPE_NONE				(0)
     22#define HC_SMITYPE_TYPE1			(1)
     23#define HC_SMITYPE_TYPE2			(2)
     24#define HC_SMITYPE_TYPE3			(3)
     25
     26#define ESM_APM_CMD				(0x0A0)
     27#define ESM_APM_POWER_CYCLE			(0x10)
     28#define ESM_STATUS_CMD_UNSUCCESSFUL		(-1)
     29
     30#define CMOS_BASE_PORT				(0x070)
     31#define CMOS_PAGE1_INDEX_PORT			(0)
     32#define CMOS_PAGE1_DATA_PORT			(1)
     33#define CMOS_PAGE2_INDEX_PORT_PIIX4		(2)
     34#define CMOS_PAGE2_DATA_PORT_PIIX4		(3)
     35#define PE1400_APM_CONTROL_PORT			(0x0B0)
     36#define PCAT_APM_CONTROL_PORT			(0x0B2)
     37#define PCAT_APM_STATUS_PORT			(0x0B3)
     38#define PE1300_CMOS_CMD_STRUCT_PTR		(0x38)
     39#define PE1400_CMOS_CMD_STRUCT_PTR		(0x70)
     40
     41#define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN	(14)
     42#define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM		(16)
     43
     44#define TIMEOUT_USEC_SHORT_SEMA_BLOCKING	(10000)
     45#define EXPIRED_TIMER				(0)
     46
     47#define SMI_CMD_MAGIC				(0x534D4931)
     48#define SMM_EPS_SIG				"$SCB"
     49
     50#define DCDBAS_DEV_ATTR_RW(_name) \
     51	DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
     52
     53#define DCDBAS_DEV_ATTR_RO(_name) \
     54	DEVICE_ATTR(_name,0400,_name##_show,NULL);
     55
     56#define DCDBAS_DEV_ATTR_WO(_name) \
     57	DEVICE_ATTR(_name,0200,NULL,_name##_store);
     58
     59#define DCDBAS_BIN_ATTR_RW(_name) \
     60struct bin_attribute bin_attr_##_name = { \
     61	.attr =  { .name = __stringify(_name), \
     62		   .mode = 0600 }, \
     63	.read =  _name##_read, \
     64	.write = _name##_write, \
     65}
     66
     67struct smi_cmd {
     68	__u32 magic;
     69	__u32 ebx;
     70	__u32 ecx;
     71	__u16 command_address;
     72	__u8 command_code;
     73	__u8 reserved;
     74	__u8 command_buffer[1];
     75} __attribute__ ((packed));
     76
     77struct apm_cmd {
     78	__u8 command;
     79	__s8 status;
     80	__u16 reserved;
     81	union {
     82		struct {
     83			__u8 parm[MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN];
     84		} __attribute__ ((packed)) shortreq;
     85
     86		struct {
     87			__u16 num_sg_entries;
     88			struct {
     89				__u32 size;
     90				__u64 addr;
     91			} __attribute__ ((packed))
     92			    sglist[MAX_SYSMGMT_LONGCMD_SGENTRY_NUM];
     93		} __attribute__ ((packed)) longreq;
     94	} __attribute__ ((packed)) parameters;
     95} __attribute__ ((packed));
     96
     97int dcdbas_smi_request(struct smi_cmd *smi_cmd);
     98
     99struct smm_eps_table {
    100	char smm_comm_buff_anchor[4];
    101	u8 length;
    102	u8 checksum;
    103	u8 version;
    104	u64 smm_comm_buff_addr;
    105	u64 num_of_4k_pages;
    106} __packed;
    107
    108struct smi_buffer {
    109	u8 *virt;
    110	unsigned long size;
    111	dma_addr_t dma;
    112};
    113
    114int dcdbas_smi_alloc(struct smi_buffer *smi_buffer, unsigned long size);
    115void dcdbas_smi_free(struct smi_buffer *smi_buffer);
    116
    117#endif /* _DCDBAS_H_ */
    118