cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ptp_idt82p33.h (2425B)

      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
      4 *
      5 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
      6 */
      7#ifndef PTP_IDT82P33_H
      8#define PTP_IDT82P33_H
      9
     10#include <linux/ktime.h>
     11#include <linux/mfd/idt82p33_reg.h>
     12#include <linux/regmap.h>
     13
     14#define FW_FILENAME	"idt82p33xxx.bin"
     15#define MAX_PHC_PLL	(2)
     16#define TOD_BYTE_COUNT	(10)
     17#define DCO_MAX_PPB     (92000)
     18#define MAX_MEASURMENT_COUNT	(5)
     19#define SNAP_THRESHOLD_NS	(10000)
     20#define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
     21#define DDCO_THRESHOLD_NS	(5)
     22#define IDT82P33_MAX_WRITE_COUNT	(512)
     23#define PEROUT_ENABLE_OUTPUT_MASK	(0xdeadbeef)
     24
     25#define PLLMASK_ADDR_HI	0xFF
     26#define PLLMASK_ADDR_LO	0xA5
     27
     28#define PLL0_OUTMASK_ADDR_HI	0xFF
     29#define PLL0_OUTMASK_ADDR_LO	0xB0
     30
     31#define PLL1_OUTMASK_ADDR_HI	0xFF
     32#define PLL1_OUTMASK_ADDR_LO	0xB2
     33
     34#define PLL2_OUTMASK_ADDR_HI	0xFF
     35#define PLL2_OUTMASK_ADDR_LO	0xB4
     36
     37#define PLL3_OUTMASK_ADDR_HI	0xFF
     38#define PLL3_OUTMASK_ADDR_LO	0xB6
     39
     40#define DEFAULT_PLL_MASK	(0x01)
     41#define DEFAULT_OUTPUT_MASK_PLL0	(0xc0)
     42#define DEFAULT_OUTPUT_MASK_PLL1	DEFAULT_OUTPUT_MASK_PLL0
     43
     44/**
     45 * @brief Maximum absolute value for write phase offset in femtoseconds
     46 */
     47#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
     48
     49/** @brief Phase offset resolution
     50 *
     51 *  DPLL phase offset = 10^15 fs / ( System Clock  * 2^13)
     52 *                    = 10^15 fs / ( 1638400000 * 2^23)
     53 *                    = 74.5058059692382 fs
     54 */
     55#define IDT_T0DPLL_PHASE_RESOL 74506
     56
     57/* PTP Hardware Clock interface */
     58struct idt82p33_channel {
     59	struct ptp_clock_info	caps;
     60	struct ptp_clock	*ptp_clock;
     61	struct idt82p33		*idt82p33;
     62	enum pll_mode		pll_mode;
     63	s32			current_freq_ppb;
     64	u8			output_mask;
     65	u16			dpll_tod_cnfg;
     66	u16			dpll_tod_trigger;
     67	u16			dpll_tod_sts;
     68	u16			dpll_mode_cnfg;
     69	u16			dpll_freq_cnfg;
     70	u16			dpll_phase_cnfg;
     71	u16			dpll_sync_cnfg;
     72	u16			dpll_input_mode_cnfg;
     73};
     74
     75struct idt82p33 {
     76	struct idt82p33_channel	channel[MAX_PHC_PLL];
     77	struct device		*dev;
     78	u8			pll_mask;
     79	/* Mutex to protect operations from being interrupted */
     80	struct mutex		*lock;
     81	struct regmap		*regmap;
     82	struct device		*mfd;
     83	/* Overhead calculation for adjtime */
     84	ktime_t			start_time;
     85	int			calculate_overhead_flag;
     86	s64			tod_write_overhead_ns;
     87};
     88
     89/* firmware interface */
     90struct idt82p33_fwrc {
     91	u8 hiaddr;
     92	u8 loaddr;
     93	u8 value;
     94	u8 reserved;
     95} __packed;
     96
     97#endif /* PTP_IDT82P33_H */