cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pwm-sprd.c (7950B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2019 Spreadtrum Communications Inc.
      4 */
      5
      6#include <linux/clk.h>
      7#include <linux/err.h>
      8#include <linux/io.h>
      9#include <linux/math64.h>
     10#include <linux/module.h>
     11#include <linux/platform_device.h>
     12#include <linux/pwm.h>
     13
     14#define SPRD_PWM_PRESCALE	0x0
     15#define SPRD_PWM_MOD		0x4
     16#define SPRD_PWM_DUTY		0x8
     17#define SPRD_PWM_ENABLE		0x18
     18
     19#define SPRD_PWM_MOD_MAX	GENMASK(7, 0)
     20#define SPRD_PWM_DUTY_MSK	GENMASK(15, 0)
     21#define SPRD_PWM_PRESCALE_MSK	GENMASK(7, 0)
     22#define SPRD_PWM_ENABLE_BIT	BIT(0)
     23
     24#define SPRD_PWM_CHN_NUM	4
     25#define SPRD_PWM_REGS_SHIFT	5
     26#define SPRD_PWM_CHN_CLKS_NUM	2
     27#define SPRD_PWM_CHN_OUTPUT_CLK	1
     28
     29struct sprd_pwm_chn {
     30	struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
     31	u32 clk_rate;
     32};
     33
     34struct sprd_pwm_chip {
     35	void __iomem *base;
     36	struct device *dev;
     37	struct pwm_chip chip;
     38	int num_pwms;
     39	struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
     40};
     41
     42/*
     43 * The list of clocks required by PWM channels, and each channel has 2 clocks:
     44 * enable clock and pwm clock.
     45 */
     46static const char * const sprd_pwm_clks[] = {
     47	"enable0", "pwm0",
     48	"enable1", "pwm1",
     49	"enable2", "pwm2",
     50	"enable3", "pwm3",
     51};
     52
     53static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
     54{
     55	u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
     56
     57	return readl_relaxed(spc->base + offset);
     58}
     59
     60static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
     61			   u32 reg, u32 val)
     62{
     63	u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
     64
     65	writel_relaxed(val, spc->base + offset);
     66}
     67
     68static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
     69			       struct pwm_state *state)
     70{
     71	struct sprd_pwm_chip *spc =
     72		container_of(chip, struct sprd_pwm_chip, chip);
     73	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
     74	u32 val, duty, prescale;
     75	u64 tmp;
     76	int ret;
     77
     78	/*
     79	 * The clocks to PWM channel has to be enabled first before
     80	 * reading to the registers.
     81	 */
     82	ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
     83	if (ret) {
     84		dev_err(spc->dev, "failed to enable pwm%u clocks\n",
     85			pwm->hwpwm);
     86		return;
     87	}
     88
     89	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
     90	if (val & SPRD_PWM_ENABLE_BIT)
     91		state->enabled = true;
     92	else
     93		state->enabled = false;
     94
     95	/*
     96	 * The hardware provides a counter that is feed by the source clock.
     97	 * The period length is (PRESCALE + 1) * MOD counter steps.
     98	 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
     99	 * Thus the period_ns and duty_ns calculation formula should be:
    100	 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
    101	 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
    102	 */
    103	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
    104	prescale = val & SPRD_PWM_PRESCALE_MSK;
    105	tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
    106	state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
    107
    108	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
    109	duty = val & SPRD_PWM_DUTY_MSK;
    110	tmp = (prescale + 1) * NSEC_PER_SEC * duty;
    111	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
    112
    113	/* Disable PWM clocks if the PWM channel is not in enable state. */
    114	if (!state->enabled)
    115		clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
    116}
    117
    118static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
    119			   int duty_ns, int period_ns)
    120{
    121	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
    122	u32 prescale, duty;
    123	u64 tmp;
    124
    125	/*
    126	 * The hardware provides a counter that is feed by the source clock.
    127	 * The period length is (PRESCALE + 1) * MOD counter steps.
    128	 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
    129	 *
    130	 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
    131	 * The value for PRESCALE is selected such that the resulting period
    132	 * gets the maximal length not bigger than the requested one with the
    133	 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
    134	 */
    135	duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
    136
    137	tmp = (u64)chn->clk_rate * period_ns;
    138	do_div(tmp, NSEC_PER_SEC);
    139	prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
    140	if (prescale > SPRD_PWM_PRESCALE_MSK)
    141		prescale = SPRD_PWM_PRESCALE_MSK;
    142
    143	/*
    144	 * Note: Writing DUTY triggers the hardware to actually apply the
    145	 * values written to MOD and DUTY to the output, so must keep writing
    146	 * DUTY last.
    147	 *
    148	 * The hardware can ensures that current running period is completed
    149	 * before changing a new configuration to avoid mixed settings.
    150	 */
    151	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
    152	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
    153	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
    154
    155	return 0;
    156}
    157
    158static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
    159			  const struct pwm_state *state)
    160{
    161	struct sprd_pwm_chip *spc =
    162		container_of(chip, struct sprd_pwm_chip, chip);
    163	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
    164	struct pwm_state *cstate = &pwm->state;
    165	int ret;
    166
    167	if (state->polarity != PWM_POLARITY_NORMAL)
    168		return -EINVAL;
    169
    170	if (state->enabled) {
    171		if (!cstate->enabled) {
    172			/*
    173			 * The clocks to PWM channel has to be enabled first
    174			 * before writing to the registers.
    175			 */
    176			ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
    177						      chn->clks);
    178			if (ret) {
    179				dev_err(spc->dev,
    180					"failed to enable pwm%u clocks\n",
    181					pwm->hwpwm);
    182				return ret;
    183			}
    184		}
    185
    186		ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
    187				      state->period);
    188		if (ret)
    189			return ret;
    190
    191		sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
    192	} else if (cstate->enabled) {
    193		/*
    194		 * Note: After setting SPRD_PWM_ENABLE to zero, the controller
    195		 * will not wait for current period to be completed, instead it
    196		 * will stop the PWM channel immediately.
    197		 */
    198		sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
    199
    200		clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
    201	}
    202
    203	return 0;
    204}
    205
    206static const struct pwm_ops sprd_pwm_ops = {
    207	.apply = sprd_pwm_apply,
    208	.get_state = sprd_pwm_get_state,
    209	.owner = THIS_MODULE,
    210};
    211
    212static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
    213{
    214	struct clk *clk_pwm;
    215	int ret, i;
    216
    217	for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
    218		struct sprd_pwm_chn *chn = &spc->chn[i];
    219		int j;
    220
    221		for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
    222			chn->clks[j].id =
    223				sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
    224
    225		ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
    226					chn->clks);
    227		if (ret) {
    228			if (ret == -ENOENT)
    229				break;
    230
    231			return dev_err_probe(spc->dev, ret,
    232					     "failed to get channel clocks\n");
    233		}
    234
    235		clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
    236		chn->clk_rate = clk_get_rate(clk_pwm);
    237	}
    238
    239	if (!i) {
    240		dev_err(spc->dev, "no available PWM channels\n");
    241		return -ENODEV;
    242	}
    243
    244	spc->num_pwms = i;
    245
    246	return 0;
    247}
    248
    249static int sprd_pwm_probe(struct platform_device *pdev)
    250{
    251	struct sprd_pwm_chip *spc;
    252	int ret;
    253
    254	spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
    255	if (!spc)
    256		return -ENOMEM;
    257
    258	spc->base = devm_platform_ioremap_resource(pdev, 0);
    259	if (IS_ERR(spc->base))
    260		return PTR_ERR(spc->base);
    261
    262	spc->dev = &pdev->dev;
    263	platform_set_drvdata(pdev, spc);
    264
    265	ret = sprd_pwm_clk_init(spc);
    266	if (ret)
    267		return ret;
    268
    269	spc->chip.dev = &pdev->dev;
    270	spc->chip.ops = &sprd_pwm_ops;
    271	spc->chip.npwm = spc->num_pwms;
    272
    273	ret = pwmchip_add(&spc->chip);
    274	if (ret)
    275		dev_err(&pdev->dev, "failed to add PWM chip\n");
    276
    277	return ret;
    278}
    279
    280static int sprd_pwm_remove(struct platform_device *pdev)
    281{
    282	struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
    283
    284	pwmchip_remove(&spc->chip);
    285
    286	return 0;
    287}
    288
    289static const struct of_device_id sprd_pwm_of_match[] = {
    290	{ .compatible = "sprd,ums512-pwm", },
    291	{ },
    292};
    293MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
    294
    295static struct platform_driver sprd_pwm_driver = {
    296	.driver = {
    297		.name = "sprd-pwm",
    298		.of_match_table = sprd_pwm_of_match,
    299	},
    300	.probe = sprd_pwm_probe,
    301	.remove = sprd_pwm_remove,
    302};
    303
    304module_platform_driver(sprd_pwm_driver);
    305
    306MODULE_DESCRIPTION("Spreadtrum PWM Driver");
    307MODULE_LICENSE("GPL v2");