ltc3589.c (13035B)
1// SPDX-License-Identifier: GPL-2.0 2// 3// Linear Technology LTC3589,LTC3589-1 regulator support 4// 5// Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix 6 7#include <linux/i2c.h> 8#include <linux/init.h> 9#include <linux/interrupt.h> 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/of.h> 13#include <linux/of_device.h> 14#include <linux/regmap.h> 15#include <linux/regulator/driver.h> 16#include <linux/regulator/of_regulator.h> 17 18#define DRIVER_NAME "ltc3589" 19 20#define LTC3589_IRQSTAT 0x02 21#define LTC3589_SCR1 0x07 22#define LTC3589_OVEN 0x10 23#define LTC3589_SCR2 0x12 24#define LTC3589_PGSTAT 0x13 25#define LTC3589_VCCR 0x20 26#define LTC3589_CLIRQ 0x21 27#define LTC3589_B1DTV1 0x23 28#define LTC3589_B1DTV2 0x24 29#define LTC3589_VRRCR 0x25 30#define LTC3589_B2DTV1 0x26 31#define LTC3589_B2DTV2 0x27 32#define LTC3589_B3DTV1 0x29 33#define LTC3589_B3DTV2 0x2a 34#define LTC3589_L2DTV1 0x32 35#define LTC3589_L2DTV2 0x33 36 37#define LTC3589_IRQSTAT_PGOOD_TIMEOUT BIT(3) 38#define LTC3589_IRQSTAT_UNDERVOLT_WARN BIT(4) 39#define LTC3589_IRQSTAT_UNDERVOLT_FAULT BIT(5) 40#define LTC3589_IRQSTAT_THERMAL_WARN BIT(6) 41#define LTC3589_IRQSTAT_THERMAL_FAULT BIT(7) 42 43#define LTC3589_OVEN_SW1 BIT(0) 44#define LTC3589_OVEN_SW2 BIT(1) 45#define LTC3589_OVEN_SW3 BIT(2) 46#define LTC3589_OVEN_BB_OUT BIT(3) 47#define LTC3589_OVEN_LDO2 BIT(4) 48#define LTC3589_OVEN_LDO3 BIT(5) 49#define LTC3589_OVEN_LDO4 BIT(6) 50#define LTC3589_OVEN_SW_CTRL BIT(7) 51 52#define LTC3589_VCCR_SW1_GO BIT(0) 53#define LTC3589_VCCR_SW2_GO BIT(2) 54#define LTC3589_VCCR_SW3_GO BIT(4) 55#define LTC3589_VCCR_LDO2_GO BIT(6) 56 57#define LTC3589_VRRCR_SW1_RAMP_MASK GENMASK(1, 0) 58#define LTC3589_VRRCR_SW2_RAMP_MASK GENMASK(3, 2) 59#define LTC3589_VRRCR_SW3_RAMP_MASK GENMASK(5, 4) 60#define LTC3589_VRRCR_LDO2_RAMP_MASK GENMASK(7, 6) 61 62enum ltc3589_variant { 63 LTC3589, 64 LTC3589_1, 65 LTC3589_2, 66}; 67 68enum ltc3589_reg { 69 LTC3589_SW1, 70 LTC3589_SW2, 71 LTC3589_SW3, 72 LTC3589_BB_OUT, 73 LTC3589_LDO1, 74 LTC3589_LDO2, 75 LTC3589_LDO3, 76 LTC3589_LDO4, 77 LTC3589_NUM_REGULATORS, 78}; 79 80struct ltc3589 { 81 struct regmap *regmap; 82 struct device *dev; 83 enum ltc3589_variant variant; 84 struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS]; 85 struct regulator_dev *regulators[LTC3589_NUM_REGULATORS]; 86}; 87 88static const int ltc3589_ldo4[] = { 89 2800000, 2500000, 1800000, 3300000, 90}; 91 92static const int ltc3589_12_ldo4[] = { 93 1200000, 1800000, 2500000, 3200000, 94}; 95 96static const unsigned int ltc3589_ramp_table[] = { 97 880, 1750, 3500, 7000 98}; 99 100static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV) 101{ 102 struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev); 103 int sel; 104 105 sel = regulator_map_voltage_linear(rdev, uV, uV); 106 if (sel < 0) 107 return sel; 108 109 /* DTV2 register follows right after the corresponding DTV1 register */ 110 return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1, 111 rdev->desc->vsel_mask, sel); 112} 113 114static int ltc3589_set_suspend_mode(struct regulator_dev *rdev, 115 unsigned int mode) 116{ 117 struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev); 118 int mask, bit = 0; 119 120 /* VCCR reference selects are right next to the VCCR go bits */ 121 mask = rdev->desc->apply_bit << 1; 122 123 if (mode == REGULATOR_MODE_STANDBY) 124 bit = mask; /* Select DTV2 */ 125 126 mask |= rdev->desc->apply_bit; 127 bit |= rdev->desc->apply_bit; 128 return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit); 129} 130 131/* SW1, SW2, SW3, LDO2 */ 132static const struct regulator_ops ltc3589_linear_regulator_ops = { 133 .enable = regulator_enable_regmap, 134 .disable = regulator_disable_regmap, 135 .is_enabled = regulator_is_enabled_regmap, 136 .list_voltage = regulator_list_voltage_linear, 137 .set_voltage_sel = regulator_set_voltage_sel_regmap, 138 .get_voltage_sel = regulator_get_voltage_sel_regmap, 139 .set_ramp_delay = regulator_set_ramp_delay_regmap, 140 .set_voltage_time_sel = regulator_set_voltage_time_sel, 141 .set_suspend_voltage = ltc3589_set_suspend_voltage, 142 .set_suspend_mode = ltc3589_set_suspend_mode, 143}; 144 145/* BB_OUT, LDO3 */ 146static const struct regulator_ops ltc3589_fixed_regulator_ops = { 147 .enable = regulator_enable_regmap, 148 .disable = regulator_disable_regmap, 149 .is_enabled = regulator_is_enabled_regmap, 150}; 151 152/* LDO1 */ 153static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = { 154}; 155 156/* LDO4 */ 157static const struct regulator_ops ltc3589_table_regulator_ops = { 158 .enable = regulator_enable_regmap, 159 .disable = regulator_disable_regmap, 160 .is_enabled = regulator_is_enabled_regmap, 161 .list_voltage = regulator_list_voltage_table, 162 .set_voltage_sel = regulator_set_voltage_sel_regmap, 163 .get_voltage_sel = regulator_get_voltage_sel_regmap, 164}; 165 166static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2) 167{ 168 uint64_t tmp; 169 170 if (uV == 0) 171 return 0; 172 173 tmp = (uint64_t)uV * r1; 174 do_div(tmp, r2); 175 return uV + (unsigned int)tmp; 176} 177 178static int ltc3589_of_parse_cb(struct device_node *np, 179 const struct regulator_desc *desc, 180 struct regulator_config *config) 181{ 182 struct ltc3589 *ltc3589 = config->driver_data; 183 struct regulator_desc *rdesc = <c3589->regulator_descs[desc->id]; 184 u32 r[2]; 185 int ret; 186 187 /* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */ 188 if (desc->id >= LTC3589_LDO3) 189 return 0; 190 191 ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2); 192 if (ret) { 193 dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n", 194 ret); 195 return ret; 196 } 197 198 if (!r[0] || !r[1]) 199 return 0; 200 201 rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]); 202 rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]); 203 rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]); 204 205 return 0; 206} 207 208#define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask) \ 209 [LTC3589_ ## _name] = { \ 210 .name = #_name, \ 211 .of_match = of_match_ptr(#_of_name), \ 212 .regulators_node = of_match_ptr("regulators"), \ 213 .of_parse_cb = ltc3589_of_parse_cb, \ 214 .n_voltages = (dtv_mask) + 1, \ 215 .fixed_uV = (dtv_mask) ? 0 : 800000, \ 216 .ops = <c3589_ ## _ops ## _regulator_ops, \ 217 .type = REGULATOR_VOLTAGE, \ 218 .id = LTC3589_ ## _name, \ 219 .owner = THIS_MODULE, \ 220 .vsel_reg = (dtv1_reg), \ 221 .vsel_mask = (dtv_mask), \ 222 .enable_reg = (en_bit) ? LTC3589_OVEN : 0, \ 223 .enable_mask = (en_bit), \ 224 } 225 226#define LTC3589_LINEAR_REG(_name, _of_name, _dtv1) \ 227 [LTC3589_ ## _name] = { \ 228 .name = #_name, \ 229 .of_match = of_match_ptr(#_of_name), \ 230 .regulators_node = of_match_ptr("regulators"), \ 231 .of_parse_cb = ltc3589_of_parse_cb, \ 232 .n_voltages = 32, \ 233 .min_uV = 362500, \ 234 .uV_step = 12500, \ 235 .ramp_delay = 1750, \ 236 .ops = <c3589_linear_regulator_ops, \ 237 .type = REGULATOR_VOLTAGE, \ 238 .id = LTC3589_ ## _name, \ 239 .owner = THIS_MODULE, \ 240 .vsel_reg = LTC3589_ ## _dtv1, \ 241 .vsel_mask = 0x1f, \ 242 .apply_reg = LTC3589_VCCR, \ 243 .apply_bit = LTC3589_VCCR_ ## _name ## _GO, \ 244 .enable_reg = LTC3589_OVEN, \ 245 .enable_mask = (LTC3589_OVEN_ ## _name), \ 246 .ramp_reg = LTC3589_VRRCR, \ 247 .ramp_mask = LTC3589_VRRCR_ ## _name ## _RAMP_MASK, \ 248 .ramp_delay_table = ltc3589_ramp_table, \ 249 .n_ramp_values = ARRAY_SIZE(ltc3589_ramp_table), \ 250 } 251 252 253#define LTC3589_FIXED_REG(_name, _of_name) \ 254 LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0) 255 256static const struct regulator_desc ltc3589_regulators[] = { 257 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1), 258 LTC3589_LINEAR_REG(SW2, sw2, B2DTV1), 259 LTC3589_LINEAR_REG(SW3, sw3, B3DTV1), 260 LTC3589_FIXED_REG(BB_OUT, bb-out), 261 LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0), 262 LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1), 263 LTC3589_FIXED_REG(LDO3, ldo3), 264 LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2, 0x60), 265}; 266 267static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg) 268{ 269 switch (reg) { 270 case LTC3589_IRQSTAT: 271 case LTC3589_SCR1: 272 case LTC3589_OVEN: 273 case LTC3589_SCR2: 274 case LTC3589_VCCR: 275 case LTC3589_CLIRQ: 276 case LTC3589_B1DTV1: 277 case LTC3589_B1DTV2: 278 case LTC3589_VRRCR: 279 case LTC3589_B2DTV1: 280 case LTC3589_B2DTV2: 281 case LTC3589_B3DTV1: 282 case LTC3589_B3DTV2: 283 case LTC3589_L2DTV1: 284 case LTC3589_L2DTV2: 285 return true; 286 } 287 return false; 288} 289 290static bool ltc3589_readable_reg(struct device *dev, unsigned int reg) 291{ 292 switch (reg) { 293 case LTC3589_IRQSTAT: 294 case LTC3589_SCR1: 295 case LTC3589_OVEN: 296 case LTC3589_SCR2: 297 case LTC3589_PGSTAT: 298 case LTC3589_VCCR: 299 case LTC3589_B1DTV1: 300 case LTC3589_B1DTV2: 301 case LTC3589_VRRCR: 302 case LTC3589_B2DTV1: 303 case LTC3589_B2DTV2: 304 case LTC3589_B3DTV1: 305 case LTC3589_B3DTV2: 306 case LTC3589_L2DTV1: 307 case LTC3589_L2DTV2: 308 return true; 309 } 310 return false; 311} 312 313static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg) 314{ 315 switch (reg) { 316 case LTC3589_IRQSTAT: 317 case LTC3589_PGSTAT: 318 case LTC3589_VCCR: 319 return true; 320 } 321 return false; 322} 323 324static const struct reg_default ltc3589_reg_defaults[] = { 325 { LTC3589_SCR1, 0x00 }, 326 { LTC3589_OVEN, 0x00 }, 327 { LTC3589_SCR2, 0x00 }, 328 { LTC3589_VCCR, 0x00 }, 329 { LTC3589_B1DTV1, 0x19 }, 330 { LTC3589_B1DTV2, 0x19 }, 331 { LTC3589_VRRCR, 0xff }, 332 { LTC3589_B2DTV1, 0x19 }, 333 { LTC3589_B2DTV2, 0x19 }, 334 { LTC3589_B3DTV1, 0x19 }, 335 { LTC3589_B3DTV2, 0x19 }, 336 { LTC3589_L2DTV1, 0x19 }, 337 { LTC3589_L2DTV2, 0x19 }, 338}; 339 340static const struct regmap_config ltc3589_regmap_config = { 341 .reg_bits = 8, 342 .val_bits = 8, 343 .writeable_reg = ltc3589_writeable_reg, 344 .readable_reg = ltc3589_readable_reg, 345 .volatile_reg = ltc3589_volatile_reg, 346 .max_register = LTC3589_L2DTV2, 347 .reg_defaults = ltc3589_reg_defaults, 348 .num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults), 349 .use_single_read = true, 350 .use_single_write = true, 351 .cache_type = REGCACHE_RBTREE, 352}; 353 354static irqreturn_t ltc3589_isr(int irq, void *dev_id) 355{ 356 struct ltc3589 *ltc3589 = dev_id; 357 unsigned int i, irqstat, event; 358 359 regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat); 360 361 if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) { 362 event = REGULATOR_EVENT_OVER_TEMP; 363 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) 364 regulator_notifier_call_chain(ltc3589->regulators[i], 365 event, NULL); 366 } 367 368 if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) { 369 event = REGULATOR_EVENT_UNDER_VOLTAGE; 370 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) 371 regulator_notifier_call_chain(ltc3589->regulators[i], 372 event, NULL); 373 } 374 375 /* Clear warning condition */ 376 regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0); 377 378 return IRQ_HANDLED; 379} 380 381static int ltc3589_probe(struct i2c_client *client, 382 const struct i2c_device_id *id) 383{ 384 struct device *dev = &client->dev; 385 struct regulator_desc *descs; 386 struct ltc3589 *ltc3589; 387 int i, ret; 388 389 ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL); 390 if (!ltc3589) 391 return -ENOMEM; 392 393 i2c_set_clientdata(client, ltc3589); 394 if (client->dev.of_node) 395 ltc3589->variant = (enum ltc3589_variant) 396 of_device_get_match_data(&client->dev); 397 else 398 ltc3589->variant = id->driver_data; 399 ltc3589->dev = dev; 400 401 descs = ltc3589->regulator_descs; 402 memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators)); 403 if (ltc3589->variant == LTC3589) { 404 descs[LTC3589_LDO3].fixed_uV = 1800000; 405 descs[LTC3589_LDO4].volt_table = ltc3589_ldo4; 406 } else { 407 descs[LTC3589_LDO3].fixed_uV = 2800000; 408 descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4; 409 } 410 411 ltc3589->regmap = devm_regmap_init_i2c(client, <c3589_regmap_config); 412 if (IS_ERR(ltc3589->regmap)) { 413 ret = PTR_ERR(ltc3589->regmap); 414 dev_err(dev, "failed to initialize regmap: %d\n", ret); 415 return ret; 416 } 417 418 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) { 419 struct regulator_desc *desc = <c3589->regulator_descs[i]; 420 struct regulator_config config = { }; 421 422 config.dev = dev; 423 config.driver_data = ltc3589; 424 425 ltc3589->regulators[i] = devm_regulator_register(dev, desc, 426 &config); 427 if (IS_ERR(ltc3589->regulators[i])) { 428 ret = PTR_ERR(ltc3589->regulators[i]); 429 dev_err(dev, "failed to register regulator %s: %d\n", 430 desc->name, ret); 431 return ret; 432 } 433 } 434 435 if (client->irq) { 436 ret = devm_request_threaded_irq(dev, client->irq, NULL, 437 ltc3589_isr, 438 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 439 client->name, ltc3589); 440 if (ret) { 441 dev_err(dev, "Failed to request IRQ: %d\n", ret); 442 return ret; 443 } 444 } 445 446 return 0; 447} 448 449static const struct i2c_device_id ltc3589_i2c_id[] = { 450 { "ltc3589", LTC3589 }, 451 { "ltc3589-1", LTC3589_1 }, 452 { "ltc3589-2", LTC3589_2 }, 453 { } 454}; 455MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id); 456 457static const struct of_device_id __maybe_unused ltc3589_of_match[] = { 458 { 459 .compatible = "lltc,ltc3589", 460 .data = (void *)LTC3589, 461 }, 462 { 463 .compatible = "lltc,ltc3589-1", 464 .data = (void *)LTC3589_1, 465 }, 466 { 467 .compatible = "lltc,ltc3589-2", 468 .data = (void *)LTC3589_2, 469 }, 470 { }, 471}; 472MODULE_DEVICE_TABLE(of, ltc3589_of_match); 473 474static struct i2c_driver ltc3589_driver = { 475 .driver = { 476 .name = DRIVER_NAME, 477 .of_match_table = of_match_ptr(ltc3589_of_match), 478 }, 479 .probe = ltc3589_probe, 480 .id_table = ltc3589_i2c_id, 481}; 482module_i2c_driver(ltc3589_driver); 483 484MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); 485MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)"); 486MODULE_LICENSE("GPL v2");