cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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rtc-ds1307.c (50885B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
      4 *
      5 *  Copyright (C) 2005 James Chapman (ds1337 core)
      6 *  Copyright (C) 2006 David Brownell
      7 *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
      8 *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
      9 */
     10
     11#include <linux/bcd.h>
     12#include <linux/i2c.h>
     13#include <linux/init.h>
     14#include <linux/mod_devicetable.h>
     15#include <linux/module.h>
     16#include <linux/property.h>
     17#include <linux/rtc/ds1307.h>
     18#include <linux/rtc.h>
     19#include <linux/slab.h>
     20#include <linux/string.h>
     21#include <linux/hwmon.h>
     22#include <linux/hwmon-sysfs.h>
     23#include <linux/clk-provider.h>
     24#include <linux/regmap.h>
     25#include <linux/watchdog.h>
     26
     27/*
     28 * We can't determine type by probing, but if we expect pre-Linux code
     29 * to have set the chip up as a clock (turning on the oscillator and
     30 * setting the date and time), Linux can ignore the non-clock features.
     31 * That's a natural job for a factory or repair bench.
     32 */
     33enum ds_type {
     34	unknown_ds_type, /* always first and 0 */
     35	ds_1307,
     36	ds_1308,
     37	ds_1337,
     38	ds_1338,
     39	ds_1339,
     40	ds_1340,
     41	ds_1341,
     42	ds_1388,
     43	ds_3231,
     44	m41t0,
     45	m41t00,
     46	m41t11,
     47	mcp794xx,
     48	rx_8025,
     49	rx_8130,
     50	last_ds_type /* always last */
     51	/* rs5c372 too?  different address... */
     52};
     53
     54/* RTC registers don't differ much, except for the century flag */
     55#define DS1307_REG_SECS		0x00	/* 00-59 */
     56#	define DS1307_BIT_CH		0x80
     57#	define DS1340_BIT_nEOSC		0x80
     58#	define MCP794XX_BIT_ST		0x80
     59#define DS1307_REG_MIN		0x01	/* 00-59 */
     60#	define M41T0_BIT_OF		0x80
     61#define DS1307_REG_HOUR		0x02	/* 00-23, or 1-12{am,pm} */
     62#	define DS1307_BIT_12HR		0x40	/* in REG_HOUR */
     63#	define DS1307_BIT_PM		0x20	/* in REG_HOUR */
     64#	define DS1340_BIT_CENTURY_EN	0x80	/* in REG_HOUR */
     65#	define DS1340_BIT_CENTURY	0x40	/* in REG_HOUR */
     66#define DS1307_REG_WDAY		0x03	/* 01-07 */
     67#	define MCP794XX_BIT_VBATEN	0x08
     68#define DS1307_REG_MDAY		0x04	/* 01-31 */
     69#define DS1307_REG_MONTH	0x05	/* 01-12 */
     70#	define DS1337_BIT_CENTURY	0x80	/* in REG_MONTH */
     71#define DS1307_REG_YEAR		0x06	/* 00-99 */
     72
     73/*
     74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
     75 * start at 7, and they differ a LOT. Only control and status matter for
     76 * basic RTC date and time functionality; be careful using them.
     77 */
     78#define DS1307_REG_CONTROL	0x07		/* or ds1338 */
     79#	define DS1307_BIT_OUT		0x80
     80#	define DS1338_BIT_OSF		0x20
     81#	define DS1307_BIT_SQWE		0x10
     82#	define DS1307_BIT_RS1		0x02
     83#	define DS1307_BIT_RS0		0x01
     84#define DS1337_REG_CONTROL	0x0e
     85#	define DS1337_BIT_nEOSC		0x80
     86#	define DS1339_BIT_BBSQI		0x20
     87#	define DS3231_BIT_BBSQW		0x40 /* same as BBSQI */
     88#	define DS1337_BIT_RS2		0x10
     89#	define DS1337_BIT_RS1		0x08
     90#	define DS1337_BIT_INTCN		0x04
     91#	define DS1337_BIT_A2IE		0x02
     92#	define DS1337_BIT_A1IE		0x01
     93#define DS1340_REG_CONTROL	0x07
     94#	define DS1340_BIT_OUT		0x80
     95#	define DS1340_BIT_FT		0x40
     96#	define DS1340_BIT_CALIB_SIGN	0x20
     97#	define DS1340_M_CALIBRATION	0x1f
     98#define DS1340_REG_FLAG		0x09
     99#	define DS1340_BIT_OSF		0x80
    100#define DS1337_REG_STATUS	0x0f
    101#	define DS1337_BIT_OSF		0x80
    102#	define DS3231_BIT_EN32KHZ	0x08
    103#	define DS1337_BIT_A2I		0x02
    104#	define DS1337_BIT_A1I		0x01
    105#define DS1339_REG_ALARM1_SECS	0x07
    106
    107#define DS13XX_TRICKLE_CHARGER_MAGIC	0xa0
    108
    109#define RX8025_REG_CTRL1	0x0e
    110#	define RX8025_BIT_2412		0x20
    111#define RX8025_REG_CTRL2	0x0f
    112#	define RX8025_BIT_PON		0x10
    113#	define RX8025_BIT_VDET		0x40
    114#	define RX8025_BIT_XST		0x20
    115
    116#define RX8130_REG_ALARM_MIN		0x17
    117#define RX8130_REG_ALARM_HOUR		0x18
    118#define RX8130_REG_ALARM_WEEK_OR_DAY	0x19
    119#define RX8130_REG_EXTENSION		0x1c
    120#define RX8130_REG_EXTENSION_WADA	BIT(3)
    121#define RX8130_REG_FLAG			0x1d
    122#define RX8130_REG_FLAG_VLF		BIT(1)
    123#define RX8130_REG_FLAG_AF		BIT(3)
    124#define RX8130_REG_CONTROL0		0x1e
    125#define RX8130_REG_CONTROL0_AIE		BIT(3)
    126#define RX8130_REG_CONTROL1		0x1f
    127#define RX8130_REG_CONTROL1_INIEN	BIT(4)
    128#define RX8130_REG_CONTROL1_CHGEN	BIT(5)
    129
    130#define MCP794XX_REG_CONTROL		0x07
    131#	define MCP794XX_BIT_ALM0_EN	0x10
    132#	define MCP794XX_BIT_ALM1_EN	0x20
    133#define MCP794XX_REG_ALARM0_BASE	0x0a
    134#define MCP794XX_REG_ALARM0_CTRL	0x0d
    135#define MCP794XX_REG_ALARM1_BASE	0x11
    136#define MCP794XX_REG_ALARM1_CTRL	0x14
    137#	define MCP794XX_BIT_ALMX_IF	BIT(3)
    138#	define MCP794XX_BIT_ALMX_C0	BIT(4)
    139#	define MCP794XX_BIT_ALMX_C1	BIT(5)
    140#	define MCP794XX_BIT_ALMX_C2	BIT(6)
    141#	define MCP794XX_BIT_ALMX_POL	BIT(7)
    142#	define MCP794XX_MSK_ALMX_MATCH	(MCP794XX_BIT_ALMX_C0 | \
    143					 MCP794XX_BIT_ALMX_C1 | \
    144					 MCP794XX_BIT_ALMX_C2)
    145
    146#define M41TXX_REG_CONTROL	0x07
    147#	define M41TXX_BIT_OUT		BIT(7)
    148#	define M41TXX_BIT_FT		BIT(6)
    149#	define M41TXX_BIT_CALIB_SIGN	BIT(5)
    150#	define M41TXX_M_CALIBRATION	GENMASK(4, 0)
    151
    152#define DS1388_REG_WDOG_HUN_SECS	0x08
    153#define DS1388_REG_WDOG_SECS		0x09
    154#define DS1388_REG_FLAG			0x0b
    155#	define DS1388_BIT_WF		BIT(6)
    156#	define DS1388_BIT_OSF		BIT(7)
    157#define DS1388_REG_CONTROL		0x0c
    158#	define DS1388_BIT_RST		BIT(0)
    159#	define DS1388_BIT_WDE		BIT(1)
    160#	define DS1388_BIT_nEOSC		BIT(7)
    161
    162/* negative offset step is -2.034ppm */
    163#define M41TXX_NEG_OFFSET_STEP_PPB	2034
    164/* positive offset step is +4.068ppm */
    165#define M41TXX_POS_OFFSET_STEP_PPB	4068
    166/* Min and max values supported with 'offset' interface by M41TXX */
    167#define M41TXX_MIN_OFFSET	((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
    168#define M41TXX_MAX_OFFSET	((31) * M41TXX_POS_OFFSET_STEP_PPB)
    169
    170struct ds1307 {
    171	enum ds_type		type;
    172	struct device		*dev;
    173	struct regmap		*regmap;
    174	const char		*name;
    175	struct rtc_device	*rtc;
    176#ifdef CONFIG_COMMON_CLK
    177	struct clk_hw		clks[2];
    178#endif
    179};
    180
    181struct chip_desc {
    182	unsigned		alarm:1;
    183	u16			nvram_offset;
    184	u16			nvram_size;
    185	u8			offset; /* register's offset */
    186	u8			century_reg;
    187	u8			century_enable_bit;
    188	u8			century_bit;
    189	u8			bbsqi_bit;
    190	irq_handler_t		irq_handler;
    191	const struct rtc_class_ops *rtc_ops;
    192	u16			trickle_charger_reg;
    193	u8			(*do_trickle_setup)(struct ds1307 *, u32,
    194						    bool);
    195	/* Does the RTC require trickle-resistor-ohms to select the value of
    196	 * the resistor between Vcc and Vbackup?
    197	 */
    198	bool			requires_trickle_resistor;
    199	/* Some RTC's batteries and supercaps were charged by default, others
    200	 * allow charging but were not configured previously to do so.
    201	 * Remember this behavior to stay backwards compatible.
    202	 */
    203	bool			charge_default;
    204};
    205
    206static const struct chip_desc chips[last_ds_type];
    207
    208static int ds1307_get_time(struct device *dev, struct rtc_time *t)
    209{
    210	struct ds1307	*ds1307 = dev_get_drvdata(dev);
    211	int		tmp, ret;
    212	const struct chip_desc *chip = &chips[ds1307->type];
    213	u8 regs[7];
    214
    215	if (ds1307->type == rx_8130) {
    216		unsigned int regflag;
    217		ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
    218		if (ret) {
    219			dev_err(dev, "%s error %d\n", "read", ret);
    220			return ret;
    221		}
    222
    223		if (regflag & RX8130_REG_FLAG_VLF) {
    224			dev_warn_once(dev, "oscillator failed, set time!\n");
    225			return -EINVAL;
    226		}
    227	}
    228
    229	/* read the RTC date and time registers all at once */
    230	ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
    231			       sizeof(regs));
    232	if (ret) {
    233		dev_err(dev, "%s error %d\n", "read", ret);
    234		return ret;
    235	}
    236
    237	dev_dbg(dev, "%s: %7ph\n", "read", regs);
    238
    239	/* if oscillator fail bit is set, no data can be trusted */
    240	if (ds1307->type == m41t0 &&
    241	    regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
    242		dev_warn_once(dev, "oscillator failed, set time!\n");
    243		return -EINVAL;
    244	}
    245
    246	tmp = regs[DS1307_REG_SECS];
    247	switch (ds1307->type) {
    248	case ds_1307:
    249	case m41t0:
    250	case m41t00:
    251	case m41t11:
    252		if (tmp & DS1307_BIT_CH)
    253			return -EINVAL;
    254		break;
    255	case ds_1308:
    256	case ds_1338:
    257		if (tmp & DS1307_BIT_CH)
    258			return -EINVAL;
    259
    260		ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
    261		if (ret)
    262			return ret;
    263		if (tmp & DS1338_BIT_OSF)
    264			return -EINVAL;
    265		break;
    266	case ds_1340:
    267		if (tmp & DS1340_BIT_nEOSC)
    268			return -EINVAL;
    269
    270		ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
    271		if (ret)
    272			return ret;
    273		if (tmp & DS1340_BIT_OSF)
    274			return -EINVAL;
    275		break;
    276	case ds_1388:
    277		ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
    278		if (ret)
    279			return ret;
    280		if (tmp & DS1388_BIT_OSF)
    281			return -EINVAL;
    282		break;
    283	case mcp794xx:
    284		if (!(tmp & MCP794XX_BIT_ST))
    285			return -EINVAL;
    286
    287		break;
    288	default:
    289		break;
    290	}
    291
    292	t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
    293	t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
    294	tmp = regs[DS1307_REG_HOUR] & 0x3f;
    295	t->tm_hour = bcd2bin(tmp);
    296	/* rx8130 is bit position, not BCD */
    297	if (ds1307->type == rx_8130)
    298		t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
    299	else
    300		t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
    301	t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
    302	tmp = regs[DS1307_REG_MONTH] & 0x1f;
    303	t->tm_mon = bcd2bin(tmp) - 1;
    304	t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
    305
    306	if (regs[chip->century_reg] & chip->century_bit &&
    307	    IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
    308		t->tm_year += 100;
    309
    310	dev_dbg(dev, "%s secs=%d, mins=%d, "
    311		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
    312		"read", t->tm_sec, t->tm_min,
    313		t->tm_hour, t->tm_mday,
    314		t->tm_mon, t->tm_year, t->tm_wday);
    315
    316	return 0;
    317}
    318
    319static int ds1307_set_time(struct device *dev, struct rtc_time *t)
    320{
    321	struct ds1307	*ds1307 = dev_get_drvdata(dev);
    322	const struct chip_desc *chip = &chips[ds1307->type];
    323	int		result;
    324	int		tmp;
    325	u8		regs[7];
    326
    327	dev_dbg(dev, "%s secs=%d, mins=%d, "
    328		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
    329		"write", t->tm_sec, t->tm_min,
    330		t->tm_hour, t->tm_mday,
    331		t->tm_mon, t->tm_year, t->tm_wday);
    332
    333	if (t->tm_year < 100)
    334		return -EINVAL;
    335
    336#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
    337	if (t->tm_year > (chip->century_bit ? 299 : 199))
    338		return -EINVAL;
    339#else
    340	if (t->tm_year > 199)
    341		return -EINVAL;
    342#endif
    343
    344	regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
    345	regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
    346	regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
    347	/* rx8130 is bit position, not BCD */
    348	if (ds1307->type == rx_8130)
    349		regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
    350	else
    351		regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
    352	regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
    353	regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
    354
    355	/* assume 20YY not 19YY */
    356	tmp = t->tm_year - 100;
    357	regs[DS1307_REG_YEAR] = bin2bcd(tmp);
    358
    359	if (chip->century_enable_bit)
    360		regs[chip->century_reg] |= chip->century_enable_bit;
    361	if (t->tm_year > 199 && chip->century_bit)
    362		regs[chip->century_reg] |= chip->century_bit;
    363
    364	switch (ds1307->type) {
    365	case ds_1308:
    366	case ds_1338:
    367		regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
    368				   DS1338_BIT_OSF, 0);
    369		break;
    370	case ds_1340:
    371		regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
    372				   DS1340_BIT_OSF, 0);
    373		break;
    374	case ds_1388:
    375		regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
    376				   DS1388_BIT_OSF, 0);
    377		break;
    378	case mcp794xx:
    379		/*
    380		 * these bits were cleared when preparing the date/time
    381		 * values and need to be set again before writing the
    382		 * regsfer out to the device.
    383		 */
    384		regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
    385		regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
    386		break;
    387	default:
    388		break;
    389	}
    390
    391	dev_dbg(dev, "%s: %7ph\n", "write", regs);
    392
    393	result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
    394				   sizeof(regs));
    395	if (result) {
    396		dev_err(dev, "%s error %d\n", "write", result);
    397		return result;
    398	}
    399
    400	if (ds1307->type == rx_8130) {
    401		/* clear Voltage Loss Flag as data is available now */
    402		result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
    403				      ~(u8)RX8130_REG_FLAG_VLF);
    404		if (result) {
    405			dev_err(dev, "%s error %d\n", "write", result);
    406			return result;
    407		}
    408	}
    409
    410	return 0;
    411}
    412
    413static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
    414{
    415	struct ds1307		*ds1307 = dev_get_drvdata(dev);
    416	int			ret;
    417	u8			regs[9];
    418
    419	/* read all ALARM1, ALARM2, and status registers at once */
    420	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
    421			       regs, sizeof(regs));
    422	if (ret) {
    423		dev_err(dev, "%s error %d\n", "alarm read", ret);
    424		return ret;
    425	}
    426
    427	dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
    428		&regs[0], &regs[4], &regs[7]);
    429
    430	/*
    431	 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
    432	 * and that all four fields are checked matches
    433	 */
    434	t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
    435	t->time.tm_min = bcd2bin(regs[1] & 0x7f);
    436	t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
    437	t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
    438
    439	/* ... and status */
    440	t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
    441	t->pending = !!(regs[8] & DS1337_BIT_A1I);
    442
    443	dev_dbg(dev, "%s secs=%d, mins=%d, "
    444		"hours=%d, mday=%d, enabled=%d, pending=%d\n",
    445		"alarm read", t->time.tm_sec, t->time.tm_min,
    446		t->time.tm_hour, t->time.tm_mday,
    447		t->enabled, t->pending);
    448
    449	return 0;
    450}
    451
    452static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
    453{
    454	struct ds1307		*ds1307 = dev_get_drvdata(dev);
    455	unsigned char		regs[9];
    456	u8			control, status;
    457	int			ret;
    458
    459	dev_dbg(dev, "%s secs=%d, mins=%d, "
    460		"hours=%d, mday=%d, enabled=%d, pending=%d\n",
    461		"alarm set", t->time.tm_sec, t->time.tm_min,
    462		t->time.tm_hour, t->time.tm_mday,
    463		t->enabled, t->pending);
    464
    465	/* read current status of both alarms and the chip */
    466	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
    467			       sizeof(regs));
    468	if (ret) {
    469		dev_err(dev, "%s error %d\n", "alarm write", ret);
    470		return ret;
    471	}
    472	control = regs[7];
    473	status = regs[8];
    474
    475	dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
    476		&regs[0], &regs[4], control, status);
    477
    478	/* set ALARM1, using 24 hour and day-of-month modes */
    479	regs[0] = bin2bcd(t->time.tm_sec);
    480	regs[1] = bin2bcd(t->time.tm_min);
    481	regs[2] = bin2bcd(t->time.tm_hour);
    482	regs[3] = bin2bcd(t->time.tm_mday);
    483
    484	/* set ALARM2 to non-garbage */
    485	regs[4] = 0;
    486	regs[5] = 0;
    487	regs[6] = 0;
    488
    489	/* disable alarms */
    490	regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
    491	regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
    492
    493	ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
    494				sizeof(regs));
    495	if (ret) {
    496		dev_err(dev, "can't set alarm time\n");
    497		return ret;
    498	}
    499
    500	/* optionally enable ALARM1 */
    501	if (t->enabled) {
    502		dev_dbg(dev, "alarm IRQ armed\n");
    503		regs[7] |= DS1337_BIT_A1IE;	/* only ALARM1 is used */
    504		regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
    505	}
    506
    507	return 0;
    508}
    509
    510static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
    511{
    512	struct ds1307		*ds1307 = dev_get_drvdata(dev);
    513
    514	return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
    515				  DS1337_BIT_A1IE,
    516				  enabled ? DS1337_BIT_A1IE : 0);
    517}
    518
    519static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
    520{
    521	u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
    522		DS1307_TRICKLE_CHARGER_NO_DIODE;
    523
    524	setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
    525
    526	switch (ohms) {
    527	case 250:
    528		setup |= DS1307_TRICKLE_CHARGER_250_OHM;
    529		break;
    530	case 2000:
    531		setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
    532		break;
    533	case 4000:
    534		setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
    535		break;
    536	default:
    537		dev_warn(ds1307->dev,
    538			 "Unsupported ohm value %u in dt\n", ohms);
    539		return 0;
    540	}
    541	return setup;
    542}
    543
    544static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
    545{
    546	/* make sure that the backup battery is enabled */
    547	u8 setup = RX8130_REG_CONTROL1_INIEN;
    548	if (diode)
    549		setup |= RX8130_REG_CONTROL1_CHGEN;
    550
    551	return setup;
    552}
    553
    554static irqreturn_t rx8130_irq(int irq, void *dev_id)
    555{
    556	struct ds1307           *ds1307 = dev_id;
    557	u8 ctl[3];
    558	int ret;
    559
    560	rtc_lock(ds1307->rtc);
    561
    562	/* Read control registers. */
    563	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
    564			       sizeof(ctl));
    565	if (ret < 0)
    566		goto out;
    567	if (!(ctl[1] & RX8130_REG_FLAG_AF))
    568		goto out;
    569	ctl[1] &= ~RX8130_REG_FLAG_AF;
    570	ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
    571
    572	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
    573				sizeof(ctl));
    574	if (ret < 0)
    575		goto out;
    576
    577	rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
    578
    579out:
    580	rtc_unlock(ds1307->rtc);
    581
    582	return IRQ_HANDLED;
    583}
    584
    585static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
    586{
    587	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    588	u8 ald[3], ctl[3];
    589	int ret;
    590
    591	/* Read alarm registers. */
    592	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
    593			       sizeof(ald));
    594	if (ret < 0)
    595		return ret;
    596
    597	/* Read control registers. */
    598	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
    599			       sizeof(ctl));
    600	if (ret < 0)
    601		return ret;
    602
    603	t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
    604	t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
    605
    606	/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
    607	t->time.tm_sec = -1;
    608	t->time.tm_min = bcd2bin(ald[0] & 0x7f);
    609	t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
    610	t->time.tm_wday = -1;
    611	t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
    612	t->time.tm_mon = -1;
    613	t->time.tm_year = -1;
    614	t->time.tm_yday = -1;
    615	t->time.tm_isdst = -1;
    616
    617	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
    618		__func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
    619		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
    620
    621	return 0;
    622}
    623
    624static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
    625{
    626	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    627	u8 ald[3], ctl[3];
    628	int ret;
    629
    630	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
    631		"enabled=%d pending=%d\n", __func__,
    632		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
    633		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
    634		t->enabled, t->pending);
    635
    636	/* Read control registers. */
    637	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
    638			       sizeof(ctl));
    639	if (ret < 0)
    640		return ret;
    641
    642	ctl[0] &= RX8130_REG_EXTENSION_WADA;
    643	ctl[1] &= ~RX8130_REG_FLAG_AF;
    644	ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
    645
    646	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
    647				sizeof(ctl));
    648	if (ret < 0)
    649		return ret;
    650
    651	/* Hardware alarm precision is 1 minute! */
    652	ald[0] = bin2bcd(t->time.tm_min);
    653	ald[1] = bin2bcd(t->time.tm_hour);
    654	ald[2] = bin2bcd(t->time.tm_mday);
    655
    656	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
    657				sizeof(ald));
    658	if (ret < 0)
    659		return ret;
    660
    661	if (!t->enabled)
    662		return 0;
    663
    664	ctl[2] |= RX8130_REG_CONTROL0_AIE;
    665
    666	return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
    667}
    668
    669static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
    670{
    671	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    672	int ret, reg;
    673
    674	ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
    675	if (ret < 0)
    676		return ret;
    677
    678	if (enabled)
    679		reg |= RX8130_REG_CONTROL0_AIE;
    680	else
    681		reg &= ~RX8130_REG_CONTROL0_AIE;
    682
    683	return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
    684}
    685
    686static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
    687{
    688	struct ds1307           *ds1307 = dev_id;
    689	struct mutex            *lock = &ds1307->rtc->ops_lock;
    690	int reg, ret;
    691
    692	mutex_lock(lock);
    693
    694	/* Check and clear alarm 0 interrupt flag. */
    695	ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
    696	if (ret)
    697		goto out;
    698	if (!(reg & MCP794XX_BIT_ALMX_IF))
    699		goto out;
    700	reg &= ~MCP794XX_BIT_ALMX_IF;
    701	ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
    702	if (ret)
    703		goto out;
    704
    705	/* Disable alarm 0. */
    706	ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
    707				 MCP794XX_BIT_ALM0_EN, 0);
    708	if (ret)
    709		goto out;
    710
    711	rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
    712
    713out:
    714	mutex_unlock(lock);
    715
    716	return IRQ_HANDLED;
    717}
    718
    719static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
    720{
    721	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    722	u8 regs[10];
    723	int ret;
    724
    725	/* Read control and alarm 0 registers. */
    726	ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
    727			       sizeof(regs));
    728	if (ret)
    729		return ret;
    730
    731	t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
    732
    733	/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
    734	t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
    735	t->time.tm_min = bcd2bin(regs[4] & 0x7f);
    736	t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
    737	t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
    738	t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
    739	t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
    740	t->time.tm_year = -1;
    741	t->time.tm_yday = -1;
    742	t->time.tm_isdst = -1;
    743
    744	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
    745		"enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
    746		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
    747		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
    748		!!(regs[6] & MCP794XX_BIT_ALMX_POL),
    749		!!(regs[6] & MCP794XX_BIT_ALMX_IF),
    750		(regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
    751
    752	return 0;
    753}
    754
    755/*
    756 * We may have a random RTC weekday, therefore calculate alarm weekday based
    757 * on current weekday we read from the RTC timekeeping regs
    758 */
    759static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
    760{
    761	struct rtc_time tm_now;
    762	int days_now, days_alarm, ret;
    763
    764	ret = ds1307_get_time(dev, &tm_now);
    765	if (ret)
    766		return ret;
    767
    768	days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
    769	days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
    770
    771	return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
    772}
    773
    774static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
    775{
    776	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    777	unsigned char regs[10];
    778	int wday, ret;
    779
    780	wday = mcp794xx_alm_weekday(dev, &t->time);
    781	if (wday < 0)
    782		return wday;
    783
    784	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
    785		"enabled=%d pending=%d\n", __func__,
    786		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
    787		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
    788		t->enabled, t->pending);
    789
    790	/* Read control and alarm 0 registers. */
    791	ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
    792			       sizeof(regs));
    793	if (ret)
    794		return ret;
    795
    796	/* Set alarm 0, using 24-hour and day-of-month modes. */
    797	regs[3] = bin2bcd(t->time.tm_sec);
    798	regs[4] = bin2bcd(t->time.tm_min);
    799	regs[5] = bin2bcd(t->time.tm_hour);
    800	regs[6] = wday;
    801	regs[7] = bin2bcd(t->time.tm_mday);
    802	regs[8] = bin2bcd(t->time.tm_mon + 1);
    803
    804	/* Clear the alarm 0 interrupt flag. */
    805	regs[6] &= ~MCP794XX_BIT_ALMX_IF;
    806	/* Set alarm match: second, minute, hour, day, date, month. */
    807	regs[6] |= MCP794XX_MSK_ALMX_MATCH;
    808	/* Disable interrupt. We will not enable until completely programmed */
    809	regs[0] &= ~MCP794XX_BIT_ALM0_EN;
    810
    811	ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
    812				sizeof(regs));
    813	if (ret)
    814		return ret;
    815
    816	if (!t->enabled)
    817		return 0;
    818	regs[0] |= MCP794XX_BIT_ALM0_EN;
    819	return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
    820}
    821
    822static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
    823{
    824	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    825
    826	return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
    827				  MCP794XX_BIT_ALM0_EN,
    828				  enabled ? MCP794XX_BIT_ALM0_EN : 0);
    829}
    830
    831static int m41txx_rtc_read_offset(struct device *dev, long *offset)
    832{
    833	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    834	unsigned int ctrl_reg;
    835	u8 val;
    836
    837	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
    838
    839	val = ctrl_reg & M41TXX_M_CALIBRATION;
    840
    841	/* check if positive */
    842	if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
    843		*offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
    844	else
    845		*offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
    846
    847	return 0;
    848}
    849
    850static int m41txx_rtc_set_offset(struct device *dev, long offset)
    851{
    852	struct ds1307 *ds1307 = dev_get_drvdata(dev);
    853	unsigned int ctrl_reg;
    854
    855	if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
    856		return -ERANGE;
    857
    858	if (offset >= 0) {
    859		ctrl_reg = DIV_ROUND_CLOSEST(offset,
    860					     M41TXX_POS_OFFSET_STEP_PPB);
    861		ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
    862	} else {
    863		ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
    864					     M41TXX_NEG_OFFSET_STEP_PPB);
    865	}
    866
    867	return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
    868				  M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
    869				  ctrl_reg);
    870}
    871
    872#ifdef CONFIG_WATCHDOG_CORE
    873static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
    874{
    875	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
    876	u8 regs[2];
    877	int ret;
    878
    879	ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
    880				 DS1388_BIT_WF, 0);
    881	if (ret)
    882		return ret;
    883
    884	ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
    885				 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
    886	if (ret)
    887		return ret;
    888
    889	/*
    890	 * watchdog timeouts are measured in seconds. So ignore hundredths of
    891	 * seconds field.
    892	 */
    893	regs[0] = 0;
    894	regs[1] = bin2bcd(wdt_dev->timeout);
    895
    896	ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
    897				sizeof(regs));
    898	if (ret)
    899		return ret;
    900
    901	return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
    902				  DS1388_BIT_WDE | DS1388_BIT_RST,
    903				  DS1388_BIT_WDE | DS1388_BIT_RST);
    904}
    905
    906static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
    907{
    908	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
    909
    910	return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
    911				  DS1388_BIT_WDE | DS1388_BIT_RST, 0);
    912}
    913
    914static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
    915{
    916	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
    917	u8 regs[2];
    918
    919	return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
    920				sizeof(regs));
    921}
    922
    923static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
    924				  unsigned int val)
    925{
    926	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
    927	u8 regs[2];
    928
    929	wdt_dev->timeout = val;
    930	regs[0] = 0;
    931	regs[1] = bin2bcd(wdt_dev->timeout);
    932
    933	return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
    934				 sizeof(regs));
    935}
    936#endif
    937
    938static const struct rtc_class_ops rx8130_rtc_ops = {
    939	.read_time      = ds1307_get_time,
    940	.set_time       = ds1307_set_time,
    941	.read_alarm     = rx8130_read_alarm,
    942	.set_alarm      = rx8130_set_alarm,
    943	.alarm_irq_enable = rx8130_alarm_irq_enable,
    944};
    945
    946static const struct rtc_class_ops mcp794xx_rtc_ops = {
    947	.read_time      = ds1307_get_time,
    948	.set_time       = ds1307_set_time,
    949	.read_alarm     = mcp794xx_read_alarm,
    950	.set_alarm      = mcp794xx_set_alarm,
    951	.alarm_irq_enable = mcp794xx_alarm_irq_enable,
    952};
    953
    954static const struct rtc_class_ops m41txx_rtc_ops = {
    955	.read_time      = ds1307_get_time,
    956	.set_time       = ds1307_set_time,
    957	.read_alarm	= ds1337_read_alarm,
    958	.set_alarm	= ds1337_set_alarm,
    959	.alarm_irq_enable = ds1307_alarm_irq_enable,
    960	.read_offset	= m41txx_rtc_read_offset,
    961	.set_offset	= m41txx_rtc_set_offset,
    962};
    963
    964static const struct chip_desc chips[last_ds_type] = {
    965	[ds_1307] = {
    966		.nvram_offset	= 8,
    967		.nvram_size	= 56,
    968	},
    969	[ds_1308] = {
    970		.nvram_offset	= 8,
    971		.nvram_size	= 56,
    972	},
    973	[ds_1337] = {
    974		.alarm		= 1,
    975		.century_reg	= DS1307_REG_MONTH,
    976		.century_bit	= DS1337_BIT_CENTURY,
    977	},
    978	[ds_1338] = {
    979		.nvram_offset	= 8,
    980		.nvram_size	= 56,
    981	},
    982	[ds_1339] = {
    983		.alarm		= 1,
    984		.century_reg	= DS1307_REG_MONTH,
    985		.century_bit	= DS1337_BIT_CENTURY,
    986		.bbsqi_bit	= DS1339_BIT_BBSQI,
    987		.trickle_charger_reg = 0x10,
    988		.do_trickle_setup = &do_trickle_setup_ds1339,
    989		.requires_trickle_resistor = true,
    990		.charge_default = true,
    991	},
    992	[ds_1340] = {
    993		.century_reg	= DS1307_REG_HOUR,
    994		.century_enable_bit = DS1340_BIT_CENTURY_EN,
    995		.century_bit	= DS1340_BIT_CENTURY,
    996		.do_trickle_setup = &do_trickle_setup_ds1339,
    997		.trickle_charger_reg = 0x08,
    998		.requires_trickle_resistor = true,
    999		.charge_default = true,
   1000	},
   1001	[ds_1341] = {
   1002		.century_reg	= DS1307_REG_MONTH,
   1003		.century_bit	= DS1337_BIT_CENTURY,
   1004	},
   1005	[ds_1388] = {
   1006		.offset		= 1,
   1007		.trickle_charger_reg = 0x0a,
   1008	},
   1009	[ds_3231] = {
   1010		.alarm		= 1,
   1011		.century_reg	= DS1307_REG_MONTH,
   1012		.century_bit	= DS1337_BIT_CENTURY,
   1013		.bbsqi_bit	= DS3231_BIT_BBSQW,
   1014	},
   1015	[rx_8130] = {
   1016		.alarm		= 1,
   1017		/* this is battery backed SRAM */
   1018		.nvram_offset	= 0x20,
   1019		.nvram_size	= 4,	/* 32bit (4 word x 8 bit) */
   1020		.offset		= 0x10,
   1021		.irq_handler = rx8130_irq,
   1022		.rtc_ops = &rx8130_rtc_ops,
   1023		.trickle_charger_reg = RX8130_REG_CONTROL1,
   1024		.do_trickle_setup = &do_trickle_setup_rx8130,
   1025	},
   1026	[m41t0] = {
   1027		.rtc_ops	= &m41txx_rtc_ops,
   1028	},
   1029	[m41t00] = {
   1030		.rtc_ops	= &m41txx_rtc_ops,
   1031	},
   1032	[m41t11] = {
   1033		/* this is battery backed SRAM */
   1034		.nvram_offset	= 8,
   1035		.nvram_size	= 56,
   1036		.rtc_ops	= &m41txx_rtc_ops,
   1037	},
   1038	[mcp794xx] = {
   1039		.alarm		= 1,
   1040		/* this is battery backed SRAM */
   1041		.nvram_offset	= 0x20,
   1042		.nvram_size	= 0x40,
   1043		.irq_handler = mcp794xx_irq,
   1044		.rtc_ops = &mcp794xx_rtc_ops,
   1045	},
   1046};
   1047
   1048static const struct i2c_device_id ds1307_id[] = {
   1049	{ "ds1307", ds_1307 },
   1050	{ "ds1308", ds_1308 },
   1051	{ "ds1337", ds_1337 },
   1052	{ "ds1338", ds_1338 },
   1053	{ "ds1339", ds_1339 },
   1054	{ "ds1388", ds_1388 },
   1055	{ "ds1340", ds_1340 },
   1056	{ "ds1341", ds_1341 },
   1057	{ "ds3231", ds_3231 },
   1058	{ "m41t0", m41t0 },
   1059	{ "m41t00", m41t00 },
   1060	{ "m41t11", m41t11 },
   1061	{ "mcp7940x", mcp794xx },
   1062	{ "mcp7941x", mcp794xx },
   1063	{ "pt7c4338", ds_1307 },
   1064	{ "rx8025", rx_8025 },
   1065	{ "isl12057", ds_1337 },
   1066	{ "rx8130", rx_8130 },
   1067	{ }
   1068};
   1069MODULE_DEVICE_TABLE(i2c, ds1307_id);
   1070
   1071static const struct of_device_id ds1307_of_match[] = {
   1072	{
   1073		.compatible = "dallas,ds1307",
   1074		.data = (void *)ds_1307
   1075	},
   1076	{
   1077		.compatible = "dallas,ds1308",
   1078		.data = (void *)ds_1308
   1079	},
   1080	{
   1081		.compatible = "dallas,ds1337",
   1082		.data = (void *)ds_1337
   1083	},
   1084	{
   1085		.compatible = "dallas,ds1338",
   1086		.data = (void *)ds_1338
   1087	},
   1088	{
   1089		.compatible = "dallas,ds1339",
   1090		.data = (void *)ds_1339
   1091	},
   1092	{
   1093		.compatible = "dallas,ds1388",
   1094		.data = (void *)ds_1388
   1095	},
   1096	{
   1097		.compatible = "dallas,ds1340",
   1098		.data = (void *)ds_1340
   1099	},
   1100	{
   1101		.compatible = "dallas,ds1341",
   1102		.data = (void *)ds_1341
   1103	},
   1104	{
   1105		.compatible = "maxim,ds3231",
   1106		.data = (void *)ds_3231
   1107	},
   1108	{
   1109		.compatible = "st,m41t0",
   1110		.data = (void *)m41t0
   1111	},
   1112	{
   1113		.compatible = "st,m41t00",
   1114		.data = (void *)m41t00
   1115	},
   1116	{
   1117		.compatible = "st,m41t11",
   1118		.data = (void *)m41t11
   1119	},
   1120	{
   1121		.compatible = "microchip,mcp7940x",
   1122		.data = (void *)mcp794xx
   1123	},
   1124	{
   1125		.compatible = "microchip,mcp7941x",
   1126		.data = (void *)mcp794xx
   1127	},
   1128	{
   1129		.compatible = "pericom,pt7c4338",
   1130		.data = (void *)ds_1307
   1131	},
   1132	{
   1133		.compatible = "epson,rx8025",
   1134		.data = (void *)rx_8025
   1135	},
   1136	{
   1137		.compatible = "isil,isl12057",
   1138		.data = (void *)ds_1337
   1139	},
   1140	{
   1141		.compatible = "epson,rx8130",
   1142		.data = (void *)rx_8130
   1143	},
   1144	{ }
   1145};
   1146MODULE_DEVICE_TABLE(of, ds1307_of_match);
   1147
   1148/*
   1149 * The ds1337 and ds1339 both have two alarms, but we only use the first
   1150 * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
   1151 * signal; ds1339 chips have only one alarm signal.
   1152 */
   1153static irqreturn_t ds1307_irq(int irq, void *dev_id)
   1154{
   1155	struct ds1307		*ds1307 = dev_id;
   1156	struct mutex		*lock = &ds1307->rtc->ops_lock;
   1157	int			stat, ret;
   1158
   1159	mutex_lock(lock);
   1160	ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
   1161	if (ret)
   1162		goto out;
   1163
   1164	if (stat & DS1337_BIT_A1I) {
   1165		stat &= ~DS1337_BIT_A1I;
   1166		regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
   1167
   1168		ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
   1169					 DS1337_BIT_A1IE, 0);
   1170		if (ret)
   1171			goto out;
   1172
   1173		rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
   1174	}
   1175
   1176out:
   1177	mutex_unlock(lock);
   1178
   1179	return IRQ_HANDLED;
   1180}
   1181
   1182/*----------------------------------------------------------------------*/
   1183
   1184static const struct rtc_class_ops ds13xx_rtc_ops = {
   1185	.read_time	= ds1307_get_time,
   1186	.set_time	= ds1307_set_time,
   1187	.read_alarm	= ds1337_read_alarm,
   1188	.set_alarm	= ds1337_set_alarm,
   1189	.alarm_irq_enable = ds1307_alarm_irq_enable,
   1190};
   1191
   1192static ssize_t frequency_test_store(struct device *dev,
   1193				    struct device_attribute *attr,
   1194				    const char *buf, size_t count)
   1195{
   1196	struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
   1197	bool freq_test_en;
   1198	int ret;
   1199
   1200	ret = kstrtobool(buf, &freq_test_en);
   1201	if (ret) {
   1202		dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
   1203		return ret;
   1204	}
   1205
   1206	regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
   1207			   freq_test_en ? M41TXX_BIT_FT : 0);
   1208
   1209	return count;
   1210}
   1211
   1212static ssize_t frequency_test_show(struct device *dev,
   1213				   struct device_attribute *attr,
   1214				   char *buf)
   1215{
   1216	struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
   1217	unsigned int ctrl_reg;
   1218
   1219	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
   1220
   1221	return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
   1222			"off\n");
   1223}
   1224
   1225static DEVICE_ATTR_RW(frequency_test);
   1226
   1227static struct attribute *rtc_freq_test_attrs[] = {
   1228	&dev_attr_frequency_test.attr,
   1229	NULL,
   1230};
   1231
   1232static const struct attribute_group rtc_freq_test_attr_group = {
   1233	.attrs		= rtc_freq_test_attrs,
   1234};
   1235
   1236static int ds1307_add_frequency_test(struct ds1307 *ds1307)
   1237{
   1238	int err;
   1239
   1240	switch (ds1307->type) {
   1241	case m41t0:
   1242	case m41t00:
   1243	case m41t11:
   1244		err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
   1245		if (err)
   1246			return err;
   1247		break;
   1248	default:
   1249		break;
   1250	}
   1251
   1252	return 0;
   1253}
   1254
   1255/*----------------------------------------------------------------------*/
   1256
   1257static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
   1258			     size_t bytes)
   1259{
   1260	struct ds1307 *ds1307 = priv;
   1261	const struct chip_desc *chip = &chips[ds1307->type];
   1262
   1263	return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
   1264				val, bytes);
   1265}
   1266
   1267static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
   1268			      size_t bytes)
   1269{
   1270	struct ds1307 *ds1307 = priv;
   1271	const struct chip_desc *chip = &chips[ds1307->type];
   1272
   1273	return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
   1274				 val, bytes);
   1275}
   1276
   1277/*----------------------------------------------------------------------*/
   1278
   1279static u8 ds1307_trickle_init(struct ds1307 *ds1307,
   1280			      const struct chip_desc *chip)
   1281{
   1282	u32 ohms, chargeable;
   1283	bool diode = chip->charge_default;
   1284
   1285	if (!chip->do_trickle_setup)
   1286		return 0;
   1287
   1288	if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
   1289				     &ohms) && chip->requires_trickle_resistor)
   1290		return 0;
   1291
   1292	/* aux-voltage-chargeable takes precedence over the deprecated
   1293	 * trickle-diode-disable
   1294	 */
   1295	if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
   1296				     &chargeable)) {
   1297		switch (chargeable) {
   1298		case 0:
   1299			diode = false;
   1300			break;
   1301		case 1:
   1302			diode = true;
   1303			break;
   1304		default:
   1305			dev_warn(ds1307->dev,
   1306				 "unsupported aux-voltage-chargeable value\n");
   1307			break;
   1308		}
   1309	} else if (device_property_read_bool(ds1307->dev,
   1310					     "trickle-diode-disable")) {
   1311		diode = false;
   1312	}
   1313
   1314	return chip->do_trickle_setup(ds1307, ohms, diode);
   1315}
   1316
   1317/*----------------------------------------------------------------------*/
   1318
   1319#if IS_REACHABLE(CONFIG_HWMON)
   1320
   1321/*
   1322 * Temperature sensor support for ds3231 devices.
   1323 */
   1324
   1325#define DS3231_REG_TEMPERATURE	0x11
   1326
   1327/*
   1328 * A user-initiated temperature conversion is not started by this function,
   1329 * so the temperature is updated once every 64 seconds.
   1330 */
   1331static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
   1332{
   1333	struct ds1307 *ds1307 = dev_get_drvdata(dev);
   1334	u8 temp_buf[2];
   1335	s16 temp;
   1336	int ret;
   1337
   1338	ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
   1339			       temp_buf, sizeof(temp_buf));
   1340	if (ret)
   1341		return ret;
   1342	/*
   1343	 * Temperature is represented as a 10-bit code with a resolution of
   1344	 * 0.25 degree celsius and encoded in two's complement format.
   1345	 */
   1346	temp = (temp_buf[0] << 8) | temp_buf[1];
   1347	temp >>= 6;
   1348	*mC = temp * 250;
   1349
   1350	return 0;
   1351}
   1352
   1353static ssize_t ds3231_hwmon_show_temp(struct device *dev,
   1354				      struct device_attribute *attr, char *buf)
   1355{
   1356	int ret;
   1357	s32 temp;
   1358
   1359	ret = ds3231_hwmon_read_temp(dev, &temp);
   1360	if (ret)
   1361		return ret;
   1362
   1363	return sprintf(buf, "%d\n", temp);
   1364}
   1365static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
   1366			  NULL, 0);
   1367
   1368static struct attribute *ds3231_hwmon_attrs[] = {
   1369	&sensor_dev_attr_temp1_input.dev_attr.attr,
   1370	NULL,
   1371};
   1372ATTRIBUTE_GROUPS(ds3231_hwmon);
   1373
   1374static void ds1307_hwmon_register(struct ds1307 *ds1307)
   1375{
   1376	struct device *dev;
   1377
   1378	if (ds1307->type != ds_3231)
   1379		return;
   1380
   1381	dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
   1382						     ds1307,
   1383						     ds3231_hwmon_groups);
   1384	if (IS_ERR(dev)) {
   1385		dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
   1386			 PTR_ERR(dev));
   1387	}
   1388}
   1389
   1390#else
   1391
   1392static void ds1307_hwmon_register(struct ds1307 *ds1307)
   1393{
   1394}
   1395
   1396#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
   1397
   1398/*----------------------------------------------------------------------*/
   1399
   1400/*
   1401 * Square-wave output support for DS3231
   1402 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
   1403 */
   1404#ifdef CONFIG_COMMON_CLK
   1405
   1406enum {
   1407	DS3231_CLK_SQW = 0,
   1408	DS3231_CLK_32KHZ,
   1409};
   1410
   1411#define clk_sqw_to_ds1307(clk)	\
   1412	container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
   1413#define clk_32khz_to_ds1307(clk)	\
   1414	container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
   1415
   1416static int ds3231_clk_sqw_rates[] = {
   1417	1,
   1418	1024,
   1419	4096,
   1420	8192,
   1421};
   1422
   1423static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
   1424{
   1425	struct mutex *lock = &ds1307->rtc->ops_lock;
   1426	int ret;
   1427
   1428	mutex_lock(lock);
   1429	ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
   1430				 mask, value);
   1431	mutex_unlock(lock);
   1432
   1433	return ret;
   1434}
   1435
   1436static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
   1437						unsigned long parent_rate)
   1438{
   1439	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
   1440	int control, ret;
   1441	int rate_sel = 0;
   1442
   1443	ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
   1444	if (ret)
   1445		return ret;
   1446	if (control & DS1337_BIT_RS1)
   1447		rate_sel += 1;
   1448	if (control & DS1337_BIT_RS2)
   1449		rate_sel += 2;
   1450
   1451	return ds3231_clk_sqw_rates[rate_sel];
   1452}
   1453
   1454static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
   1455				      unsigned long *prate)
   1456{
   1457	int i;
   1458
   1459	for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
   1460		if (ds3231_clk_sqw_rates[i] <= rate)
   1461			return ds3231_clk_sqw_rates[i];
   1462	}
   1463
   1464	return 0;
   1465}
   1466
   1467static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
   1468				   unsigned long parent_rate)
   1469{
   1470	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
   1471	int control = 0;
   1472	int rate_sel;
   1473
   1474	for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
   1475			rate_sel++) {
   1476		if (ds3231_clk_sqw_rates[rate_sel] == rate)
   1477			break;
   1478	}
   1479
   1480	if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
   1481		return -EINVAL;
   1482
   1483	if (rate_sel & 1)
   1484		control |= DS1337_BIT_RS1;
   1485	if (rate_sel & 2)
   1486		control |= DS1337_BIT_RS2;
   1487
   1488	return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
   1489				control);
   1490}
   1491
   1492static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
   1493{
   1494	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
   1495
   1496	return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
   1497}
   1498
   1499static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
   1500{
   1501	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
   1502
   1503	ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
   1504}
   1505
   1506static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
   1507{
   1508	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
   1509	int control, ret;
   1510
   1511	ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
   1512	if (ret)
   1513		return ret;
   1514
   1515	return !(control & DS1337_BIT_INTCN);
   1516}
   1517
   1518static const struct clk_ops ds3231_clk_sqw_ops = {
   1519	.prepare = ds3231_clk_sqw_prepare,
   1520	.unprepare = ds3231_clk_sqw_unprepare,
   1521	.is_prepared = ds3231_clk_sqw_is_prepared,
   1522	.recalc_rate = ds3231_clk_sqw_recalc_rate,
   1523	.round_rate = ds3231_clk_sqw_round_rate,
   1524	.set_rate = ds3231_clk_sqw_set_rate,
   1525};
   1526
   1527static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
   1528						  unsigned long parent_rate)
   1529{
   1530	return 32768;
   1531}
   1532
   1533static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
   1534{
   1535	struct mutex *lock = &ds1307->rtc->ops_lock;
   1536	int ret;
   1537
   1538	mutex_lock(lock);
   1539	ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
   1540				 DS3231_BIT_EN32KHZ,
   1541				 enable ? DS3231_BIT_EN32KHZ : 0);
   1542	mutex_unlock(lock);
   1543
   1544	return ret;
   1545}
   1546
   1547static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
   1548{
   1549	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
   1550
   1551	return ds3231_clk_32khz_control(ds1307, true);
   1552}
   1553
   1554static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
   1555{
   1556	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
   1557
   1558	ds3231_clk_32khz_control(ds1307, false);
   1559}
   1560
   1561static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
   1562{
   1563	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
   1564	int status, ret;
   1565
   1566	ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
   1567	if (ret)
   1568		return ret;
   1569
   1570	return !!(status & DS3231_BIT_EN32KHZ);
   1571}
   1572
   1573static const struct clk_ops ds3231_clk_32khz_ops = {
   1574	.prepare = ds3231_clk_32khz_prepare,
   1575	.unprepare = ds3231_clk_32khz_unprepare,
   1576	.is_prepared = ds3231_clk_32khz_is_prepared,
   1577	.recalc_rate = ds3231_clk_32khz_recalc_rate,
   1578};
   1579
   1580static const char *ds3231_clks_names[] = {
   1581	[DS3231_CLK_SQW] = "ds3231_clk_sqw",
   1582	[DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
   1583};
   1584
   1585static struct clk_init_data ds3231_clks_init[] = {
   1586	[DS3231_CLK_SQW] = {
   1587		.ops = &ds3231_clk_sqw_ops,
   1588	},
   1589	[DS3231_CLK_32KHZ] = {
   1590		.ops = &ds3231_clk_32khz_ops,
   1591	},
   1592};
   1593
   1594static int ds3231_clks_register(struct ds1307 *ds1307)
   1595{
   1596	struct device_node *node = ds1307->dev->of_node;
   1597	struct clk_onecell_data	*onecell;
   1598	int i;
   1599
   1600	onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
   1601	if (!onecell)
   1602		return -ENOMEM;
   1603
   1604	onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
   1605	onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
   1606				     sizeof(onecell->clks[0]), GFP_KERNEL);
   1607	if (!onecell->clks)
   1608		return -ENOMEM;
   1609
   1610	/* optional override of the clockname */
   1611	device_property_read_string_array(ds1307->dev, "clock-output-names",
   1612					  ds3231_clks_names,
   1613					  ARRAY_SIZE(ds3231_clks_names));
   1614
   1615	for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
   1616		struct clk_init_data init = ds3231_clks_init[i];
   1617
   1618		/*
   1619		 * Interrupt signal due to alarm conditions and square-wave
   1620		 * output share same pin, so don't initialize both.
   1621		 */
   1622		if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
   1623			continue;
   1624
   1625		init.name = ds3231_clks_names[i];
   1626		ds1307->clks[i].init = &init;
   1627
   1628		onecell->clks[i] = devm_clk_register(ds1307->dev,
   1629						     &ds1307->clks[i]);
   1630		if (IS_ERR(onecell->clks[i]))
   1631			return PTR_ERR(onecell->clks[i]);
   1632	}
   1633
   1634	if (node)
   1635		of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
   1636
   1637	return 0;
   1638}
   1639
   1640static void ds1307_clks_register(struct ds1307 *ds1307)
   1641{
   1642	int ret;
   1643
   1644	if (ds1307->type != ds_3231)
   1645		return;
   1646
   1647	ret = ds3231_clks_register(ds1307);
   1648	if (ret) {
   1649		dev_warn(ds1307->dev, "unable to register clock device %d\n",
   1650			 ret);
   1651	}
   1652}
   1653
   1654#else
   1655
   1656static void ds1307_clks_register(struct ds1307 *ds1307)
   1657{
   1658}
   1659
   1660#endif /* CONFIG_COMMON_CLK */
   1661
   1662#ifdef CONFIG_WATCHDOG_CORE
   1663static const struct watchdog_info ds1388_wdt_info = {
   1664	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
   1665	.identity = "DS1388 watchdog",
   1666};
   1667
   1668static const struct watchdog_ops ds1388_wdt_ops = {
   1669	.owner = THIS_MODULE,
   1670	.start = ds1388_wdt_start,
   1671	.stop = ds1388_wdt_stop,
   1672	.ping = ds1388_wdt_ping,
   1673	.set_timeout = ds1388_wdt_set_timeout,
   1674
   1675};
   1676
   1677static void ds1307_wdt_register(struct ds1307 *ds1307)
   1678{
   1679	struct watchdog_device	*wdt;
   1680	int err;
   1681	int val;
   1682
   1683	if (ds1307->type != ds_1388)
   1684		return;
   1685
   1686	wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
   1687	if (!wdt)
   1688		return;
   1689
   1690	err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
   1691	if (!err && val & DS1388_BIT_WF)
   1692		wdt->bootstatus = WDIOF_CARDRESET;
   1693
   1694	wdt->info = &ds1388_wdt_info;
   1695	wdt->ops = &ds1388_wdt_ops;
   1696	wdt->timeout = 99;
   1697	wdt->max_timeout = 99;
   1698	wdt->min_timeout = 1;
   1699
   1700	watchdog_init_timeout(wdt, 0, ds1307->dev);
   1701	watchdog_set_drvdata(wdt, ds1307);
   1702	devm_watchdog_register_device(ds1307->dev, wdt);
   1703}
   1704#else
   1705static void ds1307_wdt_register(struct ds1307 *ds1307)
   1706{
   1707}
   1708#endif /* CONFIG_WATCHDOG_CORE */
   1709
   1710static const struct regmap_config regmap_config = {
   1711	.reg_bits = 8,
   1712	.val_bits = 8,
   1713};
   1714
   1715static int ds1307_probe(struct i2c_client *client,
   1716			const struct i2c_device_id *id)
   1717{
   1718	struct ds1307		*ds1307;
   1719	const void		*match;
   1720	int			err = -ENODEV;
   1721	int			tmp;
   1722	const struct chip_desc	*chip;
   1723	bool			want_irq;
   1724	bool			ds1307_can_wakeup_device = false;
   1725	unsigned char		regs[8];
   1726	struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
   1727	u8			trickle_charger_setup = 0;
   1728
   1729	ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
   1730	if (!ds1307)
   1731		return -ENOMEM;
   1732
   1733	dev_set_drvdata(&client->dev, ds1307);
   1734	ds1307->dev = &client->dev;
   1735	ds1307->name = client->name;
   1736
   1737	ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
   1738	if (IS_ERR(ds1307->regmap)) {
   1739		dev_err(ds1307->dev, "regmap allocation failed\n");
   1740		return PTR_ERR(ds1307->regmap);
   1741	}
   1742
   1743	i2c_set_clientdata(client, ds1307);
   1744
   1745	match = device_get_match_data(&client->dev);
   1746	if (match) {
   1747		ds1307->type = (enum ds_type)match;
   1748		chip = &chips[ds1307->type];
   1749	} else if (id) {
   1750		chip = &chips[id->driver_data];
   1751		ds1307->type = id->driver_data;
   1752	} else {
   1753		return -ENODEV;
   1754	}
   1755
   1756	want_irq = client->irq > 0 && chip->alarm;
   1757
   1758	if (!pdata)
   1759		trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
   1760	else if (pdata->trickle_charger_setup)
   1761		trickle_charger_setup = pdata->trickle_charger_setup;
   1762
   1763	if (trickle_charger_setup && chip->trickle_charger_reg) {
   1764		dev_dbg(ds1307->dev,
   1765			"writing trickle charger info 0x%x to 0x%x\n",
   1766			trickle_charger_setup, chip->trickle_charger_reg);
   1767		regmap_write(ds1307->regmap, chip->trickle_charger_reg,
   1768			     trickle_charger_setup);
   1769	}
   1770
   1771/*
   1772 * For devices with no IRQ directly connected to the SoC, the RTC chip
   1773 * can be forced as a wakeup source by stating that explicitly in
   1774 * the device's .dts file using the "wakeup-source" boolean property.
   1775 * If the "wakeup-source" property is set, don't request an IRQ.
   1776 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
   1777 * if supported by the RTC.
   1778 */
   1779	if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
   1780		ds1307_can_wakeup_device = true;
   1781
   1782	switch (ds1307->type) {
   1783	case ds_1337:
   1784	case ds_1339:
   1785	case ds_1341:
   1786	case ds_3231:
   1787		/* get registers that the "rtc" read below won't read... */
   1788		err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
   1789				       regs, 2);
   1790		if (err) {
   1791			dev_dbg(ds1307->dev, "read error %d\n", err);
   1792			goto exit;
   1793		}
   1794
   1795		/* oscillator off?  turn it on, so clock can tick. */
   1796		if (regs[0] & DS1337_BIT_nEOSC)
   1797			regs[0] &= ~DS1337_BIT_nEOSC;
   1798
   1799		/*
   1800		 * Using IRQ or defined as wakeup-source?
   1801		 * Disable the square wave and both alarms.
   1802		 * For some variants, be sure alarms can trigger when we're
   1803		 * running on Vbackup (BBSQI/BBSQW)
   1804		 */
   1805		if (want_irq || ds1307_can_wakeup_device) {
   1806			regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
   1807			regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
   1808		}
   1809
   1810		regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
   1811			     regs[0]);
   1812
   1813		/* oscillator fault?  clear flag, and warn */
   1814		if (regs[1] & DS1337_BIT_OSF) {
   1815			regmap_write(ds1307->regmap, DS1337_REG_STATUS,
   1816				     regs[1] & ~DS1337_BIT_OSF);
   1817			dev_warn(ds1307->dev, "SET TIME!\n");
   1818		}
   1819		break;
   1820
   1821	case rx_8025:
   1822		err = regmap_bulk_read(ds1307->regmap,
   1823				       RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
   1824		if (err) {
   1825			dev_dbg(ds1307->dev, "read error %d\n", err);
   1826			goto exit;
   1827		}
   1828
   1829		/* oscillator off?  turn it on, so clock can tick. */
   1830		if (!(regs[1] & RX8025_BIT_XST)) {
   1831			regs[1] |= RX8025_BIT_XST;
   1832			regmap_write(ds1307->regmap,
   1833				     RX8025_REG_CTRL2 << 4 | 0x08,
   1834				     regs[1]);
   1835			dev_warn(ds1307->dev,
   1836				 "oscillator stop detected - SET TIME!\n");
   1837		}
   1838
   1839		if (regs[1] & RX8025_BIT_PON) {
   1840			regs[1] &= ~RX8025_BIT_PON;
   1841			regmap_write(ds1307->regmap,
   1842				     RX8025_REG_CTRL2 << 4 | 0x08,
   1843				     regs[1]);
   1844			dev_warn(ds1307->dev, "power-on detected\n");
   1845		}
   1846
   1847		if (regs[1] & RX8025_BIT_VDET) {
   1848			regs[1] &= ~RX8025_BIT_VDET;
   1849			regmap_write(ds1307->regmap,
   1850				     RX8025_REG_CTRL2 << 4 | 0x08,
   1851				     regs[1]);
   1852			dev_warn(ds1307->dev, "voltage drop detected\n");
   1853		}
   1854
   1855		/* make sure we are running in 24hour mode */
   1856		if (!(regs[0] & RX8025_BIT_2412)) {
   1857			u8 hour;
   1858
   1859			/* switch to 24 hour mode */
   1860			regmap_write(ds1307->regmap,
   1861				     RX8025_REG_CTRL1 << 4 | 0x08,
   1862				     regs[0] | RX8025_BIT_2412);
   1863
   1864			err = regmap_bulk_read(ds1307->regmap,
   1865					       RX8025_REG_CTRL1 << 4 | 0x08,
   1866					       regs, 2);
   1867			if (err) {
   1868				dev_dbg(ds1307->dev, "read error %d\n", err);
   1869				goto exit;
   1870			}
   1871
   1872			/* correct hour */
   1873			hour = bcd2bin(regs[DS1307_REG_HOUR]);
   1874			if (hour == 12)
   1875				hour = 0;
   1876			if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
   1877				hour += 12;
   1878
   1879			regmap_write(ds1307->regmap,
   1880				     DS1307_REG_HOUR << 4 | 0x08, hour);
   1881		}
   1882		break;
   1883	case ds_1388:
   1884		err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
   1885		if (err) {
   1886			dev_dbg(ds1307->dev, "read error %d\n", err);
   1887			goto exit;
   1888		}
   1889
   1890		/* oscillator off?  turn it on, so clock can tick. */
   1891		if (tmp & DS1388_BIT_nEOSC) {
   1892			tmp &= ~DS1388_BIT_nEOSC;
   1893			regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
   1894		}
   1895		break;
   1896	default:
   1897		break;
   1898	}
   1899
   1900	/* read RTC registers */
   1901	err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
   1902			       sizeof(regs));
   1903	if (err) {
   1904		dev_dbg(ds1307->dev, "read error %d\n", err);
   1905		goto exit;
   1906	}
   1907
   1908	if (ds1307->type == mcp794xx &&
   1909	    !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
   1910		regmap_write(ds1307->regmap, DS1307_REG_WDAY,
   1911			     regs[DS1307_REG_WDAY] |
   1912			     MCP794XX_BIT_VBATEN);
   1913	}
   1914
   1915	tmp = regs[DS1307_REG_HOUR];
   1916	switch (ds1307->type) {
   1917	case ds_1340:
   1918	case m41t0:
   1919	case m41t00:
   1920	case m41t11:
   1921		/*
   1922		 * NOTE: ignores century bits; fix before deploying
   1923		 * systems that will run through year 2100.
   1924		 */
   1925		break;
   1926	case rx_8025:
   1927		break;
   1928	default:
   1929		if (!(tmp & DS1307_BIT_12HR))
   1930			break;
   1931
   1932		/*
   1933		 * Be sure we're in 24 hour mode.  Multi-master systems
   1934		 * take note...
   1935		 */
   1936		tmp = bcd2bin(tmp & 0x1f);
   1937		if (tmp == 12)
   1938			tmp = 0;
   1939		if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
   1940			tmp += 12;
   1941		regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
   1942			     bin2bcd(tmp));
   1943	}
   1944
   1945	ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
   1946	if (IS_ERR(ds1307->rtc))
   1947		return PTR_ERR(ds1307->rtc);
   1948
   1949	if (want_irq || ds1307_can_wakeup_device)
   1950		device_set_wakeup_capable(ds1307->dev, true);
   1951	else
   1952		clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
   1953
   1954	if (ds1307_can_wakeup_device && !want_irq) {
   1955		dev_info(ds1307->dev,
   1956			 "'wakeup-source' is set, request for an IRQ is disabled!\n");
   1957		/* We cannot support UIE mode if we do not have an IRQ line */
   1958		clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features);
   1959	}
   1960
   1961	if (want_irq) {
   1962		err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
   1963						chip->irq_handler ?: ds1307_irq,
   1964						IRQF_SHARED | IRQF_ONESHOT,
   1965						ds1307->name, ds1307);
   1966		if (err) {
   1967			client->irq = 0;
   1968			device_set_wakeup_capable(ds1307->dev, false);
   1969			clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
   1970			dev_err(ds1307->dev, "unable to request IRQ!\n");
   1971		} else {
   1972			dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
   1973		}
   1974	}
   1975
   1976	ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
   1977	err = ds1307_add_frequency_test(ds1307);
   1978	if (err)
   1979		return err;
   1980
   1981	err = devm_rtc_register_device(ds1307->rtc);
   1982	if (err)
   1983		return err;
   1984
   1985	if (chip->nvram_size) {
   1986		struct nvmem_config nvmem_cfg = {
   1987			.name = "ds1307_nvram",
   1988			.word_size = 1,
   1989			.stride = 1,
   1990			.size = chip->nvram_size,
   1991			.reg_read = ds1307_nvram_read,
   1992			.reg_write = ds1307_nvram_write,
   1993			.priv = ds1307,
   1994		};
   1995
   1996		devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
   1997	}
   1998
   1999	ds1307_hwmon_register(ds1307);
   2000	ds1307_clks_register(ds1307);
   2001	ds1307_wdt_register(ds1307);
   2002
   2003	return 0;
   2004
   2005exit:
   2006	return err;
   2007}
   2008
   2009static struct i2c_driver ds1307_driver = {
   2010	.driver = {
   2011		.name	= "rtc-ds1307",
   2012		.of_match_table = ds1307_of_match,
   2013	},
   2014	.probe		= ds1307_probe,
   2015	.id_table	= ds1307_id,
   2016};
   2017
   2018module_i2c_driver(ds1307_driver);
   2019
   2020MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
   2021MODULE_LICENSE("GPL");