cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rtc-s3c.h (2152B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
      4 *		      http://www.simtec.co.uk/products/SWLINUX/
      5 *
      6 * S3C2410 Internal RTC register definition
      7*/
      8
      9#ifndef __ASM_ARCH_REGS_RTC_H
     10#define __ASM_ARCH_REGS_RTC_H __FILE__
     11
     12#define S3C2410_RTCREG(x) (x)
     13#define S3C2410_INTP		S3C2410_RTCREG(0x30)
     14#define S3C2410_INTP_ALM	(1 << 1)
     15#define S3C2410_INTP_TIC	(1 << 0)
     16
     17#define S3C2410_RTCCON		S3C2410_RTCREG(0x40)
     18#define S3C2410_RTCCON_RTCEN	(1 << 0)
     19#define S3C2410_RTCCON_CNTSEL	(1 << 2)
     20#define S3C2410_RTCCON_CLKRST	(1 << 3)
     21#define S3C2443_RTCCON_TICSEL	(1 << 4)
     22#define S3C64XX_RTCCON_TICEN	(1 << 8)
     23
     24#define S3C2410_TICNT		S3C2410_RTCREG(0x44)
     25#define S3C2410_TICNT_ENABLE	(1 << 7)
     26
     27/* S3C2443: tick count is 15 bit wide
     28 * TICNT[6:0] contains upper 7 bits
     29 * TICNT1[7:0] contains lower 8 bits
     30 */
     31#define S3C2443_TICNT_PART(x)	((x & 0x7f00) >> 8)
     32#define S3C2443_TICNT1		S3C2410_RTCREG(0x4C)
     33#define S3C2443_TICNT1_PART(x)	(x & 0xff)
     34
     35/* S3C2416: tick count is 32 bit wide
     36 * TICNT[6:0] contains bits [14:8]
     37 * TICNT1[7:0] contains lower 8 bits
     38 * TICNT2[16:0] contains upper 17 bits
     39 */
     40#define S3C2416_TICNT2		S3C2410_RTCREG(0x48)
     41#define S3C2416_TICNT2_PART(x)	((x & 0xffff8000) >> 15)
     42
     43#define S3C2410_RTCALM		S3C2410_RTCREG(0x50)
     44#define S3C2410_RTCALM_ALMEN	(1 << 6)
     45#define S3C2410_RTCALM_YEAREN	(1 << 5)
     46#define S3C2410_RTCALM_MONEN	(1 << 4)
     47#define S3C2410_RTCALM_DAYEN	(1 << 3)
     48#define S3C2410_RTCALM_HOUREN	(1 << 2)
     49#define S3C2410_RTCALM_MINEN	(1 << 1)
     50#define S3C2410_RTCALM_SECEN	(1 << 0)
     51
     52#define S3C2410_ALMSEC		S3C2410_RTCREG(0x54)
     53#define S3C2410_ALMMIN		S3C2410_RTCREG(0x58)
     54#define S3C2410_ALMHOUR		S3C2410_RTCREG(0x5c)
     55
     56#define S3C2410_ALMDATE		S3C2410_RTCREG(0x60)
     57#define S3C2410_ALMMON		S3C2410_RTCREG(0x64)
     58#define S3C2410_ALMYEAR		S3C2410_RTCREG(0x68)
     59
     60#define S3C2410_RTCSEC		S3C2410_RTCREG(0x70)
     61#define S3C2410_RTCMIN		S3C2410_RTCREG(0x74)
     62#define S3C2410_RTCHOUR		S3C2410_RTCREG(0x78)
     63#define S3C2410_RTCDATE		S3C2410_RTCREG(0x7c)
     64#define S3C2410_RTCMON		S3C2410_RTCREG(0x84)
     65#define S3C2410_RTCYEAR		S3C2410_RTCREG(0x88)
     66
     67#endif /* __ASM_ARCH_REGS_RTC_H */