cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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be_main.h (28987B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright 2017 Broadcom. All Rights Reserved.
      4 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
      5 *
      6 * Contact Information:
      7 * linux-drivers@broadcom.com
      8 */
      9
     10#ifndef _BEISCSI_MAIN_
     11#define _BEISCSI_MAIN_
     12
     13#include <linux/kernel.h>
     14#include <linux/pci.h>
     15#include <linux/if_ether.h>
     16#include <linux/in.h>
     17#include <linux/ctype.h>
     18#include <linux/module.h>
     19#include <linux/aer.h>
     20#include <scsi/scsi.h>
     21#include <scsi/scsi_cmnd.h>
     22#include <scsi/scsi_device.h>
     23#include <scsi/scsi_host.h>
     24#include <scsi/iscsi_proto.h>
     25#include <scsi/libiscsi.h>
     26#include <scsi/scsi_transport_iscsi.h>
     27
     28#define DRV_NAME		"be2iscsi"
     29#define BUILD_STR		"11.4.0.1"
     30#define BE_NAME			"Emulex OneConnect" \
     31				"Open-iSCSI Driver version" BUILD_STR
     32#define DRV_DESC		BE_NAME " " "Driver"
     33
     34#define BE_VENDOR_ID		0x19A2
     35#define ELX_VENDOR_ID		0x10DF
     36/* DEVICE ID's for BE2 */
     37#define BE_DEVICE_ID1		0x212
     38#define OC_DEVICE_ID1		0x702
     39#define OC_DEVICE_ID2		0x703
     40
     41/* DEVICE ID's for BE3 */
     42#define BE_DEVICE_ID2		0x222
     43#define OC_DEVICE_ID3		0x712
     44
     45/* DEVICE ID for SKH */
     46#define OC_SKH_ID1		0x722
     47
     48#define BE2_IO_DEPTH		1024
     49#define BE2_MAX_SESSIONS	256
     50#define BE2_TMFS		16
     51#define BE2_NOPOUT_REQ		16
     52#define BE2_SGE			32
     53#define BE2_DEFPDU_HDR_SZ	64
     54#define BE2_DEFPDU_DATA_SZ	8192
     55#define BE2_MAX_NUM_CQ_PROC	512
     56
     57#define MAX_CPUS		64U
     58#define BEISCSI_MAX_NUM_CPUS	7
     59
     60#define BEISCSI_VER_STRLEN 32
     61
     62#define BEISCSI_SGLIST_ELEMENTS	30
     63
     64/**
     65 * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
     66 * be invalidated at a time, consider it before changing the value of
     67 * BEISCSI_CMD_PER_LUN.
     68 */
     69#define BEISCSI_CMD_PER_LUN	128	/* scsi_host->cmd_per_lun */
     70#define BEISCSI_MAX_SECTORS	1024	/* scsi_host->max_sectors */
     71#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
     72
     73#define BEISCSI_MAX_CMD_LEN	16	/* scsi_host->max_cmd_len */
     74#define BEISCSI_NUM_MAX_LUN	256	/* scsi_host->max_lun */
     75#define BEISCSI_MAX_FRAGS_INIT	192
     76
     77#define BE_SENSE_INFO_SIZE		258
     78#define BE_ISCSI_PDU_HEADER_SIZE	64
     79#define BE_MIN_MEM_SIZE			16384
     80#define MAX_CMD_SZ			65536
     81#define IIOC_SCSI_DATA                  0x05	/* Write Operation */
     82
     83/**
     84 * hardware needs the async PDU buffers to be posted in multiples of 8
     85 * So have atleast 8 of them by default
     86 */
     87
     88#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)	\
     89	(phwi->phwi_ctxt->pasync_ctx[ulp_num])
     90
     91/********* Memory BAR register ************/
     92#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET	0xfc
     93/**
     94 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
     95 * Disable" may still globally block interrupts in addition to individual
     96 * interrupt masks; a mechanism for the device driver to block all interrupts
     97 * atomically without having to arbitrate for the PCI Interrupt Disable bit
     98 * with the OS.
     99 */
    100#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	(1 << 29)	/* bit 29 */
    101
    102/********* ISR0 Register offset **********/
    103#define CEV_ISR0_OFFSET				0xC18
    104#define CEV_ISR_SIZE				4
    105
    106/**
    107 * Macros for reading/writing a protection domain or CSR registers
    108 * in BladeEngine.
    109 */
    110
    111#define DB_TXULP0_OFFSET 0x40
    112#define DB_RXULP0_OFFSET 0xA0
    113/********* Event Q door bell *************/
    114#define DB_EQ_OFFSET			DB_CQ_OFFSET
    115#define DB_EQ_RING_ID_LOW_MASK		0x1FF	/* bits 0 - 8 */
    116/* Clear the interrupt for this eq */
    117#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
    118/* Must be 1 */
    119#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
    120/* Higher Order EQ_ID bit */
    121#define DB_EQ_RING_ID_HIGH_MASK	0x1F /* bits 11 - 15 */
    122#define DB_EQ_HIGH_SET_SHIFT	11
    123#define DB_EQ_HIGH_FEILD_SHIFT	9
    124/* Number of event entries processed */
    125#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
    126/* Rearm bit */
    127#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
    128
    129/********* Compl Q door bell *************/
    130#define DB_CQ_OFFSET			0x120
    131#define DB_CQ_RING_ID_LOW_MASK		0x3FF	/* bits 0 - 9 */
    132/* Higher Order CQ_ID bit */
    133#define DB_CQ_RING_ID_HIGH_MASK	0x1F /* bits 11 - 15 */
    134#define DB_CQ_HIGH_SET_SHIFT	11
    135#define DB_CQ_HIGH_FEILD_SHIFT	10
    136
    137/* Number of event entries processed */
    138#define DB_CQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
    139/* Rearm bit */
    140#define DB_CQ_REARM_SHIFT		(29)	/* bit 29 */
    141
    142#define GET_HWI_CONTROLLER_WS(pc)	(pc->phwi_ctrlr)
    143#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
    144		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
    145#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
    146		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
    147
    148#define PAGES_REQUIRED(x) \
    149	((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
    150
    151#define MEM_DESCR_OFFSET 8
    152#define BEISCSI_DEFQ_HDR 1
    153#define BEISCSI_DEFQ_DATA 0
    154enum be_mem_enum {
    155	HWI_MEM_ADDN_CONTEXT,
    156	HWI_MEM_WRB,
    157	HWI_MEM_WRBH,
    158	HWI_MEM_SGLH,
    159	HWI_MEM_SGE,
    160	HWI_MEM_TEMPLATE_HDR_ULP0,
    161	HWI_MEM_ASYNC_HEADER_BUF_ULP0,	/* 6 */
    162	HWI_MEM_ASYNC_DATA_BUF_ULP0,
    163	HWI_MEM_ASYNC_HEADER_RING_ULP0,
    164	HWI_MEM_ASYNC_DATA_RING_ULP0,
    165	HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
    166	HWI_MEM_ASYNC_DATA_HANDLE_ULP0,	/* 11 */
    167	HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
    168	HWI_MEM_TEMPLATE_HDR_ULP1,
    169	HWI_MEM_ASYNC_HEADER_BUF_ULP1,	/* 14 */
    170	HWI_MEM_ASYNC_DATA_BUF_ULP1,
    171	HWI_MEM_ASYNC_HEADER_RING_ULP1,
    172	HWI_MEM_ASYNC_DATA_RING_ULP1,
    173	HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
    174	HWI_MEM_ASYNC_DATA_HANDLE_ULP1,	/* 19 */
    175	HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
    176	ISCSI_MEM_GLOBAL_HEADER,
    177	SE_MEM_MAX
    178};
    179
    180struct be_bus_address32 {
    181	unsigned int address_lo;
    182	unsigned int address_hi;
    183};
    184
    185struct be_bus_address64 {
    186	unsigned long long address;
    187};
    188
    189struct be_bus_address {
    190	union {
    191		struct be_bus_address32 a32;
    192		struct be_bus_address64 a64;
    193	} u;
    194};
    195
    196struct mem_array {
    197	struct be_bus_address bus_address;	/* Bus address of location */
    198	void *virtual_address;		/* virtual address to the location */
    199	unsigned int size;		/* Size required by memory block */
    200};
    201
    202struct be_mem_descriptor {
    203	unsigned int size_in_bytes;	/* Size required by memory block */
    204	unsigned int num_elements;
    205	struct mem_array *mem_array;
    206};
    207
    208struct sgl_handle {
    209	unsigned int sgl_index;
    210	unsigned int type;
    211	unsigned int cid;
    212	struct iscsi_task *task;
    213	struct iscsi_sge *pfrag;
    214};
    215
    216struct hba_parameters {
    217	unsigned int ios_per_ctrl;
    218	unsigned int cxns_per_ctrl;
    219	unsigned int icds_per_ctrl;
    220	unsigned int num_sge_per_io;
    221	unsigned int defpdu_hdr_sz;
    222	unsigned int defpdu_data_sz;
    223	unsigned int num_cq_entries;
    224	unsigned int num_eq_entries;
    225	unsigned int wrbs_per_cxn;
    226	unsigned int hwi_ws_sz;
    227};
    228
    229#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
    230	(phwi_ctrlr->wrb_context[cri].ulp_num)
    231struct hwi_wrb_context {
    232	spinlock_t wrb_lock;
    233	struct wrb_handle **pwrb_handle_base;
    234	struct wrb_handle **pwrb_handle_basestd;
    235	struct iscsi_wrb *plast_wrb;
    236	unsigned short alloc_index;
    237	unsigned short free_index;
    238	unsigned short wrb_handles_available;
    239	unsigned short cid;
    240	uint8_t ulp_num;	/* ULP to which CID binded */
    241	uint32_t doorbell_offset;
    242};
    243
    244struct ulp_cid_info {
    245	unsigned short *cid_array;
    246	unsigned short avlbl_cids;
    247	unsigned short cid_alloc;
    248	unsigned short cid_free;
    249};
    250
    251#include "be.h"
    252#define chip_be2(phba)      (phba->generation == BE_GEN2)
    253#define chip_be3_r(phba)    (phba->generation == BE_GEN3)
    254#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
    255
    256#define BEISCSI_ULP0    0
    257#define BEISCSI_ULP1    1
    258#define BEISCSI_ULP_COUNT   2
    259#define BEISCSI_ULP0_LOADED 0x01
    260#define BEISCSI_ULP1_LOADED 0x02
    261
    262#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
    263	(((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
    264#define BEISCSI_ULP0_AVLBL_CID(phba) \
    265	BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
    266#define BEISCSI_ULP1_AVLBL_CID(phba) \
    267	BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
    268
    269struct beiscsi_hba {
    270	struct hba_parameters params;
    271	struct hwi_controller *phwi_ctrlr;
    272	unsigned int mem_req[SE_MEM_MAX];
    273	/* PCI BAR mapped addresses */
    274	u8 __iomem *csr_va;	/* CSR */
    275	u8 __iomem *db_va;	/* Door  Bell  */
    276	u8 __iomem *pci_va;	/* PCI Config */
    277	/* PCI representation of our HBA */
    278	struct pci_dev *pcidev;
    279	unsigned int num_cpus;
    280	unsigned int nxt_cqid;
    281	char *msi_name[MAX_CPUS];
    282	struct be_mem_descriptor *init_mem;
    283
    284	unsigned short io_sgl_alloc_index;
    285	unsigned short io_sgl_free_index;
    286	unsigned short io_sgl_hndl_avbl;
    287	struct sgl_handle **io_sgl_hndl_base;
    288
    289	unsigned short eh_sgl_alloc_index;
    290	unsigned short eh_sgl_free_index;
    291	unsigned short eh_sgl_hndl_avbl;
    292	struct sgl_handle **eh_sgl_hndl_base;
    293	spinlock_t io_sgl_lock;
    294	spinlock_t mgmt_sgl_lock;
    295	spinlock_t async_pdu_lock;
    296	struct list_head hba_queue;
    297#define BE_MAX_SESSION 2048
    298#define BE_INVALID_CID 0xffff
    299#define BE_SET_CID_TO_CRI(cri_index, cid) \
    300			  (phba->cid_to_cri_map[cid] = cri_index)
    301#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
    302	unsigned short cid_to_cri_map[BE_MAX_SESSION];
    303	struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
    304	struct iscsi_endpoint **ep_array;
    305	struct beiscsi_conn **conn_table;
    306	struct Scsi_Host *shost;
    307	struct iscsi_iface *ipv4_iface;
    308	struct iscsi_iface *ipv6_iface;
    309	struct {
    310		/**
    311		 * group together since they are used most frequently
    312		 * for cid to cri conversion
    313		 */
    314#define BEISCSI_PHYS_PORT_MAX	4
    315		unsigned int phys_port;
    316		/* valid values of phys_port id are 0, 1, 2, 3 */
    317		unsigned int eqid_count;
    318		unsigned int cqid_count;
    319		unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
    320#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
    321		(phba->fw_config.iscsi_cid_count[ulp_num])
    322		unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
    323		unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
    324		unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
    325		unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
    326		unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
    327
    328		unsigned short iscsi_features;
    329		uint16_t dual_ulp_aware;
    330		unsigned long ulp_supported;
    331	} fw_config;
    332
    333	unsigned long state;
    334#define BEISCSI_HBA_ONLINE	0
    335#define BEISCSI_HBA_LINK_UP	1
    336#define BEISCSI_HBA_BOOT_FOUND	2
    337#define BEISCSI_HBA_BOOT_WORK	3
    338#define BEISCSI_HBA_UER_SUPP	4
    339#define BEISCSI_HBA_PCI_ERR	5
    340#define BEISCSI_HBA_FW_TIMEOUT	6
    341#define BEISCSI_HBA_IN_UE	7
    342#define BEISCSI_HBA_IN_TPE	8
    343
    344/* error bits */
    345#define BEISCSI_HBA_IN_ERR	((1 << BEISCSI_HBA_PCI_ERR) | \
    346				 (1 << BEISCSI_HBA_FW_TIMEOUT) | \
    347				 (1 << BEISCSI_HBA_IN_UE) | \
    348				 (1 << BEISCSI_HBA_IN_TPE))
    349
    350	u8 optic_state;
    351	struct delayed_work eqd_update;
    352	/* update EQ delay timer every 1000ms */
    353#define BEISCSI_EQD_UPDATE_INTERVAL	1000
    354	struct timer_list hw_check;
    355	/* check for UE every 1000ms */
    356#define BEISCSI_UE_DETECT_INTERVAL	1000
    357	u32 ue2rp;
    358	struct delayed_work recover_port;
    359	struct work_struct sess_work;
    360
    361	bool mac_addr_set;
    362	u8 mac_address[ETH_ALEN];
    363	u8 port_name;
    364	u8 port_speed;
    365	char fw_ver_str[BEISCSI_VER_STRLEN];
    366	struct workqueue_struct *wq;	/* The actuak work queue */
    367	struct be_ctrl_info ctrl;
    368	unsigned int generation;
    369	unsigned int interface_handle;
    370
    371	struct be_aic_obj aic_obj[MAX_CPUS];
    372	unsigned int attr_log_enable;
    373	int (*iotask_fn)(struct iscsi_task *,
    374			struct scatterlist *sg,
    375			uint32_t num_sg, uint32_t xferlen,
    376			uint32_t writedir);
    377	struct boot_struct {
    378		int retry;
    379		unsigned int tag;
    380		unsigned int s_handle;
    381		struct be_dma_mem nonemb_cmd;
    382		enum {
    383			BEISCSI_BOOT_REOPEN_SESS = 1,
    384			BEISCSI_BOOT_GET_SHANDLE,
    385			BEISCSI_BOOT_GET_SINFO,
    386			BEISCSI_BOOT_LOGOUT_SESS,
    387			BEISCSI_BOOT_CREATE_KSET,
    388		} action;
    389		struct mgmt_session_info boot_sess;
    390		struct iscsi_boot_kset *boot_kset;
    391	} boot_struct;
    392	struct work_struct boot_work;
    393};
    394
    395#define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
    396#define beiscsi_hba_is_online(phba) \
    397	(!beiscsi_hba_in_error((phba)) && \
    398	 test_bit(BEISCSI_HBA_ONLINE, &phba->state))
    399
    400struct beiscsi_session {
    401	struct dma_pool *bhs_pool;
    402};
    403
    404/**
    405 * struct beiscsi_conn - iscsi connection structure
    406 */
    407struct beiscsi_conn {
    408	struct iscsi_conn *conn;
    409	struct beiscsi_hba *phba;
    410	u32 exp_statsn;
    411	u32 doorbell_offset;
    412	u32 beiscsi_conn_cid;
    413	struct beiscsi_endpoint *ep;
    414	unsigned short login_in_progress;
    415	struct wrb_handle *plogin_wrb_handle;
    416	struct sgl_handle *plogin_sgl_handle;
    417	struct beiscsi_session *beiscsi_sess;
    418	struct iscsi_task *task;
    419};
    420
    421/* This structure is used by the chip */
    422struct pdu_data_out {
    423	u32 dw[12];
    424};
    425/**
    426 * Pseudo amap definition in which each bit of the actual structure is defined
    427 * as a byte: used to calculate offset/shift/mask of each field
    428 */
    429struct amap_pdu_data_out {
    430	u8 opcode[6];		/* opcode */
    431	u8 rsvd0[2];		/* should be 0 */
    432	u8 rsvd1[7];
    433	u8 final_bit;		/* F bit */
    434	u8 rsvd2[16];
    435	u8 ahs_length[8];	/* no AHS */
    436	u8 data_len_hi[8];
    437	u8 data_len_lo[16];	/* DataSegmentLength */
    438	u8 lun[64];
    439	u8 itt[32];		/* ITT; initiator task tag */
    440	u8 ttt[32];		/* TTT; valid for R2T or 0xffffffff */
    441	u8 rsvd3[32];
    442	u8 exp_stat_sn[32];
    443	u8 rsvd4[32];
    444	u8 data_sn[32];
    445	u8 buffer_offset[32];
    446	u8 rsvd5[32];
    447};
    448
    449struct be_cmd_bhs {
    450	struct iscsi_scsi_req iscsi_hdr;
    451	unsigned char pad1[16];
    452	struct pdu_data_out iscsi_data_pdu;
    453	unsigned char pad2[BE_SENSE_INFO_SIZE -
    454			sizeof(struct pdu_data_out)];
    455};
    456
    457struct beiscsi_io_task {
    458	struct wrb_handle *pwrb_handle;
    459	struct sgl_handle *psgl_handle;
    460	struct beiscsi_conn *conn;
    461	struct scsi_cmnd *scsi_cmnd;
    462	int num_sg;
    463	struct hwi_wrb_context *pwrb_context;
    464	itt_t libiscsi_itt;
    465	struct be_cmd_bhs *cmd_bhs;
    466	struct be_bus_address bhs_pa;
    467	unsigned short bhs_len;
    468	dma_addr_t mtask_addr;
    469	uint32_t mtask_data_count;
    470	uint8_t wrb_type;
    471};
    472
    473struct be_nonio_bhs {
    474	struct iscsi_hdr iscsi_hdr;
    475	unsigned char pad1[16];
    476	struct pdu_data_out iscsi_data_pdu;
    477	unsigned char pad2[BE_SENSE_INFO_SIZE -
    478			sizeof(struct pdu_data_out)];
    479};
    480
    481struct be_status_bhs {
    482	struct iscsi_scsi_req iscsi_hdr;
    483	unsigned char pad1[16];
    484	/**
    485	 * The plus 2 below is to hold the sense info length that gets
    486	 * DMA'ed by RxULP
    487	 */
    488	unsigned char sense_info[BE_SENSE_INFO_SIZE];
    489};
    490
    491struct iscsi_sge {
    492	u32 dw[4];
    493};
    494
    495/**
    496 * Pseudo amap definition in which each bit of the actual structure is defined
    497 * as a byte: used to calculate offset/shift/mask of each field
    498 */
    499struct amap_iscsi_sge {
    500	u8 addr_hi[32];
    501	u8 addr_lo[32];
    502	u8 sge_offset[22];	/* DWORD 2 */
    503	u8 rsvd0[9];		/* DWORD 2 */
    504	u8 last_sge;		/* DWORD 2 */
    505	u8 len[17];		/* DWORD 3 */
    506	u8 rsvd1[15];		/* DWORD 3 */
    507};
    508
    509struct beiscsi_offload_params {
    510	u32 dw[6];
    511};
    512
    513#define OFFLD_PARAMS_ERL	0x00000003
    514#define OFFLD_PARAMS_DDE	0x00000004
    515#define OFFLD_PARAMS_HDE	0x00000008
    516#define OFFLD_PARAMS_IR2T	0x00000010
    517#define OFFLD_PARAMS_IMD	0x00000020
    518#define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
    519#define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
    520#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
    521
    522/**
    523 * Pseudo amap definition in which each bit of the actual structure is defined
    524 * as a byte: used to calculate offset/shift/mask of each field
    525 */
    526struct amap_beiscsi_offload_params {
    527	u8 max_burst_length[32];
    528	u8 max_send_data_segment_length[32];
    529	u8 first_burst_length[32];
    530	u8 erl[2];
    531	u8 dde[1];
    532	u8 hde[1];
    533	u8 ir2t[1];
    534	u8 imd[1];
    535	u8 data_seq_inorder[1];
    536	u8 pdu_seq_inorder[1];
    537	u8 max_r2t[16];
    538	u8 pad[8];
    539	u8 exp_statsn[32];
    540	u8 max_recv_data_segment_length[32];
    541};
    542
    543struct hd_async_handle {
    544	struct list_head link;
    545	struct be_bus_address pa;
    546	void *pbuffer;
    547	u32 buffer_len;
    548	u16 index;
    549	u16 cri;
    550	u8 is_header;
    551	u8 is_final;
    552	u8 in_use;
    553};
    554
    555#define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \
    556	(BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2)
    557
    558/**
    559 * This has list of async PDUs that are waiting to be processed.
    560 * Buffers live in this list for a brief duration before they get
    561 * processed and posted back to hardware.
    562 * Note that we don't really need one cri_wait_queue per async_entry.
    563 * We need one cri_wait_queue per CRI. Its easier to manage if this
    564 * is tagged along with the async_entry.
    565 */
    566struct hd_async_entry {
    567	struct cri_wait_queue {
    568		unsigned short hdr_len;
    569		unsigned int bytes_received;
    570		unsigned int bytes_needed;
    571		struct list_head list;
    572	} wq;
    573	/* handles posted to FW resides here */
    574	struct hd_async_handle *header;
    575	struct hd_async_handle *data;
    576};
    577
    578struct hd_async_buf_context {
    579	struct be_bus_address pa_base;
    580	void *va_base;
    581	void *ring_base;
    582	struct hd_async_handle *handle_base;
    583	u32 buffer_size;
    584	u16 pi;
    585};
    586
    587/**
    588 * hd_async_context is declared for each ULP supporting iSCSI function.
    589 */
    590struct hd_async_context {
    591	struct hd_async_buf_context async_header;
    592	struct hd_async_buf_context async_data;
    593	u16 num_entries;
    594	/**
    595	 * When unsol PDU is in, it needs to be chained till all the bytes are
    596	 * received and then processing is done. hd_async_entry is created
    597	 * based on the cid_count for each ULP. When unsol PDU comes in based
    598	 * on the conn_id it needs to be added to the correct async_entry wq.
    599	 * Below defined cid_to_async_cri_map is used to reterive the
    600	 * async_cri_map for a particular connection.
    601	 *
    602	 * This array is initialized after beiscsi_create_wrb_rings returns.
    603	 *
    604	 * - this method takes more memory space, fixed to 2K
    605	 * - any support for connections greater than this the array size needs
    606	 * to be incremented
    607	 */
    608#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
    609	unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
    610	/**
    611	 * This is a variable size array. Don`t add anything after this field!!
    612	 */
    613	struct hd_async_entry *async_entry;
    614};
    615
    616struct i_t_dpdu_cqe {
    617	u32 dw[4];
    618} __packed;
    619
    620/**
    621 * Pseudo amap definition in which each bit of the actual structure is defined
    622 * as a byte: used to calculate offset/shift/mask of each field
    623 */
    624struct amap_i_t_dpdu_cqe {
    625	u8 db_addr_hi[32];
    626	u8 db_addr_lo[32];
    627	u8 code[6];
    628	u8 cid[10];
    629	u8 dpl[16];
    630	u8 index[16];
    631	u8 num_cons[10];
    632	u8 rsvd0[4];
    633	u8 final;
    634	u8 valid;
    635} __packed;
    636
    637struct amap_i_t_dpdu_cqe_v2 {
    638	u8 db_addr_hi[32];  /* DWORD 0 */
    639	u8 db_addr_lo[32];  /* DWORD 1 */
    640	u8 code[6]; /* DWORD 2 */
    641	u8 num_cons; /* DWORD 2*/
    642	u8 rsvd0[8]; /* DWORD 2 */
    643	u8 dpl[17]; /* DWORD 2 */
    644	u8 index[16]; /* DWORD 3 */
    645	u8 cid[13]; /* DWORD 3 */
    646	u8 rsvd1; /* DWORD 3 */
    647	u8 final; /* DWORD 3 */
    648	u8 valid; /* DWORD 3 */
    649} __packed;
    650
    651#define CQE_VALID_MASK	0x80000000
    652#define CQE_CODE_MASK	0x0000003F
    653#define CQE_CID_MASK	0x0000FFC0
    654
    655#define EQE_VALID_MASK		0x00000001
    656#define EQE_MAJORCODE_MASK	0x0000000E
    657#define EQE_RESID_MASK		0xFFFF0000
    658
    659struct be_eq_entry {
    660	u32 dw[1];
    661} __packed;
    662
    663/**
    664 * Pseudo amap definition in which each bit of the actual structure is defined
    665 * as a byte: used to calculate offset/shift/mask of each field
    666 */
    667struct amap_eq_entry {
    668	u8 valid;		/* DWORD 0 */
    669	u8 major_code[3];	/* DWORD 0 */
    670	u8 minor_code[12];	/* DWORD 0 */
    671	u8 resource_id[16];	/* DWORD 0 */
    672
    673} __packed;
    674
    675struct cq_db {
    676	u32 dw[1];
    677} __packed;
    678
    679/**
    680 * Pseudo amap definition in which each bit of the actual structure is defined
    681 * as a byte: used to calculate offset/shift/mask of each field
    682 */
    683struct amap_cq_db {
    684	u8 qid[10];
    685	u8 event[1];
    686	u8 rsvd0[5];
    687	u8 num_popped[13];
    688	u8 rearm[1];
    689	u8 rsvd1[2];
    690} __packed;
    691
    692void beiscsi_process_eq(struct beiscsi_hba *phba);
    693
    694struct iscsi_wrb {
    695	u32 dw[16];
    696} __packed;
    697
    698#define WRB_TYPE_MASK 0xF0000000
    699#define SKH_WRB_TYPE_OFFSET 27
    700#define BE_WRB_TYPE_OFFSET  28
    701
    702#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
    703		(pwrb->dw[0] |= (wrb_type << type_offset))
    704
    705/**
    706 * Pseudo amap definition in which each bit of the actual structure is defined
    707 * as a byte: used to calculate offset/shift/mask of each field
    708 */
    709struct amap_iscsi_wrb {
    710	u8 lun[14];		/* DWORD 0 */
    711	u8 lt;			/* DWORD 0 */
    712	u8 invld;		/* DWORD 0 */
    713	u8 wrb_idx[8];		/* DWORD 0 */
    714	u8 dsp;			/* DWORD 0 */
    715	u8 dmsg;		/* DWORD 0 */
    716	u8 undr_run;		/* DWORD 0 */
    717	u8 over_run;		/* DWORD 0 */
    718	u8 type[4];		/* DWORD 0 */
    719	u8 ptr2nextwrb[8];	/* DWORD 1 */
    720	u8 r2t_exp_dtl[24];	/* DWORD 1 */
    721	u8 sgl_icd_idx[12];	/* DWORD 2 */
    722	u8 rsvd0[20];		/* DWORD 2 */
    723	u8 exp_data_sn[32];	/* DWORD 3 */
    724	u8 iscsi_bhs_addr_hi[32];	/* DWORD 4 */
    725	u8 iscsi_bhs_addr_lo[32];	/* DWORD 5 */
    726	u8 cmdsn_itt[32];	/* DWORD 6 */
    727	u8 dif_ref_tag[32];	/* DWORD 7 */
    728	u8 sge0_addr_hi[32];	/* DWORD 8 */
    729	u8 sge0_addr_lo[32];	/* DWORD 9  */
    730	u8 sge0_offset[22];	/* DWORD 10 */
    731	u8 pbs;			/* DWORD 10 */
    732	u8 dif_mode[2];		/* DWORD 10 */
    733	u8 rsvd1[6];		/* DWORD 10 */
    734	u8 sge0_last;		/* DWORD 10 */
    735	u8 sge0_len[17];	/* DWORD 11 */
    736	u8 dif_meta_tag[14];	/* DWORD 11 */
    737	u8 sge0_in_ddr;		/* DWORD 11 */
    738	u8 sge1_addr_hi[32];	/* DWORD 12 */
    739	u8 sge1_addr_lo[32];	/* DWORD 13 */
    740	u8 sge1_r2t_offset[22];	/* DWORD 14 */
    741	u8 rsvd2[9];		/* DWORD 14 */
    742	u8 sge1_last;		/* DWORD 14 */
    743	u8 sge1_len[17];	/* DWORD 15 */
    744	u8 ref_sgl_icd_idx[12];	/* DWORD 15 */
    745	u8 rsvd3[2];		/* DWORD 15 */
    746	u8 sge1_in_ddr;		/* DWORD 15 */
    747
    748} __packed;
    749
    750struct amap_iscsi_wrb_v2 {
    751	u8 r2t_exp_dtl[25]; /* DWORD 0 */
    752	u8 rsvd0[2];    /* DWORD 0*/
    753	u8 type[5];     /* DWORD 0 */
    754	u8 ptr2nextwrb[8];  /* DWORD 1 */
    755	u8 wrb_idx[8];      /* DWORD 1 */
    756	u8 lun[16];     /* DWORD 1 */
    757	u8 sgl_idx[16]; /* DWORD 2 */
    758	u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
    759	u8 exp_data_sn[32]; /* DWORD 3 */
    760	u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
    761	u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
    762	u8 cq_id[16];   /* DWORD 6 */
    763	u8 rsvd1[16];   /* DWORD 6 */
    764	u8 cmdsn_itt[32];   /* DWORD 7 */
    765	u8 sge0_addr_hi[32];    /* DWORD 8 */
    766	u8 sge0_addr_lo[32];    /* DWORD 9 */
    767	u8 sge0_offset[24]; /* DWORD 10 */
    768	u8 rsvd2[7];    /* DWORD 10 */
    769	u8 sge0_last;   /* DWORD 10 */
    770	u8 sge0_len[17];    /* DWORD 11 */
    771	u8 rsvd3[7];    /* DWORD 11 */
    772	u8 diff_enbl;   /* DWORD 11 */
    773	u8 u_run;       /* DWORD 11 */
    774	u8 o_run;       /* DWORD 11 */
    775	u8 invld;     /* DWORD 11 */
    776	u8 dsp;         /* DWORD 11 */
    777	u8 dmsg;        /* DWORD 11 */
    778	u8 rsvd4;       /* DWORD 11 */
    779	u8 lt;          /* DWORD 11 */
    780	u8 sge1_addr_hi[32];    /* DWORD 12 */
    781	u8 sge1_addr_lo[32];    /* DWORD 13 */
    782	u8 sge1_r2t_offset[24]; /* DWORD 14 */
    783	u8 rsvd5[7];    /* DWORD 14 */
    784	u8 sge1_last;   /* DWORD 14 */
    785	u8 sge1_len[17];    /* DWORD 15 */
    786	u8 rsvd6[15];   /* DWORD 15 */
    787} __packed;
    788
    789
    790struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
    791				     struct hwi_wrb_context **pcontext);
    792void
    793free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
    794
    795void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
    796				     struct iscsi_task *task);
    797
    798void hwi_ring_cq_db(struct beiscsi_hba *phba,
    799		     unsigned int id, unsigned int num_processed,
    800		     unsigned char rearm);
    801
    802unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
    803void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
    804
    805struct pdu_nop_out {
    806	u32 dw[12];
    807};
    808
    809/**
    810 * Pseudo amap definition in which each bit of the actual structure is defined
    811 * as a byte: used to calculate offset/shift/mask of each field
    812 */
    813struct amap_pdu_nop_out {
    814	u8 opcode[6];		/* opcode 0x00 */
    815	u8 i_bit;		/* I Bit */
    816	u8 x_bit;		/* reserved; should be 0 */
    817	u8 fp_bit_filler1[7];
    818	u8 f_bit;		/* always 1 */
    819	u8 reserved1[16];
    820	u8 ahs_length[8];	/* no AHS */
    821	u8 data_len_hi[8];
    822	u8 data_len_lo[16];	/* DataSegmentLength */
    823	u8 lun[64];
    824	u8 itt[32];		/* initiator id for ping or 0xffffffff */
    825	u8 ttt[32];		/* target id for ping or 0xffffffff */
    826	u8 cmd_sn[32];
    827	u8 exp_stat_sn[32];
    828	u8 reserved5[128];
    829};
    830
    831#define PDUBASE_OPCODE_MASK	0x0000003F
    832#define PDUBASE_DATALENHI_MASK	0x0000FF00
    833#define PDUBASE_DATALENLO_MASK	0xFFFF0000
    834
    835struct pdu_base {
    836	u32 dw[16];
    837} __packed;
    838
    839/**
    840 * Pseudo amap definition in which each bit of the actual structure is defined
    841 * as a byte: used to calculate offset/shift/mask of each field
    842 */
    843struct amap_pdu_base {
    844	u8 opcode[6];
    845	u8 i_bit;		/* immediate bit */
    846	u8 x_bit;		/* reserved, always 0 */
    847	u8 reserved1[24];	/* opcode-specific fields */
    848	u8 ahs_length[8];	/* length units is 4 byte words */
    849	u8 data_len_hi[8];
    850	u8 data_len_lo[16];	/* DatasegmentLength */
    851	u8 lun[64];		/* lun or opcode-specific fields */
    852	u8 itt[32];		/* initiator task tag */
    853	u8 reserved4[224];
    854};
    855
    856struct iscsi_target_context_update_wrb {
    857	u32 dw[16];
    858} __packed;
    859
    860/**
    861 * Pseudo amap definition in which each bit of the actual structure is defined
    862 * as a byte: used to calculate offset/shift/mask of each field
    863 */
    864#define BE_TGT_CTX_UPDT_CMD 0x07
    865struct amap_iscsi_target_context_update_wrb {
    866	u8 lun[14];		/* DWORD 0 */
    867	u8 lt;			/* DWORD 0 */
    868	u8 invld;		/* DWORD 0 */
    869	u8 wrb_idx[8];		/* DWORD 0 */
    870	u8 dsp;			/* DWORD 0 */
    871	u8 dmsg;		/* DWORD 0 */
    872	u8 undr_run;		/* DWORD 0 */
    873	u8 over_run;		/* DWORD 0 */
    874	u8 type[4];		/* DWORD 0 */
    875	u8 ptr2nextwrb[8];	/* DWORD 1 */
    876	u8 max_burst_length[19];	/* DWORD 1 */
    877	u8 rsvd0[5];		/* DWORD 1 */
    878	u8 rsvd1[15];		/* DWORD 2 */
    879	u8 max_send_data_segment_length[17];	/* DWORD 2 */
    880	u8 first_burst_length[14];	/* DWORD 3 */
    881	u8 rsvd2[2];		/* DWORD 3 */
    882	u8 tx_wrbindex_drv_msg[8];	/* DWORD 3 */
    883	u8 rsvd3[5];		/* DWORD 3 */
    884	u8 session_state[3];	/* DWORD 3 */
    885	u8 rsvd4[16];		/* DWORD 4 */
    886	u8 tx_jumbo;		/* DWORD 4 */
    887	u8 hde;			/* DWORD 4 */
    888	u8 dde;			/* DWORD 4 */
    889	u8 erl[2];		/* DWORD 4 */
    890	u8 domain_id[5];		/* DWORD 4 */
    891	u8 mode;		/* DWORD 4 */
    892	u8 imd;			/* DWORD 4 */
    893	u8 ir2t;		/* DWORD 4 */
    894	u8 notpredblq[2];	/* DWORD 4 */
    895	u8 compltonack;		/* DWORD 4 */
    896	u8 stat_sn[32];		/* DWORD 5 */
    897	u8 pad_buffer_addr_hi[32];	/* DWORD 6 */
    898	u8 pad_buffer_addr_lo[32];	/* DWORD 7 */
    899	u8 pad_addr_hi[32];	/* DWORD 8 */
    900	u8 pad_addr_lo[32];	/* DWORD 9 */
    901	u8 rsvd5[32];		/* DWORD 10 */
    902	u8 rsvd6[32];		/* DWORD 11 */
    903	u8 rsvd7[32];		/* DWORD 12 */
    904	u8 rsvd8[32];		/* DWORD 13 */
    905	u8 rsvd9[32];		/* DWORD 14 */
    906	u8 rsvd10[32];		/* DWORD 15 */
    907
    908} __packed;
    909
    910#define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
    911#define BEISCSI_MAX_CXNS    1
    912struct amap_iscsi_target_context_update_wrb_v2 {
    913	u8 max_burst_length[24];    /* DWORD 0 */
    914	u8 rsvd0[3];    /* DWORD 0 */
    915	u8 type[5];     /* DWORD 0 */
    916	u8 ptr2nextwrb[8];  /* DWORD 1 */
    917	u8 wrb_idx[8];      /* DWORD 1 */
    918	u8 rsvd1[16];       /* DWORD 1 */
    919	u8 max_send_data_segment_length[24];    /* DWORD 2 */
    920	u8 rsvd2[8];    /* DWORD 2 */
    921	u8 first_burst_length[24]; /* DWORD 3 */
    922	u8 rsvd3[8]; /* DOWRD 3 */
    923	u8 max_r2t[16]; /* DWORD 4 */
    924	u8 rsvd4;       /* DWORD 4 */
    925	u8 hde;         /* DWORD 4 */
    926	u8 dde;         /* DWORD 4 */
    927	u8 erl[2];      /* DWORD 4 */
    928	u8 rsvd5[6];    /* DWORD 4 */
    929	u8 imd;         /* DWORD 4 */
    930	u8 ir2t;        /* DWORD 4 */
    931	u8 rsvd6[3];    /* DWORD 4 */
    932	u8 stat_sn[32];     /* DWORD 5 */
    933	u8 rsvd7[32];   /* DWORD 6 */
    934	u8 rsvd8[32];   /* DWORD 7 */
    935	u8 max_recv_dataseg_len[24];    /* DWORD 8 */
    936	u8 rsvd9[8]; /* DWORD 8 */
    937	u8 rsvd10[32];   /* DWORD 9 */
    938	u8 rsvd11[32];   /* DWORD 10 */
    939	u8 max_cxns[16]; /* DWORD 11 */
    940	u8 rsvd12[11]; /* DWORD  11*/
    941	u8 invld; /* DWORD 11 */
    942	u8 rsvd13;/* DWORD 11*/
    943	u8 dmsg; /* DWORD 11 */
    944	u8 data_seq_inorder; /* DWORD 11 */
    945	u8 pdu_seq_inorder; /* DWORD 11 */
    946	u8 rsvd14[32]; /*DWORD 12 */
    947	u8 rsvd15[32]; /* DWORD 13 */
    948	u8 rsvd16[32]; /* DWORD 14 */
    949	u8 rsvd17[32]; /* DWORD 15 */
    950} __packed;
    951
    952
    953struct be_ring {
    954	u32 pages;		/* queue size in pages */
    955	u32 id;			/* queue id assigned by beklib */
    956	u32 num;		/* number of elements in queue */
    957	u32 cidx;		/* consumer index */
    958	u32 pidx;		/* producer index -- not used by most rings */
    959	u32 item_size;		/* size in bytes of one object */
    960	u8 ulp_num;	/* ULP to which CID binded */
    961	u16 register_set;
    962	u16 doorbell_format;
    963	u32 doorbell_offset;
    964
    965	void *va;		/* The virtual address of the ring.  This
    966				 * should be last to allow 32 & 64 bit debugger
    967				 * extensions to work.
    968				 */
    969};
    970
    971struct hwi_controller {
    972	struct hwi_wrb_context *wrb_context;
    973	struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
    974	struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
    975	struct hwi_context_memory *phwi_ctxt;
    976};
    977
    978enum hwh_type_enum {
    979	HWH_TYPE_IO = 1,
    980	HWH_TYPE_LOGOUT = 2,
    981	HWH_TYPE_TMF = 3,
    982	HWH_TYPE_NOP = 4,
    983	HWH_TYPE_IO_RD = 5,
    984	HWH_TYPE_LOGIN = 11,
    985	HWH_TYPE_INVALID = 0xFFFFFFFF
    986};
    987
    988struct wrb_handle {
    989	unsigned short wrb_index;
    990	struct iscsi_task *pio_handle;
    991	struct iscsi_wrb *pwrb;
    992};
    993
    994struct hwi_context_memory {
    995	struct be_eq_obj be_eq[MAX_CPUS];
    996	struct be_queue_info be_cq[MAX_CPUS - 1];
    997
    998	struct be_queue_info *be_wrbq;
    999	/**
   1000	 * Create array of ULP number for below entries as DEFQ
   1001	 * will be created for both ULP if iSCSI Protocol is
   1002	 * loaded on both ULP.
   1003	 */
   1004	struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
   1005	struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
   1006	struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
   1007};
   1008
   1009void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
   1010
   1011/* Logging related definitions */
   1012#define BEISCSI_LOG_INIT	0x0001	/* Initialization events */
   1013#define BEISCSI_LOG_MBOX	0x0002	/* Mailbox Events */
   1014#define BEISCSI_LOG_MISC	0x0004	/* Miscllaneous Events */
   1015#define BEISCSI_LOG_EH		0x0008	/* Error Handler */
   1016#define BEISCSI_LOG_IO		0x0010	/* IO Code Path */
   1017#define BEISCSI_LOG_CONFIG	0x0020	/* CONFIG Code Path */
   1018#define BEISCSI_LOG_ISCSI	0x0040	/* SCSI/iSCSI Protocol related Logs */
   1019
   1020#define __beiscsi_log(phba, level, fmt, arg...) \
   1021	shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
   1022
   1023#define beiscsi_log(phba, level, mask, fmt, arg...) \
   1024do { \
   1025	uint32_t log_value = phba->attr_log_enable; \
   1026		if (((mask) & log_value) || (level[1] <= '3')) \
   1027			__beiscsi_log(phba, level, fmt, ##arg); \
   1028} while (0);
   1029
   1030#endif