cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

common.h (9244B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * CXL Flash Device Driver
      4 *
      5 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
      6 *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
      7 *
      8 * Copyright (C) 2015 IBM Corporation
      9 */
     10
     11#ifndef _CXLFLASH_COMMON_H
     12#define _CXLFLASH_COMMON_H
     13
     14#include <linux/async.h>
     15#include <linux/cdev.h>
     16#include <linux/irq_poll.h>
     17#include <linux/list.h>
     18#include <linux/rwsem.h>
     19#include <linux/types.h>
     20#include <scsi/scsi.h>
     21#include <scsi/scsi_cmnd.h>
     22#include <scsi/scsi_device.h>
     23
     24#include "backend.h"
     25
     26extern const struct file_operations cxlflash_cxl_fops;
     27
     28#define MAX_CONTEXT	CXLFLASH_MAX_CONTEXT	/* num contexts per afu */
     29#define MAX_FC_PORTS	CXLFLASH_MAX_FC_PORTS	/* max ports per AFU */
     30#define LEGACY_FC_PORTS	2			/* legacy ports per AFU */
     31
     32#define CHAN2PORTBANK(_x)	((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
     33#define CHAN2BANKPORT(_x)	((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
     34
     35#define CHAN2PORTMASK(_x)	(1 << (_x))	/* channel to port mask */
     36#define PORTMASK2CHAN(_x)	(ilog2((_x)))	/* port mask to channel */
     37#define PORTNUM2CHAN(_x)	((_x) - 1)	/* port number to channel */
     38
     39#define CXLFLASH_BLOCK_SIZE	4096		/* 4K blocks */
     40#define CXLFLASH_MAX_XFER_SIZE	16777216	/* 16MB transfer */
     41#define CXLFLASH_MAX_SECTORS	(CXLFLASH_MAX_XFER_SIZE/512)	/* SCSI wants
     42								 * max_sectors
     43								 * in units of
     44								 * 512 byte
     45								 * sectors
     46								 */
     47
     48#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
     49
     50/* AFU command retry limit */
     51#define MC_RETRY_CNT	5	/* Sufficient for SCSI and certain AFU errors */
     52
     53/* Command management definitions */
     54#define CXLFLASH_MAX_CMDS               256
     55#define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS
     56
     57/* RRQ for master issued cmds */
     58#define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS
     59
     60/* SQ for master issued cmds */
     61#define NUM_SQ_ENTRY			CXLFLASH_MAX_CMDS
     62
     63/* Hardware queue definitions */
     64#define CXLFLASH_DEF_HWQS		1
     65#define CXLFLASH_MAX_HWQS		8
     66#define PRIMARY_HWQ			0
     67
     68
     69static inline void check_sizes(void)
     70{
     71	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
     72	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
     73}
     74
     75/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
     76#define CMD_BUFSIZE     SIZE_4K
     77
     78enum cxlflash_lr_state {
     79	LINK_RESET_INVALID,
     80	LINK_RESET_REQUIRED,
     81	LINK_RESET_COMPLETE
     82};
     83
     84enum cxlflash_init_state {
     85	INIT_STATE_NONE,
     86	INIT_STATE_PCI,
     87	INIT_STATE_AFU,
     88	INIT_STATE_SCSI,
     89	INIT_STATE_CDEV
     90};
     91
     92enum cxlflash_state {
     93	STATE_PROBING,	/* Initial state during probe */
     94	STATE_PROBED,	/* Temporary state, probe completed but EEH occurred */
     95	STATE_NORMAL,	/* Normal running state, everything good */
     96	STATE_RESET,	/* Reset state, trying to reset/recover */
     97	STATE_FAILTERM	/* Failed/terminating state, error out users/threads */
     98};
     99
    100enum cxlflash_hwq_mode {
    101	HWQ_MODE_RR,	/* Roundrobin (default) */
    102	HWQ_MODE_TAG,	/* Distribute based on block MQ tag */
    103	HWQ_MODE_CPU,	/* CPU affinity */
    104	MAX_HWQ_MODE
    105};
    106
    107/*
    108 * Each context has its own set of resource handles that is visible
    109 * only from that context.
    110 */
    111
    112struct cxlflash_cfg {
    113	struct afu *afu;
    114
    115	const struct cxlflash_backend_ops *ops;
    116	struct pci_dev *dev;
    117	struct pci_device_id *dev_id;
    118	struct Scsi_Host *host;
    119	int num_fc_ports;
    120	struct cdev cdev;
    121	struct device *chardev;
    122
    123	ulong cxlflash_regs_pci;
    124
    125	struct work_struct work_q;
    126	enum cxlflash_init_state init_state;
    127	enum cxlflash_lr_state lr_state;
    128	int lr_port;
    129	atomic_t scan_host_needed;
    130
    131	void *afu_cookie;
    132
    133	atomic_t recovery_threads;
    134	struct mutex ctx_recovery_mutex;
    135	struct mutex ctx_tbl_list_mutex;
    136	struct rw_semaphore ioctl_rwsem;
    137	struct ctx_info *ctx_tbl[MAX_CONTEXT];
    138	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
    139	struct file_operations cxl_fops;
    140
    141	/* Parameters that are LUN table related */
    142	int last_lun_index[MAX_FC_PORTS];
    143	int promote_lun_index;
    144	struct list_head lluns; /* list of llun_info structs */
    145
    146	wait_queue_head_t tmf_waitq;
    147	spinlock_t tmf_slock;
    148	bool tmf_active;
    149	bool ws_unmap;		/* Write-same unmap supported */
    150	wait_queue_head_t reset_waitq;
    151	enum cxlflash_state state;
    152	async_cookie_t async_reset_cookie;
    153};
    154
    155struct afu_cmd {
    156	struct sisl_ioarcb rcb;	/* IOARCB (cache line aligned) */
    157	struct sisl_ioasa sa;	/* IOASA must follow IOARCB */
    158	struct afu *parent;
    159	struct scsi_cmnd *scp;
    160	struct completion cevent;
    161	struct list_head queue;
    162	u32 hwq_index;
    163
    164	u8 cmd_tmf:1,
    165	   cmd_aborted:1;
    166
    167	struct list_head list;	/* Pending commands link */
    168
    169	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
    170	 * However for performance reasons the IOARCB/IOASA should be
    171	 * cache line aligned.
    172	 */
    173} __aligned(cache_line_size());
    174
    175static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
    176{
    177	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
    178}
    179
    180static inline struct afu_cmd *sc_to_afuci(struct scsi_cmnd *sc)
    181{
    182	struct afu_cmd *afuc = sc_to_afuc(sc);
    183
    184	INIT_LIST_HEAD(&afuc->queue);
    185	return afuc;
    186}
    187
    188static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
    189{
    190	struct afu_cmd *afuc = sc_to_afuc(sc);
    191
    192	memset(afuc, 0, sizeof(*afuc));
    193	return sc_to_afuci(sc);
    194}
    195
    196struct hwq {
    197	/* Stuff requiring alignment go first. */
    198	struct sisl_ioarcb sq[NUM_SQ_ENTRY];		/* 16K SQ */
    199	u64 rrq_entry[NUM_RRQ_ENTRY];			/* 2K RRQ */
    200
    201	/* Beware of alignment till here. Preferably introduce new
    202	 * fields after this point
    203	 */
    204	struct afu *afu;
    205	void *ctx_cookie;
    206	struct sisl_host_map __iomem *host_map;		/* MC host map */
    207	struct sisl_ctrl_map __iomem *ctrl_map;		/* MC control map */
    208	ctx_hndl_t ctx_hndl;	/* master's context handle */
    209	u32 index;		/* Index of this hwq */
    210	int num_irqs;		/* Number of interrupts requested for context */
    211	struct list_head pending_cmds;	/* Commands pending completion */
    212
    213	atomic_t hsq_credits;
    214	spinlock_t hsq_slock;	/* Hardware send queue lock */
    215	struct sisl_ioarcb *hsq_start;
    216	struct sisl_ioarcb *hsq_end;
    217	struct sisl_ioarcb *hsq_curr;
    218	spinlock_t hrrq_slock;
    219	u64 *hrrq_start;
    220	u64 *hrrq_end;
    221	u64 *hrrq_curr;
    222	bool toggle;
    223	bool hrrq_online;
    224
    225	s64 room;
    226
    227	struct irq_poll irqpoll;
    228} __aligned(cache_line_size());
    229
    230struct afu {
    231	struct hwq hwqs[CXLFLASH_MAX_HWQS];
    232	int (*send_cmd)(struct afu *afu, struct afu_cmd *cmd);
    233	int (*context_reset)(struct hwq *hwq);
    234
    235	/* AFU HW */
    236	struct cxlflash_afu_map __iomem *afu_map;	/* entire MMIO map */
    237
    238	atomic_t cmds_active;	/* Number of currently active AFU commands */
    239	struct mutex sync_active;	/* Mutex to serialize AFU commands */
    240	u64 hb;
    241	u32 internal_lun;	/* User-desired LUN mode for this AFU */
    242
    243	u32 num_hwqs;		/* Number of hardware queues */
    244	u32 desired_hwqs;	/* Desired h/w queues, effective on AFU reset */
    245	enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
    246	u32 hwq_rr_count;	/* Count to distribute traffic for roundrobin */
    247
    248	char version[16];
    249	u64 interface_version;
    250
    251	u32 irqpoll_weight;
    252	struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
    253};
    254
    255static inline struct hwq *get_hwq(struct afu *afu, u32 index)
    256{
    257	WARN_ON(index >= CXLFLASH_MAX_HWQS);
    258
    259	return &afu->hwqs[index];
    260}
    261
    262static inline bool afu_is_irqpoll_enabled(struct afu *afu)
    263{
    264	return !!afu->irqpoll_weight;
    265}
    266
    267static inline bool afu_has_cap(struct afu *afu, u64 cap)
    268{
    269	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
    270
    271	return afu_cap & cap;
    272}
    273
    274static inline bool afu_is_ocxl_lisn(struct afu *afu)
    275{
    276	return afu_has_cap(afu, SISL_INTVER_CAP_OCXL_LISN);
    277}
    278
    279static inline bool afu_is_afu_debug(struct afu *afu)
    280{
    281	return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
    282}
    283
    284static inline bool afu_is_lun_provision(struct afu *afu)
    285{
    286	return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
    287}
    288
    289static inline bool afu_is_sq_cmd_mode(struct afu *afu)
    290{
    291	return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
    292}
    293
    294static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
    295{
    296	return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
    297}
    298
    299static inline u64 lun_to_lunid(u64 lun)
    300{
    301	__be64 lun_id;
    302
    303	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
    304	return be64_to_cpu(lun_id);
    305}
    306
    307static inline struct fc_port_bank __iomem *get_fc_port_bank(
    308					    struct cxlflash_cfg *cfg, int i)
    309{
    310	struct afu *afu = cfg->afu;
    311
    312	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
    313}
    314
    315static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
    316{
    317	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
    318
    319	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
    320}
    321
    322static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
    323{
    324	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
    325
    326	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
    327}
    328
    329int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
    330void cxlflash_list_init(void);
    331void cxlflash_term_global_luns(void);
    332void cxlflash_free_errpage(void);
    333int cxlflash_ioctl(struct scsi_device *sdev, unsigned int cmd,
    334		   void __user *arg);
    335void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
    336int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
    337void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
    338void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
    339
    340#endif /* ifndef _CXLFLASH_COMMON_H */