cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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vnic_cq.c (2760B)

      1/*
      2 * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
      3 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
      4 *
      5 * This program is free software; you may redistribute it and/or modify
      6 * it under the terms of the GNU General Public License as published by
      7 * the Free Software Foundation; version 2 of the License.
      8 *
      9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     16 * SOFTWARE.
     17 */
     18#include <linux/errno.h>
     19#include <linux/types.h>
     20#include <linux/pci.h>
     21#include "vnic_dev.h"
     22#include "vnic_cq.h"
     23
     24void vnic_cq_free(struct vnic_cq *cq)
     25{
     26	vnic_dev_free_desc_ring(cq->vdev, &cq->ring);
     27
     28	cq->ctrl = NULL;
     29}
     30
     31int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,
     32	unsigned int desc_count, unsigned int desc_size)
     33{
     34	int err;
     35
     36	cq->index = index;
     37	cq->vdev = vdev;
     38
     39	cq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index);
     40	if (!cq->ctrl) {
     41		printk(KERN_ERR "Failed to hook CQ[%d] resource\n", index);
     42		return -EINVAL;
     43	}
     44
     45	err = vnic_dev_alloc_desc_ring(vdev, &cq->ring, desc_count, desc_size);
     46	if (err)
     47		return err;
     48
     49	return 0;
     50}
     51
     52void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
     53	unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
     54	unsigned int cq_tail_color, unsigned int interrupt_enable,
     55	unsigned int cq_entry_enable, unsigned int cq_message_enable,
     56	unsigned int interrupt_offset, u64 cq_message_addr)
     57{
     58	u64 paddr;
     59
     60	paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;
     61	writeq(paddr, &cq->ctrl->ring_base);
     62	iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size);
     63	iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable);
     64	iowrite32(color_enable, &cq->ctrl->color_enable);
     65	iowrite32(cq_head, &cq->ctrl->cq_head);
     66	iowrite32(cq_tail, &cq->ctrl->cq_tail);
     67	iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color);
     68	iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable);
     69	iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable);
     70	iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable);
     71	iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset);
     72	writeq(cq_message_addr, &cq->ctrl->cq_message_addr);
     73}
     74
     75void vnic_cq_clean(struct vnic_cq *cq)
     76{
     77	cq->to_clean = 0;
     78	cq->last_color = 0;
     79
     80	iowrite32(0, &cq->ctrl->cq_head);
     81	iowrite32(0, &cq->ctrl->cq_tail);
     82	iowrite32(1, &cq->ctrl->cq_tail_color);
     83
     84	vnic_dev_clear_desc_ring(&cq->ring);
     85}