cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hisi_sas_v2_hw.c (108883B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (c) 2016 Linaro Ltd.
      4 * Copyright (c) 2016 Hisilicon Limited.
      5 */
      6
      7#include "hisi_sas.h"
      8#define DRV_NAME "hisi_sas_v2_hw"
      9
     10/* global registers need init*/
     11#define DLVRY_QUEUE_ENABLE		0x0
     12#define IOST_BASE_ADDR_LO		0x8
     13#define IOST_BASE_ADDR_HI		0xc
     14#define ITCT_BASE_ADDR_LO		0x10
     15#define ITCT_BASE_ADDR_HI		0x14
     16#define IO_BROKEN_MSG_ADDR_LO		0x18
     17#define IO_BROKEN_MSG_ADDR_HI		0x1c
     18#define PHY_CONTEXT			0x20
     19#define PHY_STATE			0x24
     20#define PHY_PORT_NUM_MA			0x28
     21#define PORT_STATE			0x2c
     22#define PORT_STATE_PHY8_PORT_NUM_OFF	16
     23#define PORT_STATE_PHY8_PORT_NUM_MSK	(0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
     24#define PORT_STATE_PHY8_CONN_RATE_OFF	20
     25#define PORT_STATE_PHY8_CONN_RATE_MSK	(0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
     26#define PHY_CONN_RATE			0x30
     27#define HGC_TRANS_TASK_CNT_LIMIT	0x38
     28#define AXI_AHB_CLK_CFG			0x3c
     29#define ITCT_CLR			0x44
     30#define ITCT_CLR_EN_OFF			16
     31#define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
     32#define ITCT_DEV_OFF			0
     33#define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
     34#define AXI_USER1			0x48
     35#define AXI_USER2			0x4c
     36#define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
     37#define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
     38#define SATA_INITI_D2H_STORE_ADDR_LO	0x60
     39#define SATA_INITI_D2H_STORE_ADDR_HI	0x64
     40#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
     41#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
     42#define HGC_GET_ITV_TIME		0x90
     43#define DEVICE_MSG_WORK_MODE		0x94
     44#define OPENA_WT_CONTI_TIME		0x9c
     45#define I_T_NEXUS_LOSS_TIME		0xa0
     46#define MAX_CON_TIME_LIMIT_TIME		0xa4
     47#define BUS_INACTIVE_LIMIT_TIME		0xa8
     48#define REJECT_TO_OPEN_LIMIT_TIME	0xac
     49#define CFG_AGING_TIME			0xbc
     50#define HGC_DFX_CFG2			0xc0
     51#define HGC_IOMB_PROC1_STATUS	0x104
     52#define CFG_1US_TIMER_TRSH		0xcc
     53#define HGC_LM_DFX_STATUS2		0x128
     54#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF		0
     55#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK	(0xfff << \
     56					 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
     57#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF		12
     58#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK	(0x7ff << \
     59					 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
     60#define HGC_CQE_ECC_ADDR		0x13c
     61#define HGC_CQE_ECC_1B_ADDR_OFF	0
     62#define HGC_CQE_ECC_1B_ADDR_MSK	(0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
     63#define HGC_CQE_ECC_MB_ADDR_OFF	8
     64#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
     65#define HGC_IOST_ECC_ADDR		0x140
     66#define HGC_IOST_ECC_1B_ADDR_OFF	0
     67#define HGC_IOST_ECC_1B_ADDR_MSK	(0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
     68#define HGC_IOST_ECC_MB_ADDR_OFF	16
     69#define HGC_IOST_ECC_MB_ADDR_MSK	(0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
     70#define HGC_DQE_ECC_ADDR		0x144
     71#define HGC_DQE_ECC_1B_ADDR_OFF	0
     72#define HGC_DQE_ECC_1B_ADDR_MSK	(0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
     73#define HGC_DQE_ECC_MB_ADDR_OFF	16
     74#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
     75#define HGC_INVLD_DQE_INFO		0x148
     76#define HGC_INVLD_DQE_INFO_FB_CH0_OFF	9
     77#define HGC_INVLD_DQE_INFO_FB_CH0_MSK	(0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
     78#define HGC_INVLD_DQE_INFO_FB_CH3_OFF	18
     79#define HGC_ITCT_ECC_ADDR		0x150
     80#define HGC_ITCT_ECC_1B_ADDR_OFF		0
     81#define HGC_ITCT_ECC_1B_ADDR_MSK		(0x3ff << \
     82						 HGC_ITCT_ECC_1B_ADDR_OFF)
     83#define HGC_ITCT_ECC_MB_ADDR_OFF		16
     84#define HGC_ITCT_ECC_MB_ADDR_MSK		(0x3ff << \
     85						 HGC_ITCT_ECC_MB_ADDR_OFF)
     86#define HGC_AXI_FIFO_ERR_INFO	0x154
     87#define AXI_ERR_INFO_OFF		0
     88#define AXI_ERR_INFO_MSK		(0xff << AXI_ERR_INFO_OFF)
     89#define FIFO_ERR_INFO_OFF		8
     90#define FIFO_ERR_INFO_MSK		(0xff << FIFO_ERR_INFO_OFF)
     91#define INT_COAL_EN			0x19c
     92#define OQ_INT_COAL_TIME		0x1a0
     93#define OQ_INT_COAL_CNT			0x1a4
     94#define ENT_INT_COAL_TIME		0x1a8
     95#define ENT_INT_COAL_CNT		0x1ac
     96#define OQ_INT_SRC			0x1b0
     97#define OQ_INT_SRC_MSK			0x1b4
     98#define ENT_INT_SRC1			0x1b8
     99#define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
    100#define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
    101#define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
    102#define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
    103#define ENT_INT_SRC2			0x1bc
    104#define ENT_INT_SRC3			0x1c0
    105#define ENT_INT_SRC3_WP_DEPTH_OFF		8
    106#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF	9
    107#define ENT_INT_SRC3_RP_DEPTH_OFF		10
    108#define ENT_INT_SRC3_AXI_OFF			11
    109#define ENT_INT_SRC3_FIFO_OFF			12
    110#define ENT_INT_SRC3_LM_OFF				14
    111#define ENT_INT_SRC3_ITC_INT_OFF	15
    112#define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
    113#define ENT_INT_SRC3_ABT_OFF		16
    114#define ENT_INT_SRC_MSK1		0x1c4
    115#define ENT_INT_SRC_MSK2		0x1c8
    116#define ENT_INT_SRC_MSK3		0x1cc
    117#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
    118#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
    119#define SAS_ECC_INTR			0x1e8
    120#define SAS_ECC_INTR_DQE_ECC_1B_OFF		0
    121#define SAS_ECC_INTR_DQE_ECC_MB_OFF		1
    122#define SAS_ECC_INTR_IOST_ECC_1B_OFF	2
    123#define SAS_ECC_INTR_IOST_ECC_MB_OFF	3
    124#define SAS_ECC_INTR_ITCT_ECC_MB_OFF	4
    125#define SAS_ECC_INTR_ITCT_ECC_1B_OFF	5
    126#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF	6
    127#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF	7
    128#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF	8
    129#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF	9
    130#define SAS_ECC_INTR_CQE_ECC_1B_OFF		10
    131#define SAS_ECC_INTR_CQE_ECC_MB_OFF		11
    132#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF	12
    133#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF	13
    134#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF	14
    135#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF	15
    136#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF	16
    137#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF	17
    138#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF	18
    139#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF	19
    140#define SAS_ECC_INTR_MSK		0x1ec
    141#define HGC_ERR_STAT_EN			0x238
    142#define CQE_SEND_CNT			0x248
    143#define DLVRY_Q_0_BASE_ADDR_LO		0x260
    144#define DLVRY_Q_0_BASE_ADDR_HI		0x264
    145#define DLVRY_Q_0_DEPTH			0x268
    146#define DLVRY_Q_0_WR_PTR		0x26c
    147#define DLVRY_Q_0_RD_PTR		0x270
    148#define HYPER_STREAM_ID_EN_CFG		0xc80
    149#define OQ0_INT_SRC_MSK			0xc90
    150#define COMPL_Q_0_BASE_ADDR_LO		0x4e0
    151#define COMPL_Q_0_BASE_ADDR_HI		0x4e4
    152#define COMPL_Q_0_DEPTH			0x4e8
    153#define COMPL_Q_0_WR_PTR		0x4ec
    154#define COMPL_Q_0_RD_PTR		0x4f0
    155#define HGC_RXM_DFX_STATUS14	0xae8
    156#define HGC_RXM_DFX_STATUS14_MEM0_OFF		0
    157#define HGC_RXM_DFX_STATUS14_MEM0_MSK		(0x1ff << \
    158						 HGC_RXM_DFX_STATUS14_MEM0_OFF)
    159#define HGC_RXM_DFX_STATUS14_MEM1_OFF		9
    160#define HGC_RXM_DFX_STATUS14_MEM1_MSK		(0x1ff << \
    161						 HGC_RXM_DFX_STATUS14_MEM1_OFF)
    162#define HGC_RXM_DFX_STATUS14_MEM2_OFF		18
    163#define HGC_RXM_DFX_STATUS14_MEM2_MSK		(0x1ff << \
    164						 HGC_RXM_DFX_STATUS14_MEM2_OFF)
    165#define HGC_RXM_DFX_STATUS15	0xaec
    166#define HGC_RXM_DFX_STATUS15_MEM3_OFF		0
    167#define HGC_RXM_DFX_STATUS15_MEM3_MSK		(0x1ff << \
    168						 HGC_RXM_DFX_STATUS15_MEM3_OFF)
    169/* phy registers need init */
    170#define PORT_BASE			(0x2000)
    171
    172#define PHY_CFG				(PORT_BASE + 0x0)
    173#define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
    174#define PHY_CFG_ENA_OFF			0
    175#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
    176#define PHY_CFG_DC_OPT_OFF		2
    177#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
    178#define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
    179#define PROG_PHY_LINK_RATE_MAX_OFF	0
    180#define PROG_PHY_LINK_RATE_MAX_MSK	(0xff << PROG_PHY_LINK_RATE_MAX_OFF)
    181#define PHY_CTRL			(PORT_BASE + 0x14)
    182#define PHY_CTRL_RESET_OFF		0
    183#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
    184#define SAS_PHY_CTRL			(PORT_BASE + 0x20)
    185#define SL_CFG				(PORT_BASE + 0x84)
    186#define PHY_PCN				(PORT_BASE + 0x44)
    187#define SL_TOUT_CFG			(PORT_BASE + 0x8c)
    188#define SL_CONTROL			(PORT_BASE + 0x94)
    189#define SL_CONTROL_NOTIFY_EN_OFF	0
    190#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
    191#define SL_CONTROL_CTA_OFF		17
    192#define SL_CONTROL_CTA_MSK		(0x1 << SL_CONTROL_CTA_OFF)
    193#define RX_PRIMS_STATUS			(PORT_BASE + 0x98)
    194#define RX_BCAST_CHG_OFF		1
    195#define RX_BCAST_CHG_MSK		(0x1 << RX_BCAST_CHG_OFF)
    196#define TX_ID_DWORD0			(PORT_BASE + 0x9c)
    197#define TX_ID_DWORD1			(PORT_BASE + 0xa0)
    198#define TX_ID_DWORD2			(PORT_BASE + 0xa4)
    199#define TX_ID_DWORD3			(PORT_BASE + 0xa8)
    200#define TX_ID_DWORD4			(PORT_BASE + 0xaC)
    201#define TX_ID_DWORD5			(PORT_BASE + 0xb0)
    202#define TX_ID_DWORD6			(PORT_BASE + 0xb4)
    203#define TXID_AUTO			(PORT_BASE + 0xb8)
    204#define TXID_AUTO_CT3_OFF		1
    205#define TXID_AUTO_CT3_MSK		(0x1 << TXID_AUTO_CT3_OFF)
    206#define TXID_AUTO_CTB_OFF		11
    207#define TXID_AUTO_CTB_MSK		(0x1 << TXID_AUTO_CTB_OFF)
    208#define TX_HARDRST_OFF			2
    209#define TX_HARDRST_MSK			(0x1 << TX_HARDRST_OFF)
    210#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
    211#define RX_IDAF_DWORD1			(PORT_BASE + 0xc8)
    212#define RX_IDAF_DWORD2			(PORT_BASE + 0xcc)
    213#define RX_IDAF_DWORD3			(PORT_BASE + 0xd0)
    214#define RX_IDAF_DWORD4			(PORT_BASE + 0xd4)
    215#define RX_IDAF_DWORD5			(PORT_BASE + 0xd8)
    216#define RX_IDAF_DWORD6			(PORT_BASE + 0xdc)
    217#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
    218#define CON_CONTROL			(PORT_BASE + 0x118)
    219#define CON_CONTROL_CFG_OPEN_ACC_STP_OFF	0
    220#define CON_CONTROL_CFG_OPEN_ACC_STP_MSK	\
    221		(0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
    222#define DONE_RECEIVED_TIME		(PORT_BASE + 0x11c)
    223#define CHL_INT0			(PORT_BASE + 0x1b4)
    224#define CHL_INT0_HOTPLUG_TOUT_OFF	0
    225#define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
    226#define CHL_INT0_SL_RX_BCST_ACK_OFF	1
    227#define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
    228#define CHL_INT0_SL_PHY_ENABLE_OFF	2
    229#define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
    230#define CHL_INT0_NOT_RDY_OFF		4
    231#define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
    232#define CHL_INT0_PHY_RDY_OFF		5
    233#define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
    234#define CHL_INT1			(PORT_BASE + 0x1b8)
    235#define CHL_INT1_DMAC_TX_ECC_ERR_OFF	15
    236#define CHL_INT1_DMAC_TX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
    237#define CHL_INT1_DMAC_RX_ECC_ERR_OFF	17
    238#define CHL_INT1_DMAC_RX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
    239#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF	19
    240#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF	20
    241#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF	21
    242#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF	22
    243#define CHL_INT2			(PORT_BASE + 0x1bc)
    244#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF	0
    245#define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
    246#define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
    247#define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
    248#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
    249#define DMA_TX_DFX0				(PORT_BASE + 0x200)
    250#define DMA_TX_DFX1				(PORT_BASE + 0x204)
    251#define DMA_TX_DFX1_IPTT_OFF		0
    252#define DMA_TX_DFX1_IPTT_MSK		(0xffff << DMA_TX_DFX1_IPTT_OFF)
    253#define DMA_TX_FIFO_DFX0		(PORT_BASE + 0x240)
    254#define PORT_DFX0				(PORT_BASE + 0x258)
    255#define LINK_DFX2					(PORT_BASE + 0X264)
    256#define LINK_DFX2_RCVR_HOLD_STS_OFF	9
    257#define LINK_DFX2_RCVR_HOLD_STS_MSK	(0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
    258#define LINK_DFX2_SEND_HOLD_STS_OFF	10
    259#define LINK_DFX2_SEND_HOLD_STS_MSK	(0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
    260#define SAS_ERR_CNT4_REG		(PORT_BASE + 0x290)
    261#define SAS_ERR_CNT6_REG		(PORT_BASE + 0x298)
    262#define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
    263#define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
    264#define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
    265#define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
    266#define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
    267#define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
    268#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
    269#define DMA_TX_STATUS_BUSY_OFF		0
    270#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
    271#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
    272#define DMA_RX_STATUS_BUSY_OFF		0
    273#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
    274
    275#define AXI_CFG				(0x5100)
    276#define AM_CFG_MAX_TRANS		(0x5010)
    277#define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)
    278
    279#define AXI_MASTER_CFG_BASE		(0x5000)
    280#define AM_CTRL_GLOBAL			(0x0)
    281#define AM_CURR_TRANS_RETURN	(0x150)
    282
    283/* HW dma structures */
    284/* Delivery queue header */
    285/* dw0 */
    286#define CMD_HDR_ABORT_FLAG_OFF		0
    287#define CMD_HDR_ABORT_FLAG_MSK		(0x3 << CMD_HDR_ABORT_FLAG_OFF)
    288#define CMD_HDR_ABORT_DEVICE_TYPE_OFF	2
    289#define CMD_HDR_ABORT_DEVICE_TYPE_MSK	(0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
    290#define CMD_HDR_RESP_REPORT_OFF		5
    291#define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
    292#define CMD_HDR_TLR_CTRL_OFF		6
    293#define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
    294#define CMD_HDR_PHY_ID_OFF		8
    295#define CMD_HDR_PHY_ID_MSK		(0x1ff << CMD_HDR_PHY_ID_OFF)
    296#define CMD_HDR_FORCE_PHY_OFF		17
    297#define CMD_HDR_FORCE_PHY_MSK		(0x1 << CMD_HDR_FORCE_PHY_OFF)
    298#define CMD_HDR_PORT_OFF		18
    299#define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
    300#define CMD_HDR_PRIORITY_OFF		27
    301#define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
    302#define CMD_HDR_CMD_OFF			29
    303#define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
    304/* dw1 */
    305#define CMD_HDR_DIR_OFF			5
    306#define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
    307#define CMD_HDR_RESET_OFF		7
    308#define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
    309#define CMD_HDR_VDTL_OFF		10
    310#define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
    311#define CMD_HDR_FRAME_TYPE_OFF		11
    312#define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
    313#define CMD_HDR_DEV_ID_OFF		16
    314#define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
    315/* dw2 */
    316#define CMD_HDR_CFL_OFF			0
    317#define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
    318#define CMD_HDR_NCQ_TAG_OFF		10
    319#define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
    320#define CMD_HDR_MRFL_OFF		15
    321#define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
    322#define CMD_HDR_SG_MOD_OFF		24
    323#define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
    324#define CMD_HDR_FIRST_BURST_OFF		26
    325#define CMD_HDR_FIRST_BURST_MSK		(0x1 << CMD_HDR_SG_MOD_OFF)
    326/* dw3 */
    327#define CMD_HDR_IPTT_OFF		0
    328#define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
    329/* dw6 */
    330#define CMD_HDR_DIF_SGL_LEN_OFF		0
    331#define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
    332#define CMD_HDR_DATA_SGL_LEN_OFF	16
    333#define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
    334#define CMD_HDR_ABORT_IPTT_OFF		16
    335#define CMD_HDR_ABORT_IPTT_MSK		(0xffff << CMD_HDR_ABORT_IPTT_OFF)
    336
    337/* Completion header */
    338/* dw0 */
    339#define CMPLT_HDR_ERR_PHASE_OFF	2
    340#define CMPLT_HDR_ERR_PHASE_MSK	(0xff << CMPLT_HDR_ERR_PHASE_OFF)
    341#define CMPLT_HDR_RSPNS_XFRD_OFF	10
    342#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
    343#define CMPLT_HDR_ERX_OFF		12
    344#define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
    345#define CMPLT_HDR_ABORT_STAT_OFF	13
    346#define CMPLT_HDR_ABORT_STAT_MSK	(0x7 << CMPLT_HDR_ABORT_STAT_OFF)
    347/* abort_stat */
    348#define STAT_IO_NOT_VALID		0x1
    349#define STAT_IO_NO_DEVICE		0x2
    350#define STAT_IO_COMPLETE		0x3
    351#define STAT_IO_ABORTED			0x4
    352/* dw1 */
    353#define CMPLT_HDR_IPTT_OFF		0
    354#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
    355#define CMPLT_HDR_DEV_ID_OFF		16
    356#define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)
    357
    358/* ITCT header */
    359/* qw0 */
    360#define ITCT_HDR_DEV_TYPE_OFF		0
    361#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
    362#define ITCT_HDR_VALID_OFF		2
    363#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
    364#define ITCT_HDR_MCR_OFF		5
    365#define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
    366#define ITCT_HDR_VLN_OFF		9
    367#define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
    368#define ITCT_HDR_SMP_TIMEOUT_OFF	16
    369#define ITCT_HDR_SMP_TIMEOUT_8US	1
    370#define ITCT_HDR_SMP_TIMEOUT		(ITCT_HDR_SMP_TIMEOUT_8US * \
    371					 250) /* 2ms */
    372#define ITCT_HDR_AWT_CONTINUE_OFF	25
    373#define ITCT_HDR_PORT_ID_OFF		28
    374#define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
    375/* qw2 */
    376#define ITCT_HDR_INLT_OFF		0
    377#define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
    378#define ITCT_HDR_BITLT_OFF		16
    379#define ITCT_HDR_BITLT_MSK		(0xffffULL << ITCT_HDR_BITLT_OFF)
    380#define ITCT_HDR_MCTLT_OFF		32
    381#define ITCT_HDR_MCTLT_MSK		(0xffffULL << ITCT_HDR_MCTLT_OFF)
    382#define ITCT_HDR_RTOLT_OFF		48
    383#define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)
    384
    385#define HISI_SAS_FATAL_INT_NR	2
    386
    387struct hisi_sas_complete_v2_hdr {
    388	__le32 dw0;
    389	__le32 dw1;
    390	__le32 act;
    391	__le32 dw3;
    392};
    393
    394struct hisi_sas_err_record_v2 {
    395	/* dw0 */
    396	__le32 trans_tx_fail_type;
    397
    398	/* dw1 */
    399	__le32 trans_rx_fail_type;
    400
    401	/* dw2 */
    402	__le16 dma_tx_err_type;
    403	__le16 sipc_rx_err_type;
    404
    405	/* dw3 */
    406	__le32 dma_rx_err_type;
    407};
    408
    409struct signal_attenuation_s {
    410	u32 de_emphasis;
    411	u32 preshoot;
    412	u32 boost;
    413};
    414
    415struct sig_atten_lu_s {
    416	const struct signal_attenuation_s *att;
    417	u32 sas_phy_ctrl;
    418};
    419
    420static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
    421	{
    422		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
    423		.msk = HGC_DQE_ECC_1B_ADDR_MSK,
    424		.shift = HGC_DQE_ECC_1B_ADDR_OFF,
    425		.msg = "hgc_dqe_ecc1b_intr",
    426		.reg = HGC_DQE_ECC_ADDR,
    427	},
    428	{
    429		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
    430		.msk = HGC_IOST_ECC_1B_ADDR_MSK,
    431		.shift = HGC_IOST_ECC_1B_ADDR_OFF,
    432		.msg = "hgc_iost_ecc1b_intr",
    433		.reg = HGC_IOST_ECC_ADDR,
    434	},
    435	{
    436		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
    437		.msk = HGC_ITCT_ECC_1B_ADDR_MSK,
    438		.shift = HGC_ITCT_ECC_1B_ADDR_OFF,
    439		.msg = "hgc_itct_ecc1b_intr",
    440		.reg = HGC_ITCT_ECC_ADDR,
    441	},
    442	{
    443		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
    444		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
    445		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
    446		.msg = "hgc_iostl_ecc1b_intr",
    447		.reg = HGC_LM_DFX_STATUS2,
    448	},
    449	{
    450		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
    451		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
    452		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
    453		.msg = "hgc_itctl_ecc1b_intr",
    454		.reg = HGC_LM_DFX_STATUS2,
    455	},
    456	{
    457		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
    458		.msk = HGC_CQE_ECC_1B_ADDR_MSK,
    459		.shift = HGC_CQE_ECC_1B_ADDR_OFF,
    460		.msg = "hgc_cqe_ecc1b_intr",
    461		.reg = HGC_CQE_ECC_ADDR,
    462	},
    463	{
    464		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
    465		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
    466		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
    467		.msg = "rxm_mem0_ecc1b_intr",
    468		.reg = HGC_RXM_DFX_STATUS14,
    469	},
    470	{
    471		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
    472		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
    473		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
    474		.msg = "rxm_mem1_ecc1b_intr",
    475		.reg = HGC_RXM_DFX_STATUS14,
    476	},
    477	{
    478		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
    479		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
    480		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
    481		.msg = "rxm_mem2_ecc1b_intr",
    482		.reg = HGC_RXM_DFX_STATUS14,
    483	},
    484	{
    485		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
    486		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
    487		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
    488		.msg = "rxm_mem3_ecc1b_intr",
    489		.reg = HGC_RXM_DFX_STATUS15,
    490	},
    491};
    492
    493static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
    494	{
    495		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
    496		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
    497		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
    498		.msg = "hgc_dqe_eccbad_intr",
    499		.reg = HGC_DQE_ECC_ADDR,
    500	},
    501	{
    502		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
    503		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
    504		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
    505		.msg = "hgc_iost_eccbad_intr",
    506		.reg = HGC_IOST_ECC_ADDR,
    507	},
    508	{
    509		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
    510		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
    511		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
    512		.msg = "hgc_itct_eccbad_intr",
    513		.reg = HGC_ITCT_ECC_ADDR,
    514	},
    515	{
    516		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
    517		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
    518		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
    519		.msg = "hgc_iostl_eccbad_intr",
    520		.reg = HGC_LM_DFX_STATUS2,
    521	},
    522	{
    523		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
    524		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
    525		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
    526		.msg = "hgc_itctl_eccbad_intr",
    527		.reg = HGC_LM_DFX_STATUS2,
    528	},
    529	{
    530		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
    531		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
    532		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
    533		.msg = "hgc_cqe_eccbad_intr",
    534		.reg = HGC_CQE_ECC_ADDR,
    535	},
    536	{
    537		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
    538		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
    539		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
    540		.msg = "rxm_mem0_eccbad_intr",
    541		.reg = HGC_RXM_DFX_STATUS14,
    542	},
    543	{
    544		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
    545		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
    546		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
    547		.msg = "rxm_mem1_eccbad_intr",
    548		.reg = HGC_RXM_DFX_STATUS14,
    549	},
    550	{
    551		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
    552		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
    553		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
    554		.msg = "rxm_mem2_eccbad_intr",
    555		.reg = HGC_RXM_DFX_STATUS14,
    556	},
    557	{
    558		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
    559		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
    560		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
    561		.msg = "rxm_mem3_eccbad_intr",
    562		.reg = HGC_RXM_DFX_STATUS15,
    563	},
    564};
    565
    566enum {
    567	HISI_SAS_PHY_PHY_UPDOWN,
    568	HISI_SAS_PHY_CHNL_INT,
    569	HISI_SAS_PHY_INT_NR
    570};
    571
    572enum {
    573	TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
    574	TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
    575	DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
    576	SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
    577	DMA_RX_ERR_BASE = 0x60, /* dw3 */
    578
    579	/* trans tx*/
    580	TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
    581	TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
    582	TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
    583	TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
    584	TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
    585	RESERVED0, /* 0x5 */
    586	TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
    587	TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
    588	TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
    589	TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
    590	TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
    591	TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
    592	TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
    593	TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
    594	TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
    595	TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
    596	TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
    597	TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
    598	TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
    599	TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
    600	TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
    601	TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
    602	TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
    603	TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
    604	TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
    605	TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
    606	TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
    607	TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
    608	/*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
    609	TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
    610	/*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
    611	TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
    612	TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
    613	/*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
    614	TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
    615
    616	/* trans rx */
    617	TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
    618	TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
    619	TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
    620	/*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
    621	TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
    622	TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
    623	TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
    624	/*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
    625	TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
    626	TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
    627	TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
    628	TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
    629	TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
    630	RESERVED1, /* 0x2b */
    631	TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
    632	TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
    633	TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
    634	TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
    635	TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
    636	TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
    637	/*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
    638	TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
    639	/*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
    640	TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
    641	/*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
    642	RESERVED2, /* 0x34 */
    643	RESERVED3, /* 0x35 */
    644	RESERVED4, /* 0x36 */
    645	RESERVED5, /* 0x37 */
    646	TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
    647	TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
    648	TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
    649	RESERVED6, /* 0x3b */
    650	RESERVED7, /* 0x3c */
    651	RESERVED8, /* 0x3d */
    652	RESERVED9, /* 0x3e */
    653	TRANS_RX_R_ERR, /* 0x3f */
    654
    655	/* dma tx */
    656	DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
    657	DMA_TX_DIF_APP_ERR, /* 0x41 */
    658	DMA_TX_DIF_RPP_ERR, /* 0x42 */
    659	DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
    660	DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
    661	DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
    662	DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
    663	DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
    664	DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
    665	DMA_TX_RAM_ECC_ERR, /* 0x49 */
    666	DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
    667	DMA_TX_MAX_ERR_CODE,
    668
    669	/* sipc rx */
    670	SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
    671	SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
    672	SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
    673	SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
    674	SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
    675	SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
    676	SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
    677	SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
    678	SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
    679	SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
    680	SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
    681	SIPC_RX_MAX_ERR_CODE,
    682
    683	/* dma rx */
    684	DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
    685	DMA_RX_DIF_APP_ERR, /* 0x61 */
    686	DMA_RX_DIF_RPP_ERR, /* 0x62 */
    687	DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
    688	DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
    689	DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
    690	DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
    691	DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
    692	RESERVED10, /* 0x68 */
    693	DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
    694	DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
    695	DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
    696	DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
    697	DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
    698	DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
    699	DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
    700	DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
    701	DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
    702	DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
    703	DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
    704	DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
    705	DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
    706	DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
    707	DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
    708	DMA_RX_RAM_ECC_ERR, /* 0x78 */
    709	DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
    710	DMA_RX_MAX_ERR_CODE,
    711};
    712
    713#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
    714#define HISI_MAX_SATA_SUPPORT_V2_HW	(HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
    715
    716#define DIR_NO_DATA 0
    717#define DIR_TO_INI 1
    718#define DIR_TO_DEVICE 2
    719#define DIR_RESERVED 3
    720
    721#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
    722		err_phase == 0x4 || err_phase == 0x8 ||\
    723		err_phase == 0x6 || err_phase == 0xa)
    724#define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
    725		err_phase == 0x20 || err_phase == 0x40)
    726
    727static void link_timeout_disable_link(struct timer_list *t);
    728
    729static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
    730{
    731	void __iomem *regs = hisi_hba->regs + off;
    732
    733	return readl(regs);
    734}
    735
    736static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
    737{
    738	void __iomem *regs = hisi_hba->regs + off;
    739
    740	return readl_relaxed(regs);
    741}
    742
    743static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
    744{
    745	void __iomem *regs = hisi_hba->regs + off;
    746
    747	writel(val, regs);
    748}
    749
    750static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
    751				 u32 off, u32 val)
    752{
    753	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
    754
    755	writel(val, regs);
    756}
    757
    758static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
    759				      int phy_no, u32 off)
    760{
    761	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
    762
    763	return readl(regs);
    764}
    765
    766/* This function needs to be protected from pre-emption. */
    767static int
    768slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
    769			     struct domain_device *device)
    770{
    771	int sata_dev = dev_is_sata(device);
    772	void *bitmap = hisi_hba->slot_index_tags;
    773	struct hisi_sas_device *sas_dev = device->lldd_dev;
    774	int sata_idx = sas_dev->sata_idx;
    775	int start, end;
    776
    777	if (!sata_dev) {
    778		/*
    779		 * STP link SoC bug workaround: index starts from 1.
    780		 * additionally, we can only allocate odd IPTT(1~4095)
    781		 * for SAS/SMP device.
    782		 */
    783		start = 1;
    784		end = hisi_hba->slot_index_count;
    785	} else {
    786		if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
    787			return -EINVAL;
    788
    789		/*
    790		 * For SATA device: allocate even IPTT in this interval
    791		 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
    792		 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
    793		 * SoC bug workaround. So we ignore the first 32 even IPTTs.
    794		 */
    795		start = 64 * (sata_idx + 1);
    796		end = 64 * (sata_idx + 2);
    797	}
    798
    799	spin_lock(&hisi_hba->lock);
    800	while (1) {
    801		start = find_next_zero_bit(bitmap,
    802					hisi_hba->slot_index_count, start);
    803		if (start >= end) {
    804			spin_unlock(&hisi_hba->lock);
    805			return -SAS_QUEUE_FULL;
    806		}
    807		/*
    808		  * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
    809		  */
    810		if (sata_dev ^ (start & 1))
    811			break;
    812		start++;
    813	}
    814
    815	set_bit(start, bitmap);
    816	spin_unlock(&hisi_hba->lock);
    817	return start;
    818}
    819
    820static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
    821{
    822	unsigned int index;
    823	struct device *dev = hisi_hba->dev;
    824	void *bitmap = hisi_hba->sata_dev_bitmap;
    825
    826	index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
    827	if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
    828		dev_warn(dev, "alloc sata index failed, index=%d\n", index);
    829		return false;
    830	}
    831
    832	set_bit(index, bitmap);
    833	*idx = index;
    834	return true;
    835}
    836
    837
    838static struct
    839hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
    840{
    841	struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
    842	struct hisi_sas_device *sas_dev = NULL;
    843	int i, sata_dev = dev_is_sata(device);
    844	int sata_idx = -1;
    845
    846	spin_lock(&hisi_hba->lock);
    847
    848	if (sata_dev)
    849		if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
    850			goto out;
    851
    852	for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
    853		/*
    854		 * SATA device id bit0 should be 0
    855		 */
    856		if (sata_dev && (i & 1))
    857			continue;
    858		if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
    859			int queue = i % hisi_hba->queue_count;
    860			struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
    861
    862			hisi_hba->devices[i].device_id = i;
    863			sas_dev = &hisi_hba->devices[i];
    864			sas_dev->dev_status = HISI_SAS_DEV_INIT;
    865			sas_dev->dev_type = device->dev_type;
    866			sas_dev->hisi_hba = hisi_hba;
    867			sas_dev->sas_device = device;
    868			sas_dev->sata_idx = sata_idx;
    869			sas_dev->dq = dq;
    870			spin_lock_init(&sas_dev->lock);
    871			INIT_LIST_HEAD(&hisi_hba->devices[i].list);
    872			break;
    873		}
    874	}
    875
    876out:
    877	spin_unlock(&hisi_hba->lock);
    878
    879	return sas_dev;
    880}
    881
    882static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
    883{
    884	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
    885
    886	cfg &= ~PHY_CFG_DC_OPT_MSK;
    887	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
    888	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
    889}
    890
    891static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
    892{
    893	struct sas_identify_frame identify_frame;
    894	u32 *identify_buffer;
    895
    896	memset(&identify_frame, 0, sizeof(identify_frame));
    897	identify_frame.dev_type = SAS_END_DEVICE;
    898	identify_frame.frame_type = 0;
    899	identify_frame._un1 = 1;
    900	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
    901	identify_frame.target_bits = SAS_PROTOCOL_NONE;
    902	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
    903	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
    904	identify_frame.phy_id = phy_no;
    905	identify_buffer = (u32 *)(&identify_frame);
    906
    907	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
    908			__swab32(identify_buffer[0]));
    909	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
    910			__swab32(identify_buffer[1]));
    911	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
    912			__swab32(identify_buffer[2]));
    913	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
    914			__swab32(identify_buffer[3]));
    915	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
    916			__swab32(identify_buffer[4]));
    917	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
    918			__swab32(identify_buffer[5]));
    919}
    920
    921static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
    922			     struct hisi_sas_device *sas_dev)
    923{
    924	struct domain_device *device = sas_dev->sas_device;
    925	struct device *dev = hisi_hba->dev;
    926	u64 qw0, device_id = sas_dev->device_id;
    927	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
    928	struct domain_device *parent_dev = device->parent;
    929	struct asd_sas_port *sas_port = device->port;
    930	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
    931	u64 sas_addr;
    932
    933	memset(itct, 0, sizeof(*itct));
    934
    935	/* qw0 */
    936	qw0 = 0;
    937	switch (sas_dev->dev_type) {
    938	case SAS_END_DEVICE:
    939	case SAS_EDGE_EXPANDER_DEVICE:
    940	case SAS_FANOUT_EXPANDER_DEVICE:
    941		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
    942		break;
    943	case SAS_SATA_DEV:
    944	case SAS_SATA_PENDING:
    945		if (parent_dev && dev_is_expander(parent_dev->dev_type))
    946			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
    947		else
    948			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
    949		break;
    950	default:
    951		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
    952			 sas_dev->dev_type);
    953	}
    954
    955	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
    956		(device->linkrate << ITCT_HDR_MCR_OFF) |
    957		(1 << ITCT_HDR_VLN_OFF) |
    958		(ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
    959		(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
    960		(port->id << ITCT_HDR_PORT_ID_OFF));
    961	itct->qw0 = cpu_to_le64(qw0);
    962
    963	/* qw1 */
    964	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
    965	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
    966
    967	/* qw2 */
    968	if (!dev_is_sata(device))
    969		itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
    970					(0x1ULL << ITCT_HDR_BITLT_OFF) |
    971					(0x32ULL << ITCT_HDR_MCTLT_OFF) |
    972					(0x1ULL << ITCT_HDR_RTOLT_OFF));
    973}
    974
    975static int clear_itct_v2_hw(struct hisi_hba *hisi_hba,
    976			    struct hisi_sas_device *sas_dev)
    977{
    978	DECLARE_COMPLETION_ONSTACK(completion);
    979	u64 dev_id = sas_dev->device_id;
    980	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
    981	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
    982	struct device *dev = hisi_hba->dev;
    983	int i;
    984
    985	sas_dev->completion = &completion;
    986
    987	/* clear the itct interrupt state */
    988	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
    989		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
    990				 ENT_INT_SRC3_ITC_INT_MSK);
    991
    992	/* need to set register twice to clear ITCT for v2 hw */
    993	for (i = 0; i < 2; i++) {
    994		reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
    995		hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
    996		if (!wait_for_completion_timeout(sas_dev->completion,
    997						 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
    998			dev_warn(dev, "failed to clear ITCT\n");
    999			return -ETIMEDOUT;
   1000		}
   1001
   1002		memset(itct, 0, sizeof(struct hisi_sas_itct));
   1003	}
   1004	return 0;
   1005}
   1006
   1007static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
   1008{
   1009	struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
   1010
   1011	/* SoC bug workaround */
   1012	if (dev_is_sata(sas_dev->sas_device))
   1013		clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
   1014}
   1015
   1016static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
   1017{
   1018	int i, reset_val;
   1019	u32 val;
   1020	unsigned long end_time;
   1021	struct device *dev = hisi_hba->dev;
   1022
   1023	/* The mask needs to be set depending on the number of phys */
   1024	if (hisi_hba->n_phy == 9)
   1025		reset_val = 0x1fffff;
   1026	else
   1027		reset_val = 0x7ffff;
   1028
   1029	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
   1030
   1031	/* Disable all of the PHYs */
   1032	for (i = 0; i < hisi_hba->n_phy; i++) {
   1033		u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
   1034
   1035		phy_cfg &= ~PHY_CTRL_RESET_MSK;
   1036		hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
   1037	}
   1038	udelay(50);
   1039
   1040	/* Ensure DMA tx & rx idle */
   1041	for (i = 0; i < hisi_hba->n_phy; i++) {
   1042		u32 dma_tx_status, dma_rx_status;
   1043
   1044		end_time = jiffies + msecs_to_jiffies(1000);
   1045
   1046		while (1) {
   1047			dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
   1048							    DMA_TX_STATUS);
   1049			dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
   1050							    DMA_RX_STATUS);
   1051
   1052			if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
   1053				!(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
   1054				break;
   1055
   1056			msleep(20);
   1057			if (time_after(jiffies, end_time))
   1058				return -EIO;
   1059		}
   1060	}
   1061
   1062	/* Ensure axi bus idle */
   1063	end_time = jiffies + msecs_to_jiffies(1000);
   1064	while (1) {
   1065		u32 axi_status =
   1066			hisi_sas_read32(hisi_hba, AXI_CFG);
   1067
   1068		if (axi_status == 0)
   1069			break;
   1070
   1071		msleep(20);
   1072		if (time_after(jiffies, end_time))
   1073			return -EIO;
   1074	}
   1075
   1076	if (ACPI_HANDLE(dev)) {
   1077		acpi_status s;
   1078
   1079		s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
   1080		if (ACPI_FAILURE(s)) {
   1081			dev_err(dev, "Reset failed\n");
   1082			return -EIO;
   1083		}
   1084	} else if (hisi_hba->ctrl) {
   1085		/* reset and disable clock*/
   1086		regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
   1087				reset_val);
   1088		regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
   1089				reset_val);
   1090		msleep(1);
   1091		regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
   1092		if (reset_val != (val & reset_val)) {
   1093			dev_err(dev, "SAS reset fail.\n");
   1094			return -EIO;
   1095		}
   1096
   1097		/* De-reset and enable clock*/
   1098		regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
   1099				reset_val);
   1100		regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
   1101				reset_val);
   1102		msleep(1);
   1103		regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
   1104				&val);
   1105		if (val & reset_val) {
   1106			dev_err(dev, "SAS de-reset fail.\n");
   1107			return -EIO;
   1108		}
   1109	} else {
   1110		dev_err(dev, "no reset method\n");
   1111		return -EINVAL;
   1112	}
   1113
   1114	return 0;
   1115}
   1116
   1117/* This function needs to be called after resetting SAS controller. */
   1118static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
   1119{
   1120	u32 cfg;
   1121	int phy_no;
   1122
   1123	hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
   1124	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
   1125		cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
   1126		if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
   1127			continue;
   1128
   1129		cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
   1130		hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
   1131	}
   1132}
   1133
   1134static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
   1135{
   1136	int phy_no;
   1137	u32 dma_tx_dfx1;
   1138
   1139	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
   1140		if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
   1141			continue;
   1142
   1143		dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
   1144						DMA_TX_DFX1);
   1145		if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
   1146			u32 cfg = hisi_sas_phy_read32(hisi_hba,
   1147				phy_no, CON_CONTROL);
   1148
   1149			cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
   1150			hisi_sas_phy_write32(hisi_hba, phy_no,
   1151				CON_CONTROL, cfg);
   1152			clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
   1153		}
   1154	}
   1155}
   1156
   1157static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
   1158static const struct sig_atten_lu_s sig_atten_lu[] = {
   1159	{ &x6000, 0x3016a68 },
   1160};
   1161
   1162static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
   1163{
   1164	struct device *dev = hisi_hba->dev;
   1165	u32 sas_phy_ctrl = 0x30b9908;
   1166	u32 signal[3];
   1167	int i;
   1168
   1169	/* Global registers init */
   1170
   1171	/* Deal with am-max-transmissions quirk */
   1172	if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
   1173		hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
   1174		hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
   1175				 0x2020);
   1176	} /* Else, use defaults -> do nothing */
   1177
   1178	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
   1179			 (u32)((1ULL << hisi_hba->queue_count) - 1));
   1180	hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
   1181	hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
   1182	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
   1183	hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
   1184	hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
   1185	hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
   1186	hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
   1187	hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
   1188	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
   1189	hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
   1190	hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
   1191	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
   1192	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
   1193	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
   1194	hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
   1195	hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
   1196	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
   1197	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
   1198	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
   1199	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
   1200	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
   1201	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
   1202	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
   1203	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
   1204	for (i = 0; i < hisi_hba->queue_count; i++)
   1205		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
   1206
   1207	hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
   1208	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
   1209
   1210	/* Get sas_phy_ctrl value to deal with TX FFE issue. */
   1211	if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
   1212					    signal, ARRAY_SIZE(signal))) {
   1213		for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
   1214			const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
   1215			const struct signal_attenuation_s *att = lookup->att;
   1216
   1217			if ((signal[0] == att->de_emphasis) &&
   1218			    (signal[1] == att->preshoot) &&
   1219			    (signal[2] == att->boost)) {
   1220				sas_phy_ctrl = lookup->sas_phy_ctrl;
   1221				break;
   1222			}
   1223		}
   1224
   1225		if (i == ARRAY_SIZE(sig_atten_lu))
   1226			dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
   1227	}
   1228
   1229	for (i = 0; i < hisi_hba->n_phy; i++) {
   1230		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
   1231		struct asd_sas_phy *sas_phy = &phy->sas_phy;
   1232		u32 prog_phy_link_rate = 0x800;
   1233
   1234		if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
   1235				SAS_LINK_RATE_1_5_GBPS)) {
   1236			prog_phy_link_rate = 0x855;
   1237		} else {
   1238			enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
   1239
   1240			prog_phy_link_rate =
   1241				hisi_sas_get_prog_phy_linkrate_mask(max) |
   1242				0x800;
   1243		}
   1244		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
   1245			prog_phy_link_rate);
   1246		hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
   1247		hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
   1248		hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
   1249		hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
   1250		hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
   1251		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
   1252		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
   1253		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
   1254		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
   1255		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
   1256		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
   1257		hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
   1258		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
   1259		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
   1260		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
   1261		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
   1262		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
   1263		hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
   1264		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
   1265		if (hisi_hba->refclk_frequency_mhz == 66)
   1266			hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
   1267		/* else, do nothing -> leave it how you found it */
   1268	}
   1269
   1270	for (i = 0; i < hisi_hba->queue_count; i++) {
   1271		/* Delivery queue */
   1272		hisi_sas_write32(hisi_hba,
   1273				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
   1274				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
   1275
   1276		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
   1277				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
   1278
   1279		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
   1280				 HISI_SAS_QUEUE_SLOTS);
   1281
   1282		/* Completion queue */
   1283		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
   1284				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
   1285
   1286		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
   1287				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
   1288
   1289		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
   1290				 HISI_SAS_QUEUE_SLOTS);
   1291	}
   1292
   1293	/* itct */
   1294	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
   1295			 lower_32_bits(hisi_hba->itct_dma));
   1296
   1297	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
   1298			 upper_32_bits(hisi_hba->itct_dma));
   1299
   1300	/* iost */
   1301	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
   1302			 lower_32_bits(hisi_hba->iost_dma));
   1303
   1304	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
   1305			 upper_32_bits(hisi_hba->iost_dma));
   1306
   1307	/* breakpoint */
   1308	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
   1309			 lower_32_bits(hisi_hba->breakpoint_dma));
   1310
   1311	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
   1312			 upper_32_bits(hisi_hba->breakpoint_dma));
   1313
   1314	/* SATA broken msg */
   1315	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
   1316			 lower_32_bits(hisi_hba->sata_breakpoint_dma));
   1317
   1318	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
   1319			 upper_32_bits(hisi_hba->sata_breakpoint_dma));
   1320
   1321	/* SATA initial fis */
   1322	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
   1323			 lower_32_bits(hisi_hba->initial_fis_dma));
   1324
   1325	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
   1326			 upper_32_bits(hisi_hba->initial_fis_dma));
   1327}
   1328
   1329static void link_timeout_enable_link(struct timer_list *t)
   1330{
   1331	struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
   1332	int i, reg_val;
   1333
   1334	for (i = 0; i < hisi_hba->n_phy; i++) {
   1335		if (hisi_hba->reject_stp_links_msk & BIT(i))
   1336			continue;
   1337
   1338		reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
   1339		if (!(reg_val & BIT(0))) {
   1340			hisi_sas_phy_write32(hisi_hba, i,
   1341					CON_CONTROL, 0x7);
   1342			break;
   1343		}
   1344	}
   1345
   1346	hisi_hba->timer.function = link_timeout_disable_link;
   1347	mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
   1348}
   1349
   1350static void link_timeout_disable_link(struct timer_list *t)
   1351{
   1352	struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
   1353	int i, reg_val;
   1354
   1355	reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
   1356	for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
   1357		if (hisi_hba->reject_stp_links_msk & BIT(i))
   1358			continue;
   1359
   1360		if (reg_val & BIT(i)) {
   1361			hisi_sas_phy_write32(hisi_hba, i,
   1362					CON_CONTROL, 0x6);
   1363			break;
   1364		}
   1365	}
   1366
   1367	hisi_hba->timer.function = link_timeout_enable_link;
   1368	mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
   1369}
   1370
   1371static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
   1372{
   1373	hisi_hba->timer.function = link_timeout_disable_link;
   1374	hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
   1375	add_timer(&hisi_hba->timer);
   1376}
   1377
   1378static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
   1379{
   1380	struct device *dev = hisi_hba->dev;
   1381	int rc;
   1382
   1383	rc = reset_hw_v2_hw(hisi_hba);
   1384	if (rc) {
   1385		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
   1386		return rc;
   1387	}
   1388
   1389	msleep(100);
   1390	init_reg_v2_hw(hisi_hba);
   1391
   1392	return 0;
   1393}
   1394
   1395static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1396{
   1397	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
   1398
   1399	cfg |= PHY_CFG_ENA_MSK;
   1400	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
   1401}
   1402
   1403static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1404{
   1405	u32 context;
   1406
   1407	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
   1408	if (context & (1 << phy_no))
   1409		return true;
   1410
   1411	return false;
   1412}
   1413
   1414static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1415{
   1416	u32 dfx_val;
   1417
   1418	dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
   1419
   1420	if (dfx_val & BIT(16))
   1421		return false;
   1422
   1423	return true;
   1424}
   1425
   1426static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1427{
   1428	int i, max_loop = 1000;
   1429	struct device *dev = hisi_hba->dev;
   1430	u32 status, axi_status, dfx_val, dfx_tx_val;
   1431
   1432	for (i = 0; i < max_loop; i++) {
   1433		status = hisi_sas_read32_relaxed(hisi_hba,
   1434			AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
   1435
   1436		axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
   1437		dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
   1438		dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
   1439			phy_no, DMA_TX_FIFO_DFX0);
   1440
   1441		if ((status == 0x3) && (axi_status == 0x0) &&
   1442		    (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
   1443			return true;
   1444		udelay(10);
   1445	}
   1446	dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
   1447			phy_no, status, axi_status,
   1448			dfx_val, dfx_tx_val);
   1449	return false;
   1450}
   1451
   1452static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1453{
   1454	int i, max_loop = 1000;
   1455	struct device *dev = hisi_hba->dev;
   1456	u32 status, tx_dfx0;
   1457
   1458	for (i = 0; i < max_loop; i++) {
   1459		status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
   1460		status = (status & 0x3fc0) >> 6;
   1461
   1462		if (status != 0x1)
   1463			return true;
   1464
   1465		tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
   1466		if ((tx_dfx0 & 0x1ff) == 0x2)
   1467			return true;
   1468		udelay(10);
   1469	}
   1470	dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
   1471			phy_no, status, tx_dfx0);
   1472	return false;
   1473}
   1474
   1475static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1476{
   1477	if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
   1478		return true;
   1479
   1480	if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
   1481		return false;
   1482
   1483	if (!wait_io_done_v2_hw(hisi_hba, phy_no))
   1484		return false;
   1485
   1486	return true;
   1487}
   1488
   1489
   1490static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1491{
   1492	u32 cfg, axi_val, dfx0_val, txid_auto;
   1493	struct device *dev = hisi_hba->dev;
   1494
   1495	/* Close axi bus. */
   1496	axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
   1497				AM_CTRL_GLOBAL);
   1498	axi_val |= 0x1;
   1499	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
   1500		AM_CTRL_GLOBAL, axi_val);
   1501
   1502	if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
   1503		if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
   1504			goto do_disable;
   1505
   1506		/* Reset host controller. */
   1507		queue_work(hisi_hba->wq, &hisi_hba->rst_work);
   1508		return;
   1509	}
   1510
   1511	dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
   1512	dfx0_val = (dfx0_val & 0x1fc0) >> 6;
   1513	if (dfx0_val != 0x4)
   1514		goto do_disable;
   1515
   1516	if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
   1517		dev_warn(dev, "phy%d, wait tx fifo need send break\n",
   1518			phy_no);
   1519		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
   1520					TXID_AUTO);
   1521		txid_auto |= TXID_AUTO_CTB_MSK;
   1522		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
   1523					txid_auto);
   1524	}
   1525
   1526do_disable:
   1527	cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
   1528	cfg &= ~PHY_CFG_ENA_MSK;
   1529	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
   1530
   1531	/* Open axi bus. */
   1532	axi_val &= ~0x1;
   1533	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
   1534		AM_CTRL_GLOBAL, axi_val);
   1535}
   1536
   1537static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1538{
   1539	config_id_frame_v2_hw(hisi_hba, phy_no);
   1540	config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
   1541	enable_phy_v2_hw(hisi_hba, phy_no);
   1542}
   1543
   1544static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1545{
   1546	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   1547	u32 txid_auto;
   1548
   1549	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
   1550	if (phy->identify.device_type == SAS_END_DEVICE) {
   1551		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
   1552		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
   1553					txid_auto | TX_HARDRST_MSK);
   1554	}
   1555	msleep(100);
   1556	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
   1557}
   1558
   1559static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1560{
   1561	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   1562	struct asd_sas_phy *sas_phy = &phy->sas_phy;
   1563	struct sas_phy *sphy = sas_phy->phy;
   1564	u32 err4_reg_val, err6_reg_val;
   1565
   1566	/* loss dword syn, phy reset problem */
   1567	err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
   1568
   1569	/* disparity err, invalid dword */
   1570	err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
   1571
   1572	sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
   1573	sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
   1574	sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
   1575	sphy->running_disparity_error_count += err6_reg_val & 0xFF;
   1576}
   1577
   1578static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
   1579{
   1580	int i;
   1581
   1582	for (i = 0; i < hisi_hba->n_phy; i++) {
   1583		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
   1584		struct asd_sas_phy *sas_phy = &phy->sas_phy;
   1585
   1586		if (!sas_phy->phy->enabled)
   1587			continue;
   1588
   1589		hisi_sas_phy_enable(hisi_hba, i, 1);
   1590	}
   1591}
   1592
   1593static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
   1594{
   1595	u32 sl_control;
   1596
   1597	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
   1598	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
   1599	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
   1600	msleep(1);
   1601	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
   1602	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
   1603	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
   1604}
   1605
   1606static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
   1607{
   1608	return SAS_LINK_RATE_12_0_GBPS;
   1609}
   1610
   1611static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
   1612		struct sas_phy_linkrates *r)
   1613{
   1614	enum sas_linkrate max = r->maximum_linkrate;
   1615	u32 prog_phy_link_rate = 0x800;
   1616
   1617	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
   1618	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
   1619			     prog_phy_link_rate);
   1620}
   1621
   1622static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
   1623{
   1624	int i, bitmap = 0;
   1625	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
   1626	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
   1627
   1628	for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
   1629		if (phy_state & 1 << i)
   1630			if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
   1631				bitmap |= 1 << i;
   1632
   1633	if (hisi_hba->n_phy == 9) {
   1634		u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
   1635
   1636		if (phy_state & 1 << 8)
   1637			if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
   1638			     PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
   1639				bitmap |= 1 << 9;
   1640	}
   1641
   1642	return bitmap;
   1643}
   1644
   1645/* DQ lock must be taken here */
   1646static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
   1647{
   1648	struct hisi_hba *hisi_hba = dq->hisi_hba;
   1649	struct hisi_sas_slot *s, *s1, *s2 = NULL;
   1650	int dlvry_queue = dq->id;
   1651	int wp;
   1652
   1653	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
   1654		if (!s->ready)
   1655			break;
   1656		s2 = s;
   1657		list_del(&s->delivery);
   1658	}
   1659
   1660	if (!s2)
   1661		return;
   1662
   1663	/*
   1664	 * Ensure that memories for slots built on other CPUs is observed.
   1665	 */
   1666	smp_rmb();
   1667	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
   1668
   1669	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
   1670}
   1671
   1672static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
   1673			      struct hisi_sas_slot *slot,
   1674			      struct hisi_sas_cmd_hdr *hdr,
   1675			      struct scatterlist *scatter,
   1676			      int n_elem)
   1677{
   1678	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
   1679	struct scatterlist *sg;
   1680	int i;
   1681
   1682	for_each_sg(scatter, sg, n_elem, i) {
   1683		struct hisi_sas_sge *entry = &sge_page->sge[i];
   1684
   1685		entry->addr = cpu_to_le64(sg_dma_address(sg));
   1686		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
   1687		entry->data_len = cpu_to_le32(sg_dma_len(sg));
   1688		entry->data_off = 0;
   1689	}
   1690
   1691	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
   1692
   1693	hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
   1694}
   1695
   1696static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
   1697			  struct hisi_sas_slot *slot)
   1698{
   1699	struct sas_task *task = slot->task;
   1700	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
   1701	struct domain_device *device = task->dev;
   1702	struct hisi_sas_port *port = slot->port;
   1703	struct scatterlist *sg_req;
   1704	struct hisi_sas_device *sas_dev = device->lldd_dev;
   1705	dma_addr_t req_dma_addr;
   1706	unsigned int req_len;
   1707
   1708	/* req */
   1709	sg_req = &task->smp_task.smp_req;
   1710	req_dma_addr = sg_dma_address(sg_req);
   1711	req_len = sg_dma_len(&task->smp_task.smp_req);
   1712
   1713	/* create header */
   1714	/* dw0 */
   1715	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
   1716			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
   1717			       (2 << CMD_HDR_CMD_OFF)); /* smp */
   1718
   1719	/* map itct entry */
   1720	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
   1721			       (1 << CMD_HDR_FRAME_TYPE_OFF) |
   1722			       (DIR_NO_DATA << CMD_HDR_DIR_OFF));
   1723
   1724	/* dw2 */
   1725	hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
   1726			       (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
   1727			       CMD_HDR_MRFL_OFF));
   1728
   1729	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
   1730
   1731	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
   1732	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
   1733}
   1734
   1735static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
   1736			  struct hisi_sas_slot *slot)
   1737{
   1738	struct sas_task *task = slot->task;
   1739	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
   1740	struct domain_device *device = task->dev;
   1741	struct hisi_sas_device *sas_dev = device->lldd_dev;
   1742	struct hisi_sas_port *port = slot->port;
   1743	struct sas_ssp_task *ssp_task = &task->ssp_task;
   1744	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
   1745	struct sas_tmf_task *tmf = slot->tmf;
   1746	int has_data = 0, priority = !!tmf;
   1747	u8 *buf_cmd;
   1748	u32 dw1 = 0, dw2 = 0;
   1749
   1750	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
   1751			       (2 << CMD_HDR_TLR_CTRL_OFF) |
   1752			       (port->id << CMD_HDR_PORT_OFF) |
   1753			       (priority << CMD_HDR_PRIORITY_OFF) |
   1754			       (1 << CMD_HDR_CMD_OFF)); /* ssp */
   1755
   1756	dw1 = 1 << CMD_HDR_VDTL_OFF;
   1757	if (tmf) {
   1758		dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
   1759		dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
   1760	} else {
   1761		dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
   1762		switch (scsi_cmnd->sc_data_direction) {
   1763		case DMA_TO_DEVICE:
   1764			has_data = 1;
   1765			dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
   1766			break;
   1767		case DMA_FROM_DEVICE:
   1768			has_data = 1;
   1769			dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
   1770			break;
   1771		default:
   1772			dw1 &= ~CMD_HDR_DIR_MSK;
   1773		}
   1774	}
   1775
   1776	/* map itct entry */
   1777	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
   1778	hdr->dw1 = cpu_to_le32(dw1);
   1779
   1780	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
   1781	      + 3) / 4) << CMD_HDR_CFL_OFF) |
   1782	      ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
   1783	      (2 << CMD_HDR_SG_MOD_OFF);
   1784	hdr->dw2 = cpu_to_le32(dw2);
   1785
   1786	hdr->transfer_tags = cpu_to_le32(slot->idx);
   1787
   1788	if (has_data)
   1789		prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
   1790					slot->n_elem);
   1791
   1792	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
   1793	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
   1794	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
   1795
   1796	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
   1797		sizeof(struct ssp_frame_hdr);
   1798
   1799	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
   1800	if (!tmf) {
   1801		buf_cmd[9] = task->ssp_task.task_attr |
   1802				(task->ssp_task.task_prio << 3);
   1803		memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
   1804				task->ssp_task.cmd->cmd_len);
   1805	} else {
   1806		buf_cmd[10] = tmf->tmf;
   1807		switch (tmf->tmf) {
   1808		case TMF_ABORT_TASK:
   1809		case TMF_QUERY_TASK:
   1810			buf_cmd[12] =
   1811				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
   1812			buf_cmd[13] =
   1813				tmf->tag_of_task_to_be_managed & 0xff;
   1814			break;
   1815		default:
   1816			break;
   1817		}
   1818	}
   1819}
   1820
   1821#define TRANS_TX_ERR	0
   1822#define TRANS_RX_ERR	1
   1823#define DMA_TX_ERR		2
   1824#define SIPC_RX_ERR		3
   1825#define DMA_RX_ERR		4
   1826
   1827#define DMA_TX_ERR_OFF	0
   1828#define DMA_TX_ERR_MSK	(0xffff << DMA_TX_ERR_OFF)
   1829#define SIPC_RX_ERR_OFF	16
   1830#define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
   1831
   1832static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
   1833{
   1834	static const u8 trans_tx_err_code_prio[] = {
   1835		TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
   1836		TRANS_TX_ERR_PHY_NOT_ENABLE,
   1837		TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
   1838		TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
   1839		TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
   1840		RESERVED0,
   1841		TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
   1842		TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
   1843		TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
   1844		TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
   1845		TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
   1846		TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
   1847		TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
   1848		TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
   1849		TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
   1850		TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
   1851		TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
   1852		TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
   1853		TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
   1854		TRANS_TX_ERR_WITH_CLOSE_COMINIT,
   1855		TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
   1856		TRANS_TX_ERR_WITH_BREAK_REQUEST,
   1857		TRANS_TX_ERR_WITH_BREAK_RECEVIED,
   1858		TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
   1859		TRANS_TX_ERR_WITH_CLOSE_NORMAL,
   1860		TRANS_TX_ERR_WITH_NAK_RECEVIED,
   1861		TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
   1862		TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
   1863		TRANS_TX_ERR_WITH_IPTT_CONFLICT,
   1864		TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
   1865		TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
   1866	};
   1867	int index, i;
   1868
   1869	for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
   1870		index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
   1871		if (err_msk & (1 << index))
   1872			return trans_tx_err_code_prio[i];
   1873	}
   1874	return -1;
   1875}
   1876
   1877static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
   1878{
   1879	static const u8 trans_rx_err_code_prio[] = {
   1880		TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
   1881		TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
   1882		TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
   1883		TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
   1884		TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
   1885		TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
   1886		TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
   1887		TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
   1888		TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
   1889		TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
   1890		TRANS_RX_ERR_WITH_CLOSE_COMINIT,
   1891		TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
   1892		TRANS_RX_ERR_WITH_BREAK_REQUEST,
   1893		TRANS_RX_ERR_WITH_BREAK_RECEVIED,
   1894		RESERVED1,
   1895		TRANS_RX_ERR_WITH_CLOSE_NORMAL,
   1896		TRANS_RX_ERR_WITH_DATA_LEN0,
   1897		TRANS_RX_ERR_WITH_BAD_HASH,
   1898		TRANS_RX_XRDY_WLEN_ZERO_ERR,
   1899		TRANS_RX_SSP_FRM_LEN_ERR,
   1900		RESERVED2,
   1901		RESERVED3,
   1902		RESERVED4,
   1903		RESERVED5,
   1904		TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
   1905		TRANS_RX_SMP_FRM_LEN_ERR,
   1906		TRANS_RX_SMP_RESP_TIMEOUT_ERR,
   1907		RESERVED6,
   1908		RESERVED7,
   1909		RESERVED8,
   1910		RESERVED9,
   1911		TRANS_RX_R_ERR,
   1912	};
   1913	int index, i;
   1914
   1915	for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
   1916		index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
   1917		if (err_msk & (1 << index))
   1918			return trans_rx_err_code_prio[i];
   1919	}
   1920	return -1;
   1921}
   1922
   1923static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
   1924{
   1925	static const u8 dma_tx_err_code_prio[] = {
   1926		DMA_TX_UNEXP_XFER_ERR,
   1927		DMA_TX_UNEXP_RETRANS_ERR,
   1928		DMA_TX_XFER_LEN_OVERFLOW,
   1929		DMA_TX_XFER_OFFSET_ERR,
   1930		DMA_TX_RAM_ECC_ERR,
   1931		DMA_TX_DIF_LEN_ALIGN_ERR,
   1932		DMA_TX_DIF_CRC_ERR,
   1933		DMA_TX_DIF_APP_ERR,
   1934		DMA_TX_DIF_RPP_ERR,
   1935		DMA_TX_DATA_SGL_OVERFLOW,
   1936		DMA_TX_DIF_SGL_OVERFLOW,
   1937	};
   1938	int index, i;
   1939
   1940	for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
   1941		index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
   1942		err_msk = err_msk & DMA_TX_ERR_MSK;
   1943		if (err_msk & (1 << index))
   1944			return dma_tx_err_code_prio[i];
   1945	}
   1946	return -1;
   1947}
   1948
   1949static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
   1950{
   1951	static const u8 sipc_rx_err_code_prio[] = {
   1952		SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
   1953		SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
   1954		SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
   1955		SIPC_RX_WRSETUP_LEN_ODD_ERR,
   1956		SIPC_RX_WRSETUP_LEN_ZERO_ERR,
   1957		SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
   1958		SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
   1959		SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
   1960		SIPC_RX_SATA_UNEXP_FIS_ERR,
   1961		SIPC_RX_WRSETUP_ESTATUS_ERR,
   1962		SIPC_RX_DATA_UNDERFLOW_ERR,
   1963	};
   1964	int index, i;
   1965
   1966	for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
   1967		index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
   1968		err_msk = err_msk & SIPC_RX_ERR_MSK;
   1969		if (err_msk & (1 << (index + 0x10)))
   1970			return sipc_rx_err_code_prio[i];
   1971	}
   1972	return -1;
   1973}
   1974
   1975static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
   1976{
   1977	static const u8 dma_rx_err_code_prio[] = {
   1978		DMA_RX_UNKNOWN_FRM_ERR,
   1979		DMA_RX_DATA_LEN_OVERFLOW,
   1980		DMA_RX_DATA_LEN_UNDERFLOW,
   1981		DMA_RX_DATA_OFFSET_ERR,
   1982		RESERVED10,
   1983		DMA_RX_SATA_FRAME_TYPE_ERR,
   1984		DMA_RX_RESP_BUF_OVERFLOW,
   1985		DMA_RX_UNEXP_RETRANS_RESP_ERR,
   1986		DMA_RX_UNEXP_NORM_RESP_ERR,
   1987		DMA_RX_UNEXP_RDFRAME_ERR,
   1988		DMA_RX_PIO_DATA_LEN_ERR,
   1989		DMA_RX_RDSETUP_STATUS_ERR,
   1990		DMA_RX_RDSETUP_STATUS_DRQ_ERR,
   1991		DMA_RX_RDSETUP_STATUS_BSY_ERR,
   1992		DMA_RX_RDSETUP_LEN_ODD_ERR,
   1993		DMA_RX_RDSETUP_LEN_ZERO_ERR,
   1994		DMA_RX_RDSETUP_LEN_OVER_ERR,
   1995		DMA_RX_RDSETUP_OFFSET_ERR,
   1996		DMA_RX_RDSETUP_ACTIVE_ERR,
   1997		DMA_RX_RDSETUP_ESTATUS_ERR,
   1998		DMA_RX_RAM_ECC_ERR,
   1999		DMA_RX_DIF_CRC_ERR,
   2000		DMA_RX_DIF_APP_ERR,
   2001		DMA_RX_DIF_RPP_ERR,
   2002		DMA_RX_DATA_SGL_OVERFLOW,
   2003		DMA_RX_DIF_SGL_OVERFLOW,
   2004	};
   2005	int index, i;
   2006
   2007	for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
   2008		index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
   2009		if (err_msk & (1 << index))
   2010			return dma_rx_err_code_prio[i];
   2011	}
   2012	return -1;
   2013}
   2014
   2015/* by default, task resp is complete */
   2016static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
   2017			   struct sas_task *task,
   2018			   struct hisi_sas_slot *slot,
   2019			   int err_phase)
   2020{
   2021	struct task_status_struct *ts = &task->task_status;
   2022	struct hisi_sas_err_record_v2 *err_record =
   2023			hisi_sas_status_buf_addr_mem(slot);
   2024	u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
   2025	u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
   2026	u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
   2027	u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
   2028	u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
   2029	int error = -1;
   2030
   2031	if (err_phase == 1) {
   2032		/* error in TX phase, the priority of error is: DW2 > DW0 */
   2033		error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
   2034		if (error == -1)
   2035			error = parse_trans_tx_err_code_v2_hw(
   2036					trans_tx_fail_type);
   2037	} else if (err_phase == 2) {
   2038		/* error in RX phase, the priority is: DW1 > DW3 > DW2 */
   2039		error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
   2040		if (error == -1) {
   2041			error = parse_dma_rx_err_code_v2_hw(
   2042					dma_rx_err_type);
   2043			if (error == -1)
   2044				error = parse_sipc_rx_err_code_v2_hw(
   2045						sipc_rx_err_type);
   2046		}
   2047	}
   2048
   2049	switch (task->task_proto) {
   2050	case SAS_PROTOCOL_SSP:
   2051	{
   2052		switch (error) {
   2053		case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
   2054		{
   2055			ts->stat = SAS_OPEN_REJECT;
   2056			ts->open_rej_reason = SAS_OREJ_NO_DEST;
   2057			break;
   2058		}
   2059		case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
   2060		{
   2061			ts->stat = SAS_OPEN_REJECT;
   2062			ts->open_rej_reason = SAS_OREJ_EPROTO;
   2063			break;
   2064		}
   2065		case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
   2066		{
   2067			ts->stat = SAS_OPEN_REJECT;
   2068			ts->open_rej_reason = SAS_OREJ_CONN_RATE;
   2069			break;
   2070		}
   2071		case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
   2072		{
   2073			ts->stat = SAS_OPEN_REJECT;
   2074			ts->open_rej_reason = SAS_OREJ_BAD_DEST;
   2075			break;
   2076		}
   2077		case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
   2078		{
   2079			ts->stat = SAS_OPEN_REJECT;
   2080			ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
   2081			break;
   2082		}
   2083		case DMA_RX_UNEXP_NORM_RESP_ERR:
   2084		case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
   2085		case DMA_RX_RESP_BUF_OVERFLOW:
   2086		{
   2087			ts->stat = SAS_OPEN_REJECT;
   2088			ts->open_rej_reason = SAS_OREJ_UNKNOWN;
   2089			break;
   2090		}
   2091		case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
   2092		{
   2093			/* not sure */
   2094			ts->stat = SAS_DEV_NO_RESPONSE;
   2095			break;
   2096		}
   2097		case DMA_RX_DATA_LEN_OVERFLOW:
   2098		{
   2099			ts->stat = SAS_DATA_OVERRUN;
   2100			ts->residual = 0;
   2101			break;
   2102		}
   2103		case DMA_RX_DATA_LEN_UNDERFLOW:
   2104		{
   2105			ts->residual = trans_tx_fail_type;
   2106			ts->stat = SAS_DATA_UNDERRUN;
   2107			break;
   2108		}
   2109		case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
   2110		case TRANS_TX_ERR_PHY_NOT_ENABLE:
   2111		case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
   2112		case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
   2113		case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
   2114		case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
   2115		case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
   2116		case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
   2117		case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
   2118		case TRANS_TX_ERR_WITH_BREAK_REQUEST:
   2119		case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
   2120		case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
   2121		case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
   2122		case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
   2123		case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
   2124		case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
   2125		case TRANS_TX_ERR_WITH_NAK_RECEVIED:
   2126		case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
   2127		case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
   2128		case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
   2129		case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
   2130		case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
   2131		case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
   2132		case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
   2133		case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
   2134		case TRANS_RX_ERR_WITH_BREAK_REQUEST:
   2135		case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
   2136		case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
   2137		case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
   2138		case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
   2139		case TRANS_TX_ERR_FRAME_TXED:
   2140		case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
   2141		case TRANS_RX_ERR_WITH_DATA_LEN0:
   2142		case TRANS_RX_ERR_WITH_BAD_HASH:
   2143		case TRANS_RX_XRDY_WLEN_ZERO_ERR:
   2144		case TRANS_RX_SSP_FRM_LEN_ERR:
   2145		case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
   2146		case DMA_TX_DATA_SGL_OVERFLOW:
   2147		case DMA_TX_UNEXP_XFER_ERR:
   2148		case DMA_TX_UNEXP_RETRANS_ERR:
   2149		case DMA_TX_XFER_LEN_OVERFLOW:
   2150		case DMA_TX_XFER_OFFSET_ERR:
   2151		case SIPC_RX_DATA_UNDERFLOW_ERR:
   2152		case DMA_RX_DATA_SGL_OVERFLOW:
   2153		case DMA_RX_DATA_OFFSET_ERR:
   2154		case DMA_RX_RDSETUP_LEN_ODD_ERR:
   2155		case DMA_RX_RDSETUP_LEN_ZERO_ERR:
   2156		case DMA_RX_RDSETUP_LEN_OVER_ERR:
   2157		case DMA_RX_SATA_FRAME_TYPE_ERR:
   2158		case DMA_RX_UNKNOWN_FRM_ERR:
   2159		{
   2160			/* This will request a retry */
   2161			ts->stat = SAS_QUEUE_FULL;
   2162			slot->abort = 1;
   2163			break;
   2164		}
   2165		default:
   2166			break;
   2167		}
   2168	}
   2169		break;
   2170	case SAS_PROTOCOL_SMP:
   2171		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
   2172		break;
   2173
   2174	case SAS_PROTOCOL_SATA:
   2175	case SAS_PROTOCOL_STP:
   2176	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
   2177	{
   2178		switch (error) {
   2179		case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
   2180		{
   2181			ts->stat = SAS_OPEN_REJECT;
   2182			ts->open_rej_reason = SAS_OREJ_NO_DEST;
   2183			break;
   2184		}
   2185		case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
   2186		{
   2187			ts->resp = SAS_TASK_UNDELIVERED;
   2188			ts->stat = SAS_DEV_NO_RESPONSE;
   2189			break;
   2190		}
   2191		case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
   2192		{
   2193			ts->stat = SAS_OPEN_REJECT;
   2194			ts->open_rej_reason = SAS_OREJ_EPROTO;
   2195			break;
   2196		}
   2197		case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
   2198		{
   2199			ts->stat = SAS_OPEN_REJECT;
   2200			ts->open_rej_reason = SAS_OREJ_CONN_RATE;
   2201			break;
   2202		}
   2203		case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
   2204		{
   2205			ts->stat = SAS_OPEN_REJECT;
   2206			ts->open_rej_reason = SAS_OREJ_CONN_RATE;
   2207			break;
   2208		}
   2209		case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
   2210		{
   2211			ts->stat = SAS_OPEN_REJECT;
   2212			ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
   2213			break;
   2214		}
   2215		case DMA_RX_RESP_BUF_OVERFLOW:
   2216		case DMA_RX_UNEXP_NORM_RESP_ERR:
   2217		case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
   2218		{
   2219			ts->stat = SAS_OPEN_REJECT;
   2220			ts->open_rej_reason = SAS_OREJ_UNKNOWN;
   2221			break;
   2222		}
   2223		case DMA_RX_DATA_LEN_OVERFLOW:
   2224		{
   2225			ts->stat = SAS_DATA_OVERRUN;
   2226			ts->residual = 0;
   2227			break;
   2228		}
   2229		case DMA_RX_DATA_LEN_UNDERFLOW:
   2230		{
   2231			ts->residual = trans_tx_fail_type;
   2232			ts->stat = SAS_DATA_UNDERRUN;
   2233			break;
   2234		}
   2235		case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
   2236		case TRANS_TX_ERR_PHY_NOT_ENABLE:
   2237		case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
   2238		case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
   2239		case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
   2240		case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
   2241		case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
   2242		case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
   2243		case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
   2244		case TRANS_TX_ERR_WITH_BREAK_REQUEST:
   2245		case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
   2246		case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
   2247		case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
   2248		case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
   2249		case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
   2250		case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
   2251		case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
   2252		case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
   2253		case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
   2254		case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
   2255		case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
   2256		case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
   2257		case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
   2258		case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
   2259		case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
   2260		case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
   2261		case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
   2262		case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
   2263		case TRANS_RX_ERR_WITH_BREAK_REQUEST:
   2264		case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
   2265		case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
   2266		case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
   2267		case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
   2268		case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
   2269		case TRANS_RX_ERR_WITH_DATA_LEN0:
   2270		case TRANS_RX_ERR_WITH_BAD_HASH:
   2271		case TRANS_RX_XRDY_WLEN_ZERO_ERR:
   2272		case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
   2273		case DMA_TX_DATA_SGL_OVERFLOW:
   2274		case DMA_TX_UNEXP_XFER_ERR:
   2275		case DMA_TX_UNEXP_RETRANS_ERR:
   2276		case DMA_TX_XFER_LEN_OVERFLOW:
   2277		case DMA_TX_XFER_OFFSET_ERR:
   2278		case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
   2279		case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
   2280		case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
   2281		case SIPC_RX_WRSETUP_LEN_ODD_ERR:
   2282		case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
   2283		case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
   2284		case SIPC_RX_SATA_UNEXP_FIS_ERR:
   2285		case DMA_RX_DATA_SGL_OVERFLOW:
   2286		case DMA_RX_DATA_OFFSET_ERR:
   2287		case DMA_RX_SATA_FRAME_TYPE_ERR:
   2288		case DMA_RX_UNEXP_RDFRAME_ERR:
   2289		case DMA_RX_PIO_DATA_LEN_ERR:
   2290		case DMA_RX_RDSETUP_STATUS_ERR:
   2291		case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
   2292		case DMA_RX_RDSETUP_STATUS_BSY_ERR:
   2293		case DMA_RX_RDSETUP_LEN_ODD_ERR:
   2294		case DMA_RX_RDSETUP_LEN_ZERO_ERR:
   2295		case DMA_RX_RDSETUP_LEN_OVER_ERR:
   2296		case DMA_RX_RDSETUP_OFFSET_ERR:
   2297		case DMA_RX_RDSETUP_ACTIVE_ERR:
   2298		case DMA_RX_RDSETUP_ESTATUS_ERR:
   2299		case DMA_RX_UNKNOWN_FRM_ERR:
   2300		case TRANS_RX_SSP_FRM_LEN_ERR:
   2301		case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
   2302		{
   2303			slot->abort = 1;
   2304			ts->stat = SAS_PHY_DOWN;
   2305			break;
   2306		}
   2307		default:
   2308		{
   2309			ts->stat = SAS_PROTO_RESPONSE;
   2310			break;
   2311		}
   2312		}
   2313		hisi_sas_sata_done(task, slot);
   2314	}
   2315		break;
   2316	default:
   2317		break;
   2318	}
   2319}
   2320
   2321static void slot_complete_v2_hw(struct hisi_hba *hisi_hba,
   2322				struct hisi_sas_slot *slot)
   2323{
   2324	struct sas_task *task = slot->task;
   2325	struct hisi_sas_device *sas_dev;
   2326	struct device *dev = hisi_hba->dev;
   2327	struct task_status_struct *ts;
   2328	struct domain_device *device;
   2329	struct sas_ha_struct *ha;
   2330	struct hisi_sas_complete_v2_hdr *complete_queue =
   2331			hisi_hba->complete_hdr[slot->cmplt_queue];
   2332	struct hisi_sas_complete_v2_hdr *complete_hdr =
   2333			&complete_queue[slot->cmplt_queue_slot];
   2334	unsigned long flags;
   2335	bool is_internal = slot->is_internal;
   2336	u32 dw0;
   2337
   2338	if (unlikely(!task || !task->lldd_task || !task->dev))
   2339		return;
   2340
   2341	ts = &task->task_status;
   2342	device = task->dev;
   2343	ha = device->port->ha;
   2344	sas_dev = device->lldd_dev;
   2345
   2346	spin_lock_irqsave(&task->task_state_lock, flags);
   2347	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
   2348	spin_unlock_irqrestore(&task->task_state_lock, flags);
   2349
   2350	memset(ts, 0, sizeof(*ts));
   2351	ts->resp = SAS_TASK_COMPLETE;
   2352
   2353	if (unlikely(!sas_dev)) {
   2354		dev_dbg(dev, "slot complete: port has no device\n");
   2355		ts->stat = SAS_PHY_DOWN;
   2356		goto out;
   2357	}
   2358
   2359	/* Use SAS+TMF status codes */
   2360	dw0 = le32_to_cpu(complete_hdr->dw0);
   2361	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
   2362		CMPLT_HDR_ABORT_STAT_OFF) {
   2363	case STAT_IO_ABORTED:
   2364		/* this io has been aborted by abort command */
   2365		ts->stat = SAS_ABORTED_TASK;
   2366		goto out;
   2367	case STAT_IO_COMPLETE:
   2368		/* internal abort command complete */
   2369		ts->stat = TMF_RESP_FUNC_SUCC;
   2370		del_timer_sync(&slot->internal_abort_timer);
   2371		goto out;
   2372	case STAT_IO_NO_DEVICE:
   2373		ts->stat = TMF_RESP_FUNC_COMPLETE;
   2374		del_timer_sync(&slot->internal_abort_timer);
   2375		goto out;
   2376	case STAT_IO_NOT_VALID:
   2377		/* abort single io, controller don't find
   2378		 * the io need to abort
   2379		 */
   2380		ts->stat = TMF_RESP_FUNC_FAILED;
   2381		del_timer_sync(&slot->internal_abort_timer);
   2382		goto out;
   2383	default:
   2384		break;
   2385	}
   2386
   2387	if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
   2388		u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
   2389				>> CMPLT_HDR_ERR_PHASE_OFF;
   2390		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
   2391
   2392		/* Analyse error happens on which phase TX or RX */
   2393		if (ERR_ON_TX_PHASE(err_phase))
   2394			slot_err_v2_hw(hisi_hba, task, slot, 1);
   2395		else if (ERR_ON_RX_PHASE(err_phase))
   2396			slot_err_v2_hw(hisi_hba, task, slot, 2);
   2397
   2398		if (ts->stat != SAS_DATA_UNDERRUN)
   2399			dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
   2400				 slot->idx, task, sas_dev->device_id,
   2401				 complete_hdr->dw0, complete_hdr->dw1,
   2402				 complete_hdr->act, complete_hdr->dw3,
   2403				 error_info[0], error_info[1],
   2404				 error_info[2], error_info[3]);
   2405
   2406		if (unlikely(slot->abort)) {
   2407			sas_task_abort(task);
   2408			return;
   2409		}
   2410		goto out;
   2411	}
   2412
   2413	switch (task->task_proto) {
   2414	case SAS_PROTOCOL_SSP:
   2415	{
   2416		struct hisi_sas_status_buffer *status_buffer =
   2417				hisi_sas_status_buf_addr_mem(slot);
   2418		struct ssp_response_iu *iu = (struct ssp_response_iu *)
   2419				&status_buffer->iu[0];
   2420
   2421		sas_ssp_task_response(dev, task, iu);
   2422		break;
   2423	}
   2424	case SAS_PROTOCOL_SMP:
   2425	{
   2426		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
   2427		void *to = page_address(sg_page(sg_resp));
   2428
   2429		ts->stat = SAS_SAM_STAT_GOOD;
   2430
   2431		dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
   2432			     DMA_TO_DEVICE);
   2433		memcpy(to + sg_resp->offset,
   2434		       hisi_sas_status_buf_addr_mem(slot) +
   2435		       sizeof(struct hisi_sas_err_record),
   2436		       sg_resp->length);
   2437		break;
   2438	}
   2439	case SAS_PROTOCOL_SATA:
   2440	case SAS_PROTOCOL_STP:
   2441	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
   2442	{
   2443		ts->stat = SAS_SAM_STAT_GOOD;
   2444		hisi_sas_sata_done(task, slot);
   2445		break;
   2446	}
   2447	default:
   2448		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
   2449		break;
   2450	}
   2451
   2452	if (!slot->port->port_attached) {
   2453		dev_warn(dev, "slot complete: port %d has removed\n",
   2454			slot->port->sas_port.id);
   2455		ts->stat = SAS_PHY_DOWN;
   2456	}
   2457
   2458out:
   2459	spin_lock_irqsave(&task->task_state_lock, flags);
   2460	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
   2461		spin_unlock_irqrestore(&task->task_state_lock, flags);
   2462		dev_info(dev, "slot complete: task(%pK) aborted\n", task);
   2463		return;
   2464	}
   2465	task->task_state_flags |= SAS_TASK_STATE_DONE;
   2466	spin_unlock_irqrestore(&task->task_state_lock, flags);
   2467	hisi_sas_slot_task_free(hisi_hba, task, slot);
   2468
   2469	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
   2470		spin_lock_irqsave(&device->done_lock, flags);
   2471		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
   2472			spin_unlock_irqrestore(&device->done_lock, flags);
   2473			dev_info(dev, "slot complete: task(%pK) ignored\n",
   2474				 task);
   2475			return;
   2476		}
   2477		spin_unlock_irqrestore(&device->done_lock, flags);
   2478	}
   2479
   2480	if (task->task_done)
   2481		task->task_done(task);
   2482}
   2483
   2484static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
   2485			  struct hisi_sas_slot *slot)
   2486{
   2487	struct sas_task *task = slot->task;
   2488	struct domain_device *device = task->dev;
   2489	struct domain_device *parent_dev = device->parent;
   2490	struct hisi_sas_device *sas_dev = device->lldd_dev;
   2491	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
   2492	struct asd_sas_port *sas_port = device->port;
   2493	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
   2494	struct sas_ata_task *ata_task = &task->ata_task;
   2495	struct sas_tmf_task *tmf = slot->tmf;
   2496	u8 *buf_cmd;
   2497	int has_data = 0, hdr_tag = 0;
   2498	u32 dw0, dw1 = 0, dw2 = 0;
   2499
   2500	/* create header */
   2501	/* dw0 */
   2502	dw0 = port->id << CMD_HDR_PORT_OFF;
   2503	if (parent_dev && dev_is_expander(parent_dev->dev_type))
   2504		dw0 |= 3 << CMD_HDR_CMD_OFF;
   2505	else
   2506		dw0 |= 4 << CMD_HDR_CMD_OFF;
   2507
   2508	if (tmf && ata_task->force_phy) {
   2509		dw0 |= CMD_HDR_FORCE_PHY_MSK;
   2510		dw0 |= (1 << ata_task->force_phy_id) << CMD_HDR_PHY_ID_OFF;
   2511	}
   2512
   2513	hdr->dw0 = cpu_to_le32(dw0);
   2514
   2515	/* dw1 */
   2516	switch (task->data_dir) {
   2517	case DMA_TO_DEVICE:
   2518		has_data = 1;
   2519		dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
   2520		break;
   2521	case DMA_FROM_DEVICE:
   2522		has_data = 1;
   2523		dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
   2524		break;
   2525	default:
   2526		dw1 &= ~CMD_HDR_DIR_MSK;
   2527	}
   2528
   2529	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
   2530			(task->ata_task.fis.control & ATA_SRST))
   2531		dw1 |= 1 << CMD_HDR_RESET_OFF;
   2532
   2533	dw1 |= (hisi_sas_get_ata_protocol(
   2534		&task->ata_task.fis, task->data_dir))
   2535		<< CMD_HDR_FRAME_TYPE_OFF;
   2536	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
   2537	hdr->dw1 = cpu_to_le32(dw1);
   2538
   2539	/* dw2 */
   2540	if (task->ata_task.use_ncq) {
   2541		struct ata_queued_cmd *qc = task->uldd_task;
   2542
   2543		hdr_tag = qc->tag;
   2544		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
   2545		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
   2546	}
   2547
   2548	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
   2549			2 << CMD_HDR_SG_MOD_OFF;
   2550	hdr->dw2 = cpu_to_le32(dw2);
   2551
   2552	/* dw3 */
   2553	hdr->transfer_tags = cpu_to_le32(slot->idx);
   2554
   2555	if (has_data)
   2556		prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
   2557					slot->n_elem);
   2558
   2559	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
   2560	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
   2561	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
   2562
   2563	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
   2564
   2565	if (likely(!task->ata_task.device_control_reg_update))
   2566		task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
   2567	/* fill in command FIS */
   2568	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
   2569}
   2570
   2571static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
   2572{
   2573	struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
   2574	struct hisi_sas_port *port = slot->port;
   2575	struct asd_sas_port *asd_sas_port;
   2576	struct asd_sas_phy *sas_phy;
   2577
   2578	if (!port)
   2579		return;
   2580
   2581	asd_sas_port = &port->sas_port;
   2582
   2583	/* Kick the hardware - send break command */
   2584	list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
   2585		struct hisi_sas_phy *phy = sas_phy->lldd_phy;
   2586		struct hisi_hba *hisi_hba = phy->hisi_hba;
   2587		int phy_no = sas_phy->id;
   2588		u32 link_dfx2;
   2589
   2590		link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
   2591		if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
   2592		    (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
   2593			u32 txid_auto;
   2594
   2595			txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
   2596							TXID_AUTO);
   2597			txid_auto |= TXID_AUTO_CTB_MSK;
   2598			hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
   2599					     txid_auto);
   2600			return;
   2601		}
   2602	}
   2603}
   2604
   2605static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
   2606			     struct hisi_sas_slot *slot)
   2607{
   2608	struct sas_task *task = slot->task;
   2609	struct sas_internal_abort_task *abort = &task->abort_task;
   2610	struct domain_device *dev = task->dev;
   2611	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
   2612	struct hisi_sas_port *port = slot->port;
   2613	struct timer_list *timer = &slot->internal_abort_timer;
   2614	struct hisi_sas_device *sas_dev = dev->lldd_dev;
   2615
   2616	/* setup the quirk timer */
   2617	timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
   2618	/* Set the timeout to 10ms less than internal abort timeout */
   2619	mod_timer(timer, jiffies + msecs_to_jiffies(100));
   2620
   2621	/* dw0 */
   2622	hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
   2623			       (port->id << CMD_HDR_PORT_OFF) |
   2624			       (dev_is_sata(dev) <<
   2625				CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
   2626			       (abort->type << CMD_HDR_ABORT_FLAG_OFF));
   2627
   2628	/* dw1 */
   2629	hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEV_ID_OFF);
   2630
   2631	/* dw7 */
   2632	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
   2633	hdr->transfer_tags = cpu_to_le32(slot->idx);
   2634}
   2635
   2636static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
   2637{
   2638	int i, res = IRQ_HANDLED;
   2639	u32 port_id, link_rate;
   2640	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   2641	struct asd_sas_phy *sas_phy = &phy->sas_phy;
   2642	struct device *dev = hisi_hba->dev;
   2643	u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
   2644	struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
   2645
   2646	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
   2647
   2648	if (is_sata_phy_v2_hw(hisi_hba, phy_no))
   2649		goto end;
   2650
   2651	del_timer(&phy->timer);
   2652
   2653	if (phy_no == 8) {
   2654		u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
   2655
   2656		port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
   2657			  PORT_STATE_PHY8_PORT_NUM_OFF;
   2658		link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
   2659			    PORT_STATE_PHY8_CONN_RATE_OFF;
   2660	} else {
   2661		port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
   2662		port_id = (port_id >> (4 * phy_no)) & 0xf;
   2663		link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
   2664		link_rate = (link_rate >> (phy_no * 4)) & 0xf;
   2665	}
   2666
   2667	if (port_id == 0xf) {
   2668		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
   2669		res = IRQ_NONE;
   2670		goto end;
   2671	}
   2672
   2673	for (i = 0; i < 6; i++) {
   2674		u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
   2675					       RX_IDAF_DWORD0 + (i * 4));
   2676		frame_rcvd[i] = __swab32(idaf);
   2677	}
   2678
   2679	sas_phy->linkrate = link_rate;
   2680	sas_phy->oob_mode = SAS_OOB_MODE;
   2681	memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
   2682	dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
   2683	phy->port_id = port_id;
   2684	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
   2685	phy->phy_type |= PORT_TYPE_SAS;
   2686	phy->phy_attached = 1;
   2687	phy->identify.device_type = id->dev_type;
   2688	phy->frame_rcvd_size =	sizeof(struct sas_identify_frame);
   2689	if (phy->identify.device_type == SAS_END_DEVICE)
   2690		phy->identify.target_port_protocols =
   2691			SAS_PROTOCOL_SSP;
   2692	else if (phy->identify.device_type != SAS_PHY_UNUSED) {
   2693		phy->identify.target_port_protocols =
   2694			SAS_PROTOCOL_SMP;
   2695		if (!timer_pending(&hisi_hba->timer))
   2696			set_link_timer_quirk(hisi_hba);
   2697	}
   2698	hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
   2699end:
   2700	if (phy->reset_completion)
   2701		complete(phy->reset_completion);
   2702	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
   2703			     CHL_INT0_SL_PHY_ENABLE_MSK);
   2704	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
   2705
   2706	return res;
   2707}
   2708
   2709static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
   2710{
   2711	u32 port_state;
   2712
   2713	port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
   2714	if (port_state & 0x1ff)
   2715		return true;
   2716
   2717	return false;
   2718}
   2719
   2720static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
   2721{
   2722	u32 phy_state, sl_ctrl, txid_auto;
   2723	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   2724	struct hisi_sas_port *port = phy->port;
   2725	struct device *dev = hisi_hba->dev;
   2726
   2727	del_timer(&phy->timer);
   2728	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
   2729
   2730	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
   2731	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
   2732	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
   2733			  GFP_ATOMIC);
   2734
   2735	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
   2736	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
   2737			     sl_ctrl & ~SL_CONTROL_CTA_MSK);
   2738	if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
   2739		if (!check_any_wideports_v2_hw(hisi_hba) &&
   2740				timer_pending(&hisi_hba->timer))
   2741			del_timer(&hisi_hba->timer);
   2742
   2743	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
   2744	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
   2745			     txid_auto | TXID_AUTO_CT3_MSK);
   2746
   2747	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
   2748	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
   2749
   2750	return IRQ_HANDLED;
   2751}
   2752
   2753static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
   2754{
   2755	struct hisi_hba *hisi_hba = p;
   2756	u32 irq_msk;
   2757	int phy_no = 0;
   2758	irqreturn_t res = IRQ_NONE;
   2759
   2760	irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
   2761		   >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
   2762	while (irq_msk) {
   2763		if (irq_msk  & 1) {
   2764			u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
   2765					    CHL_INT0);
   2766
   2767			switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
   2768					CHL_INT0_SL_PHY_ENABLE_MSK)) {
   2769
   2770			case CHL_INT0_SL_PHY_ENABLE_MSK:
   2771				/* phy up */
   2772				if (phy_up_v2_hw(phy_no, hisi_hba) ==
   2773				    IRQ_HANDLED)
   2774					res = IRQ_HANDLED;
   2775				break;
   2776
   2777			case CHL_INT0_NOT_RDY_MSK:
   2778				/* phy down */
   2779				if (phy_down_v2_hw(phy_no, hisi_hba) ==
   2780				    IRQ_HANDLED)
   2781					res = IRQ_HANDLED;
   2782				break;
   2783
   2784			case (CHL_INT0_NOT_RDY_MSK |
   2785					CHL_INT0_SL_PHY_ENABLE_MSK):
   2786				reg_value = hisi_sas_read32(hisi_hba,
   2787						PHY_STATE);
   2788				if (reg_value & BIT(phy_no)) {
   2789					/* phy up */
   2790					if (phy_up_v2_hw(phy_no, hisi_hba) ==
   2791					    IRQ_HANDLED)
   2792						res = IRQ_HANDLED;
   2793				} else {
   2794					/* phy down */
   2795					if (phy_down_v2_hw(phy_no, hisi_hba) ==
   2796					    IRQ_HANDLED)
   2797						res = IRQ_HANDLED;
   2798				}
   2799				break;
   2800
   2801			default:
   2802				break;
   2803			}
   2804
   2805		}
   2806		irq_msk >>= 1;
   2807		phy_no++;
   2808	}
   2809
   2810	return res;
   2811}
   2812
   2813static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
   2814{
   2815	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   2816	struct asd_sas_phy *sas_phy = &phy->sas_phy;
   2817	u32 bcast_status;
   2818
   2819	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
   2820	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
   2821	if ((bcast_status & RX_BCAST_CHG_MSK) &&
   2822	    !test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
   2823		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
   2824				      GFP_ATOMIC);
   2825	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
   2826			     CHL_INT0_SL_RX_BCST_ACK_MSK);
   2827	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
   2828}
   2829
   2830static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
   2831	{
   2832		.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
   2833		.msg = "dmac_tx_ecc_bad_err",
   2834	},
   2835	{
   2836		.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
   2837		.msg = "dmac_rx_ecc_bad_err",
   2838	},
   2839	{
   2840		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
   2841		.msg = "dma_tx_axi_wr_err",
   2842	},
   2843	{
   2844		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
   2845		.msg = "dma_tx_axi_rd_err",
   2846	},
   2847	{
   2848		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
   2849		.msg = "dma_rx_axi_wr_err",
   2850	},
   2851	{
   2852		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
   2853		.msg = "dma_rx_axi_rd_err",
   2854	},
   2855};
   2856
   2857static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
   2858{
   2859	struct hisi_hba *hisi_hba = p;
   2860	struct device *dev = hisi_hba->dev;
   2861	u32 ent_msk, ent_tmp, irq_msk;
   2862	int phy_no = 0;
   2863
   2864	ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
   2865	ent_tmp = ent_msk;
   2866	ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
   2867	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
   2868
   2869	irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
   2870			HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
   2871
   2872	while (irq_msk) {
   2873		u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
   2874						     CHL_INT0);
   2875		u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
   2876						     CHL_INT1);
   2877		u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
   2878						     CHL_INT2);
   2879
   2880		if ((irq_msk & (1 << phy_no)) && irq_value1) {
   2881			int i;
   2882
   2883			for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
   2884				const struct hisi_sas_hw_error *error =
   2885						&port_ecc_axi_error[i];
   2886
   2887				if (!(irq_value1 & error->irq_msk))
   2888					continue;
   2889
   2890				dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
   2891					error->msg, phy_no, irq_value1);
   2892				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
   2893			}
   2894
   2895			hisi_sas_phy_write32(hisi_hba, phy_no,
   2896					     CHL_INT1, irq_value1);
   2897		}
   2898
   2899		if ((irq_msk & (1 << phy_no)) && irq_value2) {
   2900			struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   2901
   2902			if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
   2903				dev_warn(dev, "phy%d identify timeout\n",
   2904					 phy_no);
   2905				hisi_sas_notify_phy_event(phy,
   2906						HISI_PHYE_LINK_RESET);
   2907			}
   2908
   2909			hisi_sas_phy_write32(hisi_hba, phy_no,
   2910						 CHL_INT2, irq_value2);
   2911		}
   2912
   2913		if ((irq_msk & (1 << phy_no)) && irq_value0) {
   2914			if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
   2915				phy_bcast_v2_hw(phy_no, hisi_hba);
   2916
   2917			if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
   2918				hisi_sas_phy_oob_ready(hisi_hba, phy_no);
   2919
   2920			hisi_sas_phy_write32(hisi_hba, phy_no,
   2921					CHL_INT0, irq_value0
   2922					& (~CHL_INT0_HOTPLUG_TOUT_MSK)
   2923					& (~CHL_INT0_SL_PHY_ENABLE_MSK)
   2924					& (~CHL_INT0_NOT_RDY_MSK));
   2925		}
   2926		irq_msk &= ~(1 << phy_no);
   2927		phy_no++;
   2928	}
   2929
   2930	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
   2931
   2932	return IRQ_HANDLED;
   2933}
   2934
   2935static void
   2936one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
   2937{
   2938	struct device *dev = hisi_hba->dev;
   2939	const struct hisi_sas_hw_error *ecc_error;
   2940	u32 val;
   2941	int i;
   2942
   2943	for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
   2944		ecc_error = &one_bit_ecc_errors[i];
   2945		if (irq_value & ecc_error->irq_msk) {
   2946			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
   2947			val &= ecc_error->msk;
   2948			val >>= ecc_error->shift;
   2949			dev_warn(dev, "%s found: mem addr is 0x%08X\n",
   2950				 ecc_error->msg, val);
   2951		}
   2952	}
   2953}
   2954
   2955static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
   2956		u32 irq_value)
   2957{
   2958	struct device *dev = hisi_hba->dev;
   2959	const struct hisi_sas_hw_error *ecc_error;
   2960	u32 val;
   2961	int i;
   2962
   2963	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
   2964		ecc_error = &multi_bit_ecc_errors[i];
   2965		if (irq_value & ecc_error->irq_msk) {
   2966			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
   2967			val &= ecc_error->msk;
   2968			val >>= ecc_error->shift;
   2969			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
   2970				ecc_error->msg, irq_value, val);
   2971			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
   2972		}
   2973	}
   2974
   2975	return;
   2976}
   2977
   2978static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
   2979{
   2980	struct hisi_hba *hisi_hba = p;
   2981	u32 irq_value, irq_msk;
   2982
   2983	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
   2984	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
   2985
   2986	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
   2987	if (irq_value) {
   2988		one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
   2989		multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
   2990	}
   2991
   2992	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
   2993	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
   2994
   2995	return IRQ_HANDLED;
   2996}
   2997
   2998static const struct hisi_sas_hw_error axi_error[] = {
   2999	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
   3000	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
   3001	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
   3002	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
   3003	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
   3004	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
   3005	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
   3006	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
   3007	{}
   3008};
   3009
   3010static const struct hisi_sas_hw_error fifo_error[] = {
   3011	{ .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
   3012	{ .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
   3013	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
   3014	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
   3015	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
   3016	{}
   3017};
   3018
   3019static const struct hisi_sas_hw_error fatal_axi_errors[] = {
   3020	{
   3021		.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
   3022		.msg = "write pointer and depth",
   3023	},
   3024	{
   3025		.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
   3026		.msg = "iptt no match slot",
   3027	},
   3028	{
   3029		.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
   3030		.msg = "read pointer and depth",
   3031	},
   3032	{
   3033		.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
   3034		.reg = HGC_AXI_FIFO_ERR_INFO,
   3035		.sub = axi_error,
   3036	},
   3037	{
   3038		.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
   3039		.reg = HGC_AXI_FIFO_ERR_INFO,
   3040		.sub = fifo_error,
   3041	},
   3042	{
   3043		.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
   3044		.msg = "LM add/fetch list",
   3045	},
   3046	{
   3047		.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
   3048		.msg = "SAS_HGC_ABT fetch LM list",
   3049	},
   3050};
   3051
   3052static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
   3053{
   3054	struct hisi_hba *hisi_hba = p;
   3055	u32 irq_value, irq_msk, err_value;
   3056	struct device *dev = hisi_hba->dev;
   3057	const struct hisi_sas_hw_error *axi_error;
   3058	int i;
   3059
   3060	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
   3061	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
   3062
   3063	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
   3064
   3065	for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
   3066		axi_error = &fatal_axi_errors[i];
   3067		if (!(irq_value & axi_error->irq_msk))
   3068			continue;
   3069
   3070		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
   3071				 1 << axi_error->shift);
   3072		if (axi_error->sub) {
   3073			const struct hisi_sas_hw_error *sub = axi_error->sub;
   3074
   3075			err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
   3076			for (; sub->msk || sub->msg; sub++) {
   3077				if (!(err_value & sub->msk))
   3078					continue;
   3079				dev_err(dev, "%s (0x%x) found!\n",
   3080					sub->msg, irq_value);
   3081				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
   3082			}
   3083		} else {
   3084			dev_err(dev, "%s (0x%x) found!\n",
   3085				axi_error->msg, irq_value);
   3086			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
   3087		}
   3088	}
   3089
   3090	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
   3091		u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
   3092		u32 dev_id = reg_val & ITCT_DEV_MSK;
   3093		struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
   3094
   3095		hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
   3096		dev_dbg(dev, "clear ITCT ok\n");
   3097		complete(sas_dev->completion);
   3098	}
   3099
   3100	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
   3101	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
   3102
   3103	return IRQ_HANDLED;
   3104}
   3105
   3106static irqreturn_t  cq_thread_v2_hw(int irq_no, void *p)
   3107{
   3108	struct hisi_sas_cq *cq = p;
   3109	struct hisi_hba *hisi_hba = cq->hisi_hba;
   3110	struct hisi_sas_slot *slot;
   3111	struct hisi_sas_itct *itct;
   3112	struct hisi_sas_complete_v2_hdr *complete_queue;
   3113	u32 rd_point = cq->rd_point, wr_point, dev_id;
   3114	int queue = cq->id;
   3115
   3116	if (unlikely(hisi_hba->reject_stp_links_msk))
   3117		phys_try_accept_stp_links_v2_hw(hisi_hba);
   3118
   3119	complete_queue = hisi_hba->complete_hdr[queue];
   3120
   3121	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
   3122				   (0x14 * queue));
   3123
   3124	while (rd_point != wr_point) {
   3125		struct hisi_sas_complete_v2_hdr *complete_hdr;
   3126		int iptt;
   3127
   3128		complete_hdr = &complete_queue[rd_point];
   3129
   3130		/* Check for NCQ completion */
   3131		if (complete_hdr->act) {
   3132			u32 act_tmp = le32_to_cpu(complete_hdr->act);
   3133			int ncq_tag_count = ffs(act_tmp);
   3134			u32 dw1 = le32_to_cpu(complete_hdr->dw1);
   3135
   3136			dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
   3137				 CMPLT_HDR_DEV_ID_OFF;
   3138			itct = &hisi_hba->itct[dev_id];
   3139
   3140			/* The NCQ tags are held in the itct header */
   3141			while (ncq_tag_count) {
   3142				__le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
   3143				u64 ncq_tag;
   3144
   3145				ncq_tag_count--;
   3146				__ncq_tag = _ncq_tag[ncq_tag_count / 5];
   3147				ncq_tag = le64_to_cpu(__ncq_tag);
   3148				iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
   3149				       0xfff;
   3150
   3151				slot = &hisi_hba->slot_info[iptt];
   3152				slot->cmplt_queue_slot = rd_point;
   3153				slot->cmplt_queue = queue;
   3154				slot_complete_v2_hw(hisi_hba, slot);
   3155
   3156				act_tmp &= ~(1 << ncq_tag_count);
   3157				ncq_tag_count = ffs(act_tmp);
   3158			}
   3159		} else {
   3160			u32 dw1 = le32_to_cpu(complete_hdr->dw1);
   3161
   3162			iptt = dw1 & CMPLT_HDR_IPTT_MSK;
   3163			slot = &hisi_hba->slot_info[iptt];
   3164			slot->cmplt_queue_slot = rd_point;
   3165			slot->cmplt_queue = queue;
   3166			slot_complete_v2_hw(hisi_hba, slot);
   3167		}
   3168
   3169		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
   3170			rd_point = 0;
   3171	}
   3172
   3173	/* update rd_point */
   3174	cq->rd_point = rd_point;
   3175	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
   3176
   3177	return IRQ_HANDLED;
   3178}
   3179
   3180static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
   3181{
   3182	struct hisi_sas_cq *cq = p;
   3183	struct hisi_hba *hisi_hba = cq->hisi_hba;
   3184	int queue = cq->id;
   3185
   3186	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
   3187
   3188	return IRQ_WAKE_THREAD;
   3189}
   3190
   3191static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
   3192{
   3193	struct hisi_sas_phy *phy = p;
   3194	struct hisi_hba *hisi_hba = phy->hisi_hba;
   3195	struct asd_sas_phy *sas_phy = &phy->sas_phy;
   3196	struct device *dev = hisi_hba->dev;
   3197	struct	hisi_sas_initial_fis *initial_fis;
   3198	struct dev_to_host_fis *fis;
   3199	u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
   3200	irqreturn_t res = IRQ_HANDLED;
   3201	u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
   3202	int phy_no, offset;
   3203
   3204	del_timer(&phy->timer);
   3205
   3206	phy_no = sas_phy->id;
   3207	initial_fis = &hisi_hba->initial_fis[phy_no];
   3208	fis = &initial_fis->fis;
   3209
   3210	offset = 4 * (phy_no / 4);
   3211	ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
   3212	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
   3213			 ent_msk | 1 << ((phy_no % 4) * 8));
   3214
   3215	ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
   3216	ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
   3217			     (phy_no % 4)));
   3218	ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
   3219	if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
   3220		dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
   3221		res = IRQ_NONE;
   3222		goto end;
   3223	}
   3224
   3225	/* check ERR bit of Status Register */
   3226	if (fis->status & ATA_ERR) {
   3227		dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
   3228			 fis->status);
   3229		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
   3230		res = IRQ_NONE;
   3231		goto end;
   3232	}
   3233
   3234	if (unlikely(phy_no == 8)) {
   3235		u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
   3236
   3237		port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
   3238			  PORT_STATE_PHY8_PORT_NUM_OFF;
   3239		link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
   3240			    PORT_STATE_PHY8_CONN_RATE_OFF;
   3241	} else {
   3242		port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
   3243		port_id = (port_id >> (4 * phy_no)) & 0xf;
   3244		link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
   3245		link_rate = (link_rate >> (phy_no * 4)) & 0xf;
   3246	}
   3247
   3248	if (port_id == 0xf) {
   3249		dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
   3250		res = IRQ_NONE;
   3251		goto end;
   3252	}
   3253
   3254	sas_phy->linkrate = link_rate;
   3255	hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
   3256						HARD_PHY_LINKRATE);
   3257	phy->maximum_linkrate = hard_phy_linkrate & 0xf;
   3258	phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
   3259
   3260	sas_phy->oob_mode = SATA_OOB_MODE;
   3261	/* Make up some unique SAS address */
   3262	attached_sas_addr[0] = 0x50;
   3263	attached_sas_addr[6] = hisi_hba->shost->host_no;
   3264	attached_sas_addr[7] = phy_no;
   3265	memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
   3266	memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
   3267	dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
   3268	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
   3269	phy->port_id = port_id;
   3270	phy->phy_type |= PORT_TYPE_SATA;
   3271	phy->phy_attached = 1;
   3272	phy->identify.device_type = SAS_SATA_DEV;
   3273	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
   3274	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
   3275	hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
   3276
   3277	if (phy->reset_completion)
   3278		complete(phy->reset_completion);
   3279end:
   3280	hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
   3281	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
   3282
   3283	return res;
   3284}
   3285
   3286static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
   3287	int_phy_updown_v2_hw,
   3288	int_chnl_int_v2_hw,
   3289};
   3290
   3291static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
   3292	fatal_ecc_int_v2_hw,
   3293	fatal_axi_int_v2_hw
   3294};
   3295
   3296#define CQ0_IRQ_INDEX (96)
   3297
   3298static int hisi_sas_v2_interrupt_preinit(struct hisi_hba *hisi_hba)
   3299{
   3300	struct platform_device *pdev = hisi_hba->platform_dev;
   3301	struct Scsi_Host *shost = hisi_hba->shost;
   3302	struct irq_affinity desc = {
   3303		.pre_vectors = CQ0_IRQ_INDEX,
   3304		.post_vectors = 16,
   3305	};
   3306	int resv = desc.pre_vectors + desc.post_vectors, minvec = resv + 1, nvec;
   3307
   3308	nvec = devm_platform_get_irqs_affinity(pdev, &desc, minvec, 128,
   3309					       &hisi_hba->irq_map);
   3310	if (nvec < 0)
   3311		return nvec;
   3312
   3313	shost->nr_hw_queues = hisi_hba->cq_nvecs = nvec - resv;
   3314
   3315	return 0;
   3316}
   3317
   3318/*
   3319 * There is a limitation in the hip06 chipset that we need
   3320 * to map in all mbigen interrupts, even if they are not used.
   3321 */
   3322static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
   3323{
   3324	struct platform_device *pdev = hisi_hba->platform_dev;
   3325	struct device *dev = &pdev->dev;
   3326	int irq, rc = 0;
   3327	int i, phy_no, fatal_no, queue_no;
   3328
   3329	for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
   3330		irq = hisi_hba->irq_map[i + 1]; /* Phy up/down is irq1 */
   3331		rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
   3332				      DRV_NAME " phy", hisi_hba);
   3333		if (rc) {
   3334			dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
   3335				irq, rc);
   3336			rc = -ENOENT;
   3337			goto err_out;
   3338		}
   3339	}
   3340
   3341	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
   3342		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
   3343
   3344		irq = hisi_hba->irq_map[phy_no + 72];
   3345		rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
   3346				      DRV_NAME " sata", phy);
   3347		if (rc) {
   3348			dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n",
   3349				irq, rc);
   3350			rc = -ENOENT;
   3351			goto err_out;
   3352		}
   3353	}
   3354
   3355	for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
   3356		irq = hisi_hba->irq_map[fatal_no + 81];
   3357		rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
   3358				      DRV_NAME " fatal", hisi_hba);
   3359		if (rc) {
   3360			dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
   3361				irq, rc);
   3362			rc = -ENOENT;
   3363			goto err_out;
   3364		}
   3365	}
   3366
   3367	for (queue_no = 0; queue_no < hisi_hba->cq_nvecs; queue_no++) {
   3368		struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
   3369
   3370		cq->irq_no = hisi_hba->irq_map[queue_no + 96];
   3371		rc = devm_request_threaded_irq(dev, cq->irq_no,
   3372					       cq_interrupt_v2_hw,
   3373					       cq_thread_v2_hw, IRQF_ONESHOT,
   3374					       DRV_NAME " cq", cq);
   3375		if (rc) {
   3376			dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
   3377					cq->irq_no, rc);
   3378			rc = -ENOENT;
   3379			goto err_out;
   3380		}
   3381		cq->irq_mask = irq_get_affinity_mask(cq->irq_no);
   3382	}
   3383err_out:
   3384	return rc;
   3385}
   3386
   3387static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
   3388{
   3389	int rc;
   3390
   3391	memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
   3392
   3393	rc = hw_init_v2_hw(hisi_hba);
   3394	if (rc)
   3395		return rc;
   3396
   3397	rc = interrupt_init_v2_hw(hisi_hba);
   3398	if (rc)
   3399		return rc;
   3400
   3401	return 0;
   3402}
   3403
   3404static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
   3405{
   3406	struct platform_device *pdev = hisi_hba->platform_dev;
   3407	int i;
   3408
   3409	for (i = 0; i < hisi_hba->queue_count; i++)
   3410		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
   3411
   3412	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
   3413	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
   3414	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
   3415	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
   3416
   3417	for (i = 0; i < hisi_hba->n_phy; i++) {
   3418		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
   3419		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
   3420	}
   3421
   3422	for (i = 0; i < 128; i++)
   3423		synchronize_irq(platform_get_irq(pdev, i));
   3424}
   3425
   3426
   3427static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
   3428{
   3429	return hisi_sas_read32(hisi_hba, PHY_STATE);
   3430}
   3431
   3432static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
   3433{
   3434	struct device *dev = hisi_hba->dev;
   3435	int rc, cnt;
   3436
   3437	interrupt_disable_v2_hw(hisi_hba);
   3438	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
   3439
   3440	hisi_sas_stop_phys(hisi_hba);
   3441
   3442	mdelay(10);
   3443
   3444	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
   3445
   3446	/* wait until bus idle */
   3447	cnt = 0;
   3448	while (1) {
   3449		u32 status = hisi_sas_read32_relaxed(hisi_hba,
   3450				AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
   3451
   3452		if (status == 0x3)
   3453			break;
   3454
   3455		udelay(10);
   3456		if (cnt++ > 10) {
   3457			dev_err(dev, "wait axi bus state to idle timeout!\n");
   3458			return -1;
   3459		}
   3460	}
   3461
   3462	hisi_sas_init_mem(hisi_hba);
   3463
   3464	rc = hw_init_v2_hw(hisi_hba);
   3465	if (rc)
   3466		return rc;
   3467
   3468	phys_reject_stp_links_v2_hw(hisi_hba);
   3469
   3470	return 0;
   3471}
   3472
   3473static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
   3474			u8 reg_index, u8 reg_count, u8 *write_data)
   3475{
   3476	struct device *dev = hisi_hba->dev;
   3477	int phy_no, count;
   3478
   3479	if (!hisi_hba->sgpio_regs)
   3480		return -EOPNOTSUPP;
   3481
   3482	switch (reg_type) {
   3483	case SAS_GPIO_REG_TX:
   3484		count = reg_count * 4;
   3485		count = min(count, hisi_hba->n_phy);
   3486
   3487		for (phy_no = 0; phy_no < count; phy_no++) {
   3488			/*
   3489			 * GPIO_TX[n] register has the highest numbered drive
   3490			 * of the four in the first byte and the lowest
   3491			 * numbered drive in the fourth byte.
   3492			 * See SFF-8485 Rev. 0.7 Table 24.
   3493			 */
   3494			void __iomem  *reg_addr = hisi_hba->sgpio_regs +
   3495					reg_index * 4 + phy_no;
   3496			int data_idx = phy_no + 3 - (phy_no % 4) * 2;
   3497
   3498			writeb(write_data[data_idx], reg_addr);
   3499		}
   3500
   3501		break;
   3502	default:
   3503		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
   3504			reg_type);
   3505		return -EINVAL;
   3506	}
   3507
   3508	return 0;
   3509}
   3510
   3511static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
   3512					     int delay_ms, int timeout_ms)
   3513{
   3514	struct device *dev = hisi_hba->dev;
   3515	int entries, entries_old = 0, time;
   3516
   3517	for (time = 0; time < timeout_ms; time += delay_ms) {
   3518		entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
   3519		if (entries == entries_old)
   3520			break;
   3521
   3522		entries_old = entries;
   3523		msleep(delay_ms);
   3524	}
   3525
   3526	if (time >= timeout_ms) {
   3527		dev_dbg(dev, "Wait commands complete timeout!\n");
   3528		return;
   3529	}
   3530
   3531	dev_dbg(dev, "wait commands complete %dms\n", time);
   3532
   3533}
   3534
   3535static struct attribute *host_v2_hw_attrs[] = {
   3536	&dev_attr_phy_event_threshold.attr,
   3537	NULL
   3538};
   3539
   3540ATTRIBUTE_GROUPS(host_v2_hw);
   3541
   3542static int map_queues_v2_hw(struct Scsi_Host *shost)
   3543{
   3544	struct hisi_hba *hisi_hba = shost_priv(shost);
   3545	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
   3546	const struct cpumask *mask;
   3547	unsigned int queue, cpu;
   3548
   3549	for (queue = 0; queue < qmap->nr_queues; queue++) {
   3550		mask = irq_get_affinity_mask(hisi_hba->irq_map[96 + queue]);
   3551		if (!mask)
   3552			continue;
   3553
   3554		for_each_cpu(cpu, mask)
   3555			qmap->mq_map[cpu] = qmap->queue_offset + queue;
   3556	}
   3557
   3558	return 0;
   3559
   3560}
   3561
   3562static struct scsi_host_template sht_v2_hw = {
   3563	.name			= DRV_NAME,
   3564	.proc_name		= DRV_NAME,
   3565	.module			= THIS_MODULE,
   3566	.queuecommand		= sas_queuecommand,
   3567	.dma_need_drain		= ata_scsi_dma_need_drain,
   3568	.target_alloc		= sas_target_alloc,
   3569	.slave_configure	= hisi_sas_slave_configure,
   3570	.scan_finished		= hisi_sas_scan_finished,
   3571	.scan_start		= hisi_sas_scan_start,
   3572	.change_queue_depth	= sas_change_queue_depth,
   3573	.bios_param		= sas_bios_param,
   3574	.this_id		= -1,
   3575	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
   3576	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
   3577	.eh_device_reset_handler = sas_eh_device_reset_handler,
   3578	.eh_target_reset_handler = sas_eh_target_reset_handler,
   3579	.slave_alloc		= hisi_sas_slave_alloc,
   3580	.target_destroy		= sas_target_destroy,
   3581	.ioctl			= sas_ioctl,
   3582#ifdef CONFIG_COMPAT
   3583	.compat_ioctl		= sas_ioctl,
   3584#endif
   3585	.shost_groups		= host_v2_hw_groups,
   3586	.host_reset		= hisi_sas_host_reset,
   3587	.map_queues		= map_queues_v2_hw,
   3588	.host_tagset		= 1,
   3589};
   3590
   3591static const struct hisi_sas_hw hisi_sas_v2_hw = {
   3592	.hw_init = hisi_sas_v2_init,
   3593	.interrupt_preinit = hisi_sas_v2_interrupt_preinit,
   3594	.setup_itct = setup_itct_v2_hw,
   3595	.slot_index_alloc = slot_index_alloc_quirk_v2_hw,
   3596	.alloc_dev = alloc_dev_quirk_v2_hw,
   3597	.sl_notify_ssp = sl_notify_ssp_v2_hw,
   3598	.get_wideport_bitmap = get_wideport_bitmap_v2_hw,
   3599	.clear_itct = clear_itct_v2_hw,
   3600	.free_device = free_device_v2_hw,
   3601	.prep_smp = prep_smp_v2_hw,
   3602	.prep_ssp = prep_ssp_v2_hw,
   3603	.prep_stp = prep_ata_v2_hw,
   3604	.prep_abort = prep_abort_v2_hw,
   3605	.start_delivery = start_delivery_v2_hw,
   3606	.phys_init = phys_init_v2_hw,
   3607	.phy_start = start_phy_v2_hw,
   3608	.phy_disable = disable_phy_v2_hw,
   3609	.phy_hard_reset = phy_hard_reset_v2_hw,
   3610	.get_events = phy_get_events_v2_hw,
   3611	.phy_set_linkrate = phy_set_linkrate_v2_hw,
   3612	.phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
   3613	.complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
   3614	.soft_reset = soft_reset_v2_hw,
   3615	.get_phys_state = get_phys_state_v2_hw,
   3616	.write_gpio = write_gpio_v2_hw,
   3617	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
   3618	.sht = &sht_v2_hw,
   3619};
   3620
   3621static int hisi_sas_v2_probe(struct platform_device *pdev)
   3622{
   3623	return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
   3624}
   3625
   3626static int hisi_sas_v2_remove(struct platform_device *pdev)
   3627{
   3628	return hisi_sas_remove(pdev);
   3629}
   3630
   3631static const struct of_device_id sas_v2_of_match[] = {
   3632	{ .compatible = "hisilicon,hip06-sas-v2",},
   3633	{ .compatible = "hisilicon,hip07-sas-v2",},
   3634	{},
   3635};
   3636MODULE_DEVICE_TABLE(of, sas_v2_of_match);
   3637
   3638static const struct acpi_device_id sas_v2_acpi_match[] = {
   3639	{ "HISI0162", 0 },
   3640	{ }
   3641};
   3642
   3643MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
   3644
   3645static struct platform_driver hisi_sas_v2_driver = {
   3646	.probe = hisi_sas_v2_probe,
   3647	.remove = hisi_sas_v2_remove,
   3648	.driver = {
   3649		.name = DRV_NAME,
   3650		.of_match_table = sas_v2_of_match,
   3651		.acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
   3652	},
   3653};
   3654
   3655module_platform_driver(hisi_sas_v2_driver);
   3656
   3657MODULE_LICENSE("GPL");
   3658MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
   3659MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
   3660MODULE_ALIAS("platform:" DRV_NAME);