lpfc_hw4.h (178497B)
1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23#include <uapi/scsi/fc/fc_fs.h> 24#include <uapi/scsi/fc/fc_els.h> 25 26/* Macros to deal with bit fields. Each bit field must have 3 #defines 27 * associated with it (_SHIFT, _MASK, and _WORD). 28 * EG. For a bit field that is in the 7th bit of the "field4" field of a 29 * structure and is 2 bits in size the following #defines must exist: 30 * struct temp { 31 * uint32_t field1; 32 * uint32_t field2; 33 * uint32_t field3; 34 * uint32_t field4; 35 * #define example_bit_field_SHIFT 7 36 * #define example_bit_field_MASK 0x03 37 * #define example_bit_field_WORD field4 38 * uint32_t field5; 39 * }; 40 * Then the macros below may be used to get or set the value of that field. 41 * EG. To get the value of the bit field from the above example: 42 * struct temp t1; 43 * value = bf_get(example_bit_field, &t1); 44 * And then to set that bit field: 45 * bf_set(example_bit_field, &t1, 2); 46 * Or clear that bit field: 47 * bf_set(example_bit_field, &t1, 0); 48 */ 49#define bf_get_be32(name, ptr) \ 50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 51#define bf_get_le32(name, ptr) \ 52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 53#define bf_get(name, ptr) \ 54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 55#define bf_set_le32(name, ptr, value) \ 56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 58 ~(name##_MASK << name##_SHIFT))))) 59#define bf_set(name, ptr, value) \ 60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 62 63#define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF) 64#define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF) 65 66#define get_job_ulpword(x, y) ((x)->iocb.un.ulpWord[y]) 67 68#define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y) 69#define set_job_ulpword4(x, y) ((&(x)->wcqe_cmpl)->parameter = y) 70 71struct dma_address { 72 uint32_t addr_lo; 73 uint32_t addr_hi; 74}; 75 76struct lpfc_sli_intf { 77 uint32_t word0; 78#define lpfc_sli_intf_valid_SHIFT 29 79#define lpfc_sli_intf_valid_MASK 0x00000007 80#define lpfc_sli_intf_valid_WORD word0 81#define LPFC_SLI_INTF_VALID 6 82#define lpfc_sli_intf_sli_hint2_SHIFT 24 83#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 84#define lpfc_sli_intf_sli_hint2_WORD word0 85#define LPFC_SLI_INTF_SLI_HINT2_NONE 0 86#define lpfc_sli_intf_sli_hint1_SHIFT 16 87#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 88#define lpfc_sli_intf_sli_hint1_WORD word0 89#define LPFC_SLI_INTF_SLI_HINT1_NONE 0 90#define LPFC_SLI_INTF_SLI_HINT1_1 1 91#define LPFC_SLI_INTF_SLI_HINT1_2 2 92#define lpfc_sli_intf_if_type_SHIFT 12 93#define lpfc_sli_intf_if_type_MASK 0x0000000F 94#define lpfc_sli_intf_if_type_WORD word0 95#define LPFC_SLI_INTF_IF_TYPE_0 0 96#define LPFC_SLI_INTF_IF_TYPE_1 1 97#define LPFC_SLI_INTF_IF_TYPE_2 2 98#define LPFC_SLI_INTF_IF_TYPE_6 6 99#define lpfc_sli_intf_sli_family_SHIFT 8 100#define lpfc_sli_intf_sli_family_MASK 0x0000000F 101#define lpfc_sli_intf_sli_family_WORD word0 102#define LPFC_SLI_INTF_FAMILY_BE2 0x0 103#define LPFC_SLI_INTF_FAMILY_BE3 0x1 104#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 105#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 106#define LPFC_SLI_INTF_FAMILY_G6 0xc 107#define LPFC_SLI_INTF_FAMILY_G7 0xd 108#define LPFC_SLI_INTF_FAMILY_G7P 0xe 109#define lpfc_sli_intf_slirev_SHIFT 4 110#define lpfc_sli_intf_slirev_MASK 0x0000000F 111#define lpfc_sli_intf_slirev_WORD word0 112#define LPFC_SLI_INTF_REV_SLI3 3 113#define LPFC_SLI_INTF_REV_SLI4 4 114#define lpfc_sli_intf_func_type_SHIFT 0 115#define lpfc_sli_intf_func_type_MASK 0x00000001 116#define lpfc_sli_intf_func_type_WORD word0 117#define LPFC_SLI_INTF_IF_TYPE_PHYS 0 118#define LPFC_SLI_INTF_IF_TYPE_VIRT 1 119}; 120 121#define LPFC_SLI4_MBX_EMBED true 122#define LPFC_SLI4_MBX_NEMBED false 123 124#define LPFC_SLI4_MB_WORD_COUNT 64 125#define LPFC_MAX_MQ_PAGE 8 126#define LPFC_MAX_WQ_PAGE_V0 4 127#define LPFC_MAX_WQ_PAGE 8 128#define LPFC_MAX_RQ_PAGE 8 129#define LPFC_MAX_CQ_PAGE 4 130#define LPFC_MAX_EQ_PAGE 8 131 132#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 133#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 134#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 135 136/* Define SLI4 Alignment requirements. */ 137#define LPFC_ALIGN_16_BYTE 16 138#define LPFC_ALIGN_64_BYTE 64 139#define SLI4_PAGE_SIZE 4096 140 141/* Define SLI4 specific definitions. */ 142#define LPFC_MQ_CQE_BYTE_OFFSET 256 143#define LPFC_MBX_CMD_HDR_LENGTH 16 144#define LPFC_MBX_ERROR_RANGE 0x4000 145#define LPFC_BMBX_BIT1_ADDR_HI 0x2 146#define LPFC_BMBX_BIT1_ADDR_LO 0 147#define LPFC_RPI_HDR_COUNT 64 148#define LPFC_HDR_TEMPLATE_SIZE 4096 149#define LPFC_RPI_ALLOC_ERROR 0xFFFF 150#define LPFC_FCF_RECORD_WD_CNT 132 151#define LPFC_ENTIRE_FCF_DATABASE 0 152#define LPFC_DFLT_FCF_INDEX 0 153 154/* Virtual function numbers */ 155#define LPFC_VF0 0 156#define LPFC_VF1 1 157#define LPFC_VF2 2 158#define LPFC_VF3 3 159#define LPFC_VF4 4 160#define LPFC_VF5 5 161#define LPFC_VF6 6 162#define LPFC_VF7 7 163#define LPFC_VF8 8 164#define LPFC_VF9 9 165#define LPFC_VF10 10 166#define LPFC_VF11 11 167#define LPFC_VF12 12 168#define LPFC_VF13 13 169#define LPFC_VF14 14 170#define LPFC_VF15 15 171#define LPFC_VF16 16 172#define LPFC_VF17 17 173#define LPFC_VF18 18 174#define LPFC_VF19 19 175#define LPFC_VF20 20 176#define LPFC_VF21 21 177#define LPFC_VF22 22 178#define LPFC_VF23 23 179#define LPFC_VF24 24 180#define LPFC_VF25 25 181#define LPFC_VF26 26 182#define LPFC_VF27 27 183#define LPFC_VF28 28 184#define LPFC_VF29 29 185#define LPFC_VF30 30 186#define LPFC_VF31 31 187 188/* PCI function numbers */ 189#define LPFC_PCI_FUNC0 0 190#define LPFC_PCI_FUNC1 1 191#define LPFC_PCI_FUNC2 2 192#define LPFC_PCI_FUNC3 3 193#define LPFC_PCI_FUNC4 4 194 195/* SLI4 interface type-2 PDEV_CTL register */ 196#define LPFC_CTL_PDEV_CTL_OFFSET 0x414 197#define LPFC_CTL_PDEV_CTL_DRST 0x00000001 198#define LPFC_CTL_PDEV_CTL_FRST 0x00000002 199#define LPFC_CTL_PDEV_CTL_DD 0x00000004 200#define LPFC_CTL_PDEV_CTL_LC 0x00000008 201#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 202#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 203#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 204#define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 205 206#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 207 208/* Active interrupt test count */ 209#define LPFC_ACT_INTR_CNT 4 210 211/* Algrithmns for scheduling FCP commands to WQs */ 212#define LPFC_FCP_SCHED_BY_HDWQ 0 213#define LPFC_FCP_SCHED_BY_CPU 1 214 215/* Algrithmns for NameServer Query after RSCN */ 216#define LPFC_NS_QUERY_GID_FT 0 217#define LPFC_NS_QUERY_GID_PT 1 218 219/* Delay Multiplier constant */ 220#define LPFC_DMULT_CONST 651042 221#define LPFC_DMULT_MAX 1023 222 223/* Configuration of Interrupts / sec for entire HBA port */ 224#define LPFC_MIN_IMAX 5000 225#define LPFC_MAX_IMAX 5000000 226#define LPFC_DEF_IMAX 0 227 228#define LPFC_MAX_AUTO_EQ_DELAY 120 229#define LPFC_EQ_DELAY_STEP 15 230#define LPFC_EQD_ISR_TRIGGER 20000 231/* 1s intervals */ 232#define LPFC_EQ_DELAY_MSECS 1000 233 234#define LPFC_MIN_CPU_MAP 0 235#define LPFC_MAX_CPU_MAP 1 236#define LPFC_HBA_CPU_MAP 1 237 238/* PORT_CAPABILITIES constants. */ 239#define LPFC_MAX_SUPPORTED_PAGES 8 240 241enum ulp_bde64_word3 { 242 ULP_BDE64_SIZE_MASK = 0xffffff, 243 244 ULP_BDE64_TYPE_SHIFT = 24, 245 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT), 246 247 /* BDE (Host_resident) */ 248 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT), 249 /* Immediate Data BDE */ 250 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT), 251 /* BDE (Port-resident) */ 252 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT), 253 /* Input BDE (Host-resident) */ 254 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT), 255 /* Input BDE (Port-resident) */ 256 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT), 257 /* BLP (Host-resident) */ 258 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT), 259 /* BLP (Port-resident) */ 260 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT), 261}; 262 263struct ulp_bde64_le { 264 __le32 type_size; /* type 31:24, size 23:0 */ 265 __le32 addr_low; 266 __le32 addr_high; 267}; 268 269struct ulp_bde64 { 270 union ULP_BDE_TUS { 271 uint32_t w; 272 struct { 273#ifdef __BIG_ENDIAN_BITFIELD 274 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 275 VALUE !! */ 276 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 277#else /* __LITTLE_ENDIAN_BITFIELD */ 278 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 279 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 280 VALUE !! */ 281#endif 282#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 283#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 284#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 285#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 286#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 287#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 288#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 289 } f; 290 } tus; 291 uint32_t addrLow; 292 uint32_t addrHigh; 293}; 294 295/* Maximun size of immediate data that can fit into a 128 byte WQE */ 296#define LPFC_MAX_BDE_IMM_SIZE 64 297 298struct lpfc_sli4_flags { 299 uint32_t word0; 300#define lpfc_idx_rsrc_rdy_SHIFT 0 301#define lpfc_idx_rsrc_rdy_MASK 0x00000001 302#define lpfc_idx_rsrc_rdy_WORD word0 303#define LPFC_IDX_RSRC_RDY 1 304#define lpfc_rpi_rsrc_rdy_SHIFT 1 305#define lpfc_rpi_rsrc_rdy_MASK 0x00000001 306#define lpfc_rpi_rsrc_rdy_WORD word0 307#define LPFC_RPI_RSRC_RDY 1 308#define lpfc_vpi_rsrc_rdy_SHIFT 2 309#define lpfc_vpi_rsrc_rdy_MASK 0x00000001 310#define lpfc_vpi_rsrc_rdy_WORD word0 311#define LPFC_VPI_RSRC_RDY 1 312#define lpfc_vfi_rsrc_rdy_SHIFT 3 313#define lpfc_vfi_rsrc_rdy_MASK 0x00000001 314#define lpfc_vfi_rsrc_rdy_WORD word0 315#define LPFC_VFI_RSRC_RDY 1 316#define lpfc_ftr_ashdr_SHIFT 4 317#define lpfc_ftr_ashdr_MASK 0x00000001 318#define lpfc_ftr_ashdr_WORD word0 319}; 320 321struct sli4_bls_rsp { 322 uint32_t word0_rsvd; /* Word0 must be reserved */ 323 uint32_t word1; 324#define lpfc_abts_orig_SHIFT 0 325#define lpfc_abts_orig_MASK 0x00000001 326#define lpfc_abts_orig_WORD word1 327#define LPFC_ABTS_UNSOL_RSP 1 328#define LPFC_ABTS_UNSOL_INT 0 329 uint32_t word2; 330#define lpfc_abts_rxid_SHIFT 0 331#define lpfc_abts_rxid_MASK 0x0000FFFF 332#define lpfc_abts_rxid_WORD word2 333#define lpfc_abts_oxid_SHIFT 16 334#define lpfc_abts_oxid_MASK 0x0000FFFF 335#define lpfc_abts_oxid_WORD word2 336 uint32_t word3; 337#define lpfc_vndr_code_SHIFT 0 338#define lpfc_vndr_code_MASK 0x000000FF 339#define lpfc_vndr_code_WORD word3 340#define lpfc_rsn_expln_SHIFT 8 341#define lpfc_rsn_expln_MASK 0x000000FF 342#define lpfc_rsn_expln_WORD word3 343#define lpfc_rsn_code_SHIFT 16 344#define lpfc_rsn_code_MASK 0x000000FF 345#define lpfc_rsn_code_WORD word3 346 347 uint32_t word4; 348 uint32_t word5_rsvd; /* Word5 must be reserved */ 349}; 350 351/* event queue entry structure */ 352struct lpfc_eqe { 353 uint32_t word0; 354#define lpfc_eqe_resource_id_SHIFT 16 355#define lpfc_eqe_resource_id_MASK 0x0000FFFF 356#define lpfc_eqe_resource_id_WORD word0 357#define lpfc_eqe_minor_code_SHIFT 4 358#define lpfc_eqe_minor_code_MASK 0x00000FFF 359#define lpfc_eqe_minor_code_WORD word0 360#define lpfc_eqe_major_code_SHIFT 1 361#define lpfc_eqe_major_code_MASK 0x00000007 362#define lpfc_eqe_major_code_WORD word0 363#define lpfc_eqe_valid_SHIFT 0 364#define lpfc_eqe_valid_MASK 0x00000001 365#define lpfc_eqe_valid_WORD word0 366}; 367 368/* completion queue entry structure (common fields for all cqe types) */ 369struct lpfc_cqe { 370 uint32_t reserved0; 371 uint32_t reserved1; 372 uint32_t reserved2; 373 uint32_t word3; 374#define lpfc_cqe_valid_SHIFT 31 375#define lpfc_cqe_valid_MASK 0x00000001 376#define lpfc_cqe_valid_WORD word3 377#define lpfc_cqe_code_SHIFT 16 378#define lpfc_cqe_code_MASK 0x000000FF 379#define lpfc_cqe_code_WORD word3 380}; 381 382/* Completion Queue Entry Status Codes */ 383#define CQE_STATUS_SUCCESS 0x0 384#define CQE_STATUS_FCP_RSP_FAILURE 0x1 385#define CQE_STATUS_REMOTE_STOP 0x2 386#define CQE_STATUS_LOCAL_REJECT 0x3 387#define CQE_STATUS_NPORT_RJT 0x4 388#define CQE_STATUS_FABRIC_RJT 0x5 389#define CQE_STATUS_NPORT_BSY 0x6 390#define CQE_STATUS_FABRIC_BSY 0x7 391#define CQE_STATUS_INTERMED_RSP 0x8 392#define CQE_STATUS_LS_RJT 0x9 393#define CQE_STATUS_CMD_REJECT 0xb 394#define CQE_STATUS_FCP_TGT_LENCHECK 0xc 395#define CQE_STATUS_NEED_BUFF_ENTRY 0xf 396#define CQE_STATUS_DI_ERROR 0x16 397 398/* Used when mapping CQE status to IOCB */ 399#define LPFC_IOCB_STATUS_MASK 0xf 400 401/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 402#define CQE_HW_STATUS_NO_ERR 0x0 403#define CQE_HW_STATUS_UNDERRUN 0x1 404#define CQE_HW_STATUS_OVERRUN 0x2 405 406/* Completion Queue Entry Codes */ 407#define CQE_CODE_COMPL_WQE 0x1 408#define CQE_CODE_RELEASE_WQE 0x2 409#define CQE_CODE_RECEIVE 0x4 410#define CQE_CODE_XRI_ABORTED 0x5 411#define CQE_CODE_RECEIVE_V1 0x9 412#define CQE_CODE_NVME_ERSP 0xd 413 414/* 415 * Define mask value for xri_aborted and wcqe completed CQE extended status. 416 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 417 */ 418#define WCQE_PARAM_MASK 0x1FF 419 420/* completion queue entry for wqe completions */ 421struct lpfc_wcqe_complete { 422 uint32_t word0; 423#define lpfc_wcqe_c_request_tag_SHIFT 16 424#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 425#define lpfc_wcqe_c_request_tag_WORD word0 426#define lpfc_wcqe_c_status_SHIFT 8 427#define lpfc_wcqe_c_status_MASK 0x000000FF 428#define lpfc_wcqe_c_status_WORD word0 429#define lpfc_wcqe_c_hw_status_SHIFT 0 430#define lpfc_wcqe_c_hw_status_MASK 0x000000FF 431#define lpfc_wcqe_c_hw_status_WORD word0 432#define lpfc_wcqe_c_ersp0_SHIFT 0 433#define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 434#define lpfc_wcqe_c_ersp0_WORD word0 435 uint32_t total_data_placed; 436#define lpfc_wcqe_c_cmf_cg_SHIFT 31 437#define lpfc_wcqe_c_cmf_cg_MASK 0x00000001 438#define lpfc_wcqe_c_cmf_cg_WORD total_data_placed 439#define lpfc_wcqe_c_cmf_bw_SHIFT 0 440#define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF 441#define lpfc_wcqe_c_cmf_bw_WORD total_data_placed 442 uint32_t parameter; 443#define lpfc_wcqe_c_bg_edir_SHIFT 5 444#define lpfc_wcqe_c_bg_edir_MASK 0x00000001 445#define lpfc_wcqe_c_bg_edir_WORD parameter 446#define lpfc_wcqe_c_bg_tdpv_SHIFT 3 447#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 448#define lpfc_wcqe_c_bg_tdpv_WORD parameter 449#define lpfc_wcqe_c_bg_re_SHIFT 2 450#define lpfc_wcqe_c_bg_re_MASK 0x00000001 451#define lpfc_wcqe_c_bg_re_WORD parameter 452#define lpfc_wcqe_c_bg_ae_SHIFT 1 453#define lpfc_wcqe_c_bg_ae_MASK 0x00000001 454#define lpfc_wcqe_c_bg_ae_WORD parameter 455#define lpfc_wcqe_c_bg_ge_SHIFT 0 456#define lpfc_wcqe_c_bg_ge_MASK 0x00000001 457#define lpfc_wcqe_c_bg_ge_WORD parameter 458 uint32_t word3; 459#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 460#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 461#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 462#define lpfc_wcqe_c_xb_SHIFT 28 463#define lpfc_wcqe_c_xb_MASK 0x00000001 464#define lpfc_wcqe_c_xb_WORD word3 465#define lpfc_wcqe_c_pv_SHIFT 27 466#define lpfc_wcqe_c_pv_MASK 0x00000001 467#define lpfc_wcqe_c_pv_WORD word3 468#define lpfc_wcqe_c_priority_SHIFT 24 469#define lpfc_wcqe_c_priority_MASK 0x00000007 470#define lpfc_wcqe_c_priority_WORD word3 471#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 472#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 473#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 474#define lpfc_wcqe_c_sqhead_SHIFT 0 475#define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 476#define lpfc_wcqe_c_sqhead_WORD word3 477}; 478 479/* completion queue entry for wqe release */ 480struct lpfc_wcqe_release { 481 uint32_t reserved0; 482 uint32_t reserved1; 483 uint32_t word2; 484#define lpfc_wcqe_r_wq_id_SHIFT 16 485#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 486#define lpfc_wcqe_r_wq_id_WORD word2 487#define lpfc_wcqe_r_wqe_index_SHIFT 0 488#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 489#define lpfc_wcqe_r_wqe_index_WORD word2 490 uint32_t word3; 491#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 492#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 493#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 494#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 495#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 496#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 497}; 498 499struct sli4_wcqe_xri_aborted { 500 uint32_t word0; 501#define lpfc_wcqe_xa_status_SHIFT 8 502#define lpfc_wcqe_xa_status_MASK 0x000000FF 503#define lpfc_wcqe_xa_status_WORD word0 504 uint32_t parameter; 505 uint32_t word2; 506#define lpfc_wcqe_xa_remote_xid_SHIFT 16 507#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 508#define lpfc_wcqe_xa_remote_xid_WORD word2 509#define lpfc_wcqe_xa_xri_SHIFT 0 510#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 511#define lpfc_wcqe_xa_xri_WORD word2 512 uint32_t word3; 513#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 514#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 515#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 516#define lpfc_wcqe_xa_ia_SHIFT 30 517#define lpfc_wcqe_xa_ia_MASK 0x00000001 518#define lpfc_wcqe_xa_ia_WORD word3 519#define CQE_XRI_ABORTED_IA_REMOTE 0 520#define CQE_XRI_ABORTED_IA_LOCAL 1 521#define lpfc_wcqe_xa_br_SHIFT 29 522#define lpfc_wcqe_xa_br_MASK 0x00000001 523#define lpfc_wcqe_xa_br_WORD word3 524#define CQE_XRI_ABORTED_BR_BA_ACC 0 525#define CQE_XRI_ABORTED_BR_BA_RJT 1 526#define lpfc_wcqe_xa_eo_SHIFT 28 527#define lpfc_wcqe_xa_eo_MASK 0x00000001 528#define lpfc_wcqe_xa_eo_WORD word3 529#define CQE_XRI_ABORTED_EO_REMOTE 0 530#define CQE_XRI_ABORTED_EO_LOCAL 1 531#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 532#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 533#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 534}; 535 536/* completion queue entry structure for rqe completion */ 537struct lpfc_rcqe { 538 uint32_t word0; 539#define lpfc_rcqe_bindex_SHIFT 16 540#define lpfc_rcqe_bindex_MASK 0x0000FFF 541#define lpfc_rcqe_bindex_WORD word0 542#define lpfc_rcqe_status_SHIFT 8 543#define lpfc_rcqe_status_MASK 0x000000FF 544#define lpfc_rcqe_status_WORD word0 545#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 546#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 547#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 548#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 549 uint32_t word1; 550#define lpfc_rcqe_fcf_id_v1_SHIFT 0 551#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 552#define lpfc_rcqe_fcf_id_v1_WORD word1 553 uint32_t word2; 554#define lpfc_rcqe_length_SHIFT 16 555#define lpfc_rcqe_length_MASK 0x0000FFFF 556#define lpfc_rcqe_length_WORD word2 557#define lpfc_rcqe_rq_id_SHIFT 6 558#define lpfc_rcqe_rq_id_MASK 0x000003FF 559#define lpfc_rcqe_rq_id_WORD word2 560#define lpfc_rcqe_fcf_id_SHIFT 0 561#define lpfc_rcqe_fcf_id_MASK 0x0000003F 562#define lpfc_rcqe_fcf_id_WORD word2 563#define lpfc_rcqe_rq_id_v1_SHIFT 0 564#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 565#define lpfc_rcqe_rq_id_v1_WORD word2 566 uint32_t word3; 567#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 568#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 569#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 570#define lpfc_rcqe_port_SHIFT 30 571#define lpfc_rcqe_port_MASK 0x00000001 572#define lpfc_rcqe_port_WORD word3 573#define lpfc_rcqe_hdr_length_SHIFT 24 574#define lpfc_rcqe_hdr_length_MASK 0x0000001F 575#define lpfc_rcqe_hdr_length_WORD word3 576#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 577#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 578#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 579#define lpfc_rcqe_eof_SHIFT 8 580#define lpfc_rcqe_eof_MASK 0x000000FF 581#define lpfc_rcqe_eof_WORD word3 582#define FCOE_EOFn 0x41 583#define FCOE_EOFt 0x42 584#define FCOE_EOFni 0x49 585#define FCOE_EOFa 0x50 586#define lpfc_rcqe_sof_SHIFT 0 587#define lpfc_rcqe_sof_MASK 0x000000FF 588#define lpfc_rcqe_sof_WORD word3 589#define FCOE_SOFi2 0x2d 590#define FCOE_SOFi3 0x2e 591#define FCOE_SOFn2 0x35 592#define FCOE_SOFn3 0x36 593}; 594 595struct lpfc_rqe { 596 uint32_t address_hi; 597 uint32_t address_lo; 598}; 599 600/* buffer descriptors */ 601struct lpfc_bde4 { 602 uint32_t addr_hi; 603 uint32_t addr_lo; 604 uint32_t word2; 605#define lpfc_bde4_last_SHIFT 31 606#define lpfc_bde4_last_MASK 0x00000001 607#define lpfc_bde4_last_WORD word2 608#define lpfc_bde4_sge_offset_SHIFT 0 609#define lpfc_bde4_sge_offset_MASK 0x000003FF 610#define lpfc_bde4_sge_offset_WORD word2 611 uint32_t word3; 612#define lpfc_bde4_length_SHIFT 0 613#define lpfc_bde4_length_MASK 0x000000FF 614#define lpfc_bde4_length_WORD word3 615}; 616 617struct lpfc_register { 618 uint32_t word0; 619}; 620 621#define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 622#define LPFC_PORT_SEM_MASK 0xF000 623/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 624#define LPFC_UERR_STATUS_HI 0x00A4 625#define LPFC_UERR_STATUS_LO 0x00A0 626#define LPFC_UE_MASK_HI 0x00AC 627#define LPFC_UE_MASK_LO 0x00A8 628 629/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 630#define LPFC_SLI_INTF 0x0058 631#define LPFC_SLI_ASIC_VER 0x009C 632 633#define LPFC_CTL_PORT_SEM_OFFSET 0x400 634#define lpfc_port_smphr_perr_SHIFT 31 635#define lpfc_port_smphr_perr_MASK 0x1 636#define lpfc_port_smphr_perr_WORD word0 637#define lpfc_port_smphr_sfi_SHIFT 30 638#define lpfc_port_smphr_sfi_MASK 0x1 639#define lpfc_port_smphr_sfi_WORD word0 640#define lpfc_port_smphr_nip_SHIFT 29 641#define lpfc_port_smphr_nip_MASK 0x1 642#define lpfc_port_smphr_nip_WORD word0 643#define lpfc_port_smphr_ipc_SHIFT 28 644#define lpfc_port_smphr_ipc_MASK 0x1 645#define lpfc_port_smphr_ipc_WORD word0 646#define lpfc_port_smphr_scr1_SHIFT 27 647#define lpfc_port_smphr_scr1_MASK 0x1 648#define lpfc_port_smphr_scr1_WORD word0 649#define lpfc_port_smphr_scr2_SHIFT 26 650#define lpfc_port_smphr_scr2_MASK 0x1 651#define lpfc_port_smphr_scr2_WORD word0 652#define lpfc_port_smphr_host_scratch_SHIFT 16 653#define lpfc_port_smphr_host_scratch_MASK 0xFF 654#define lpfc_port_smphr_host_scratch_WORD word0 655#define lpfc_port_smphr_port_status_SHIFT 0 656#define lpfc_port_smphr_port_status_MASK 0xFFFF 657#define lpfc_port_smphr_port_status_WORD word0 658 659#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 660#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 661#define LPFC_POST_STAGE_HOST_RDY 0x0002 662#define LPFC_POST_STAGE_BE_RESET 0x0003 663#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 664#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 665#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 666#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 667#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 668#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 669#define LPFC_POST_STAGE_DDR_TEST_START 0x0400 670#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 671#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 672#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 673#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 674#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 675#define LPFC_POST_STAGE_ARMFW_START 0x0800 676#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 677#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 678#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 679#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 680#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 681#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 682#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 683#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 684#define LPFC_POST_STAGE_PARSE_XML 0x0B04 685#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 686#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 687#define LPFC_POST_STAGE_RC_DONE 0x0B07 688#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 689#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 690#define LPFC_POST_STAGE_PORT_READY 0xC000 691#define LPFC_POST_STAGE_PORT_UE 0xF000 692 693#define LPFC_CTL_PORT_STA_OFFSET 0x404 694#define lpfc_sliport_status_err_SHIFT 31 695#define lpfc_sliport_status_err_MASK 0x1 696#define lpfc_sliport_status_err_WORD word0 697#define lpfc_sliport_status_end_SHIFT 30 698#define lpfc_sliport_status_end_MASK 0x1 699#define lpfc_sliport_status_end_WORD word0 700#define lpfc_sliport_status_oti_SHIFT 29 701#define lpfc_sliport_status_oti_MASK 0x1 702#define lpfc_sliport_status_oti_WORD word0 703#define lpfc_sliport_status_dip_SHIFT 25 704#define lpfc_sliport_status_dip_MASK 0x1 705#define lpfc_sliport_status_dip_WORD word0 706#define lpfc_sliport_status_rn_SHIFT 24 707#define lpfc_sliport_status_rn_MASK 0x1 708#define lpfc_sliport_status_rn_WORD word0 709#define lpfc_sliport_status_rdy_SHIFT 23 710#define lpfc_sliport_status_rdy_MASK 0x1 711#define lpfc_sliport_status_rdy_WORD word0 712#define lpfc_sliport_status_pldv_SHIFT 0 713#define lpfc_sliport_status_pldv_MASK 0x1 714#define lpfc_sliport_status_pldv_WORD word0 715#define CFG_PLD 0x3C 716#define MAX_IF_TYPE_2_RESETS 6 717 718#define LPFC_CTL_PORT_CTL_OFFSET 0x408 719#define lpfc_sliport_ctrl_end_SHIFT 30 720#define lpfc_sliport_ctrl_end_MASK 0x1 721#define lpfc_sliport_ctrl_end_WORD word0 722#define LPFC_SLIPORT_LITTLE_ENDIAN 0 723#define LPFC_SLIPORT_BIG_ENDIAN 1 724#define lpfc_sliport_ctrl_ip_SHIFT 27 725#define lpfc_sliport_ctrl_ip_MASK 0x1 726#define lpfc_sliport_ctrl_ip_WORD word0 727#define LPFC_SLIPORT_INIT_PORT 1 728 729#define LPFC_CTL_PORT_ER1_OFFSET 0x40C 730#define LPFC_CTL_PORT_ER2_OFFSET 0x410 731 732#define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 733#define lpfc_sliport_eqdelay_delay_SHIFT 16 734#define lpfc_sliport_eqdelay_delay_MASK 0xffff 735#define lpfc_sliport_eqdelay_delay_WORD word0 736#define lpfc_sliport_eqdelay_id_SHIFT 0 737#define lpfc_sliport_eqdelay_id_MASK 0xfff 738#define lpfc_sliport_eqdelay_id_WORD word0 739#define LPFC_SEC_TO_USEC 1000000 740#define LPFC_SEC_TO_MSEC 1000 741 742/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 743 * reside in BAR 2. 744 */ 745#define LPFC_SLIPORT_IF0_SMPHR 0x00AC 746 747#define LPFC_IMR_MASK_ALL 0xFFFFFFFF 748#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 749 750#define LPFC_HST_ISR0 0x0C18 751#define LPFC_HST_ISR1 0x0C1C 752#define LPFC_HST_ISR2 0x0C20 753#define LPFC_HST_ISR3 0x0C24 754#define LPFC_HST_ISR4 0x0C28 755 756#define LPFC_HST_IMR0 0x0C48 757#define LPFC_HST_IMR1 0x0C4C 758#define LPFC_HST_IMR2 0x0C50 759#define LPFC_HST_IMR3 0x0C54 760#define LPFC_HST_IMR4 0x0C58 761 762#define LPFC_HST_ISCR0 0x0C78 763#define LPFC_HST_ISCR1 0x0C7C 764#define LPFC_HST_ISCR2 0x0C80 765#define LPFC_HST_ISCR3 0x0C84 766#define LPFC_HST_ISCR4 0x0C88 767 768#define LPFC_SLI4_INTR0 BIT0 769#define LPFC_SLI4_INTR1 BIT1 770#define LPFC_SLI4_INTR2 BIT2 771#define LPFC_SLI4_INTR3 BIT3 772#define LPFC_SLI4_INTR4 BIT4 773#define LPFC_SLI4_INTR5 BIT5 774#define LPFC_SLI4_INTR6 BIT6 775#define LPFC_SLI4_INTR7 BIT7 776#define LPFC_SLI4_INTR8 BIT8 777#define LPFC_SLI4_INTR9 BIT9 778#define LPFC_SLI4_INTR10 BIT10 779#define LPFC_SLI4_INTR11 BIT11 780#define LPFC_SLI4_INTR12 BIT12 781#define LPFC_SLI4_INTR13 BIT13 782#define LPFC_SLI4_INTR14 BIT14 783#define LPFC_SLI4_INTR15 BIT15 784#define LPFC_SLI4_INTR16 BIT16 785#define LPFC_SLI4_INTR17 BIT17 786#define LPFC_SLI4_INTR18 BIT18 787#define LPFC_SLI4_INTR19 BIT19 788#define LPFC_SLI4_INTR20 BIT20 789#define LPFC_SLI4_INTR21 BIT21 790#define LPFC_SLI4_INTR22 BIT22 791#define LPFC_SLI4_INTR23 BIT23 792#define LPFC_SLI4_INTR24 BIT24 793#define LPFC_SLI4_INTR25 BIT25 794#define LPFC_SLI4_INTR26 BIT26 795#define LPFC_SLI4_INTR27 BIT27 796#define LPFC_SLI4_INTR28 BIT28 797#define LPFC_SLI4_INTR29 BIT29 798#define LPFC_SLI4_INTR30 BIT30 799#define LPFC_SLI4_INTR31 BIT31 800 801/* 802 * The Doorbell registers defined here exist in different BAR 803 * register sets depending on the UCNA Port's reported if_type 804 * value. For UCNA ports running SLI4 and if_type 0, they reside in 805 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 806 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 807 * BAR2. The offsets and base address are different, so the driver 808 * has to compute the register addresses accordingly 809 */ 810#define LPFC_ULP0_RQ_DOORBELL 0x00A0 811#define LPFC_ULP1_RQ_DOORBELL 0x00C0 812#define LPFC_IF6_RQ_DOORBELL 0x0080 813#define lpfc_rq_db_list_fm_num_posted_SHIFT 24 814#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 815#define lpfc_rq_db_list_fm_num_posted_WORD word0 816#define lpfc_rq_db_list_fm_index_SHIFT 16 817#define lpfc_rq_db_list_fm_index_MASK 0x00FF 818#define lpfc_rq_db_list_fm_index_WORD word0 819#define lpfc_rq_db_list_fm_id_SHIFT 0 820#define lpfc_rq_db_list_fm_id_MASK 0xFFFF 821#define lpfc_rq_db_list_fm_id_WORD word0 822#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 823#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 824#define lpfc_rq_db_ring_fm_num_posted_WORD word0 825#define lpfc_rq_db_ring_fm_id_SHIFT 0 826#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 827#define lpfc_rq_db_ring_fm_id_WORD word0 828 829#define LPFC_ULP0_WQ_DOORBELL 0x0040 830#define LPFC_ULP1_WQ_DOORBELL 0x0060 831#define lpfc_wq_db_list_fm_num_posted_SHIFT 24 832#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 833#define lpfc_wq_db_list_fm_num_posted_WORD word0 834#define lpfc_wq_db_list_fm_index_SHIFT 16 835#define lpfc_wq_db_list_fm_index_MASK 0x00FF 836#define lpfc_wq_db_list_fm_index_WORD word0 837#define lpfc_wq_db_list_fm_id_SHIFT 0 838#define lpfc_wq_db_list_fm_id_MASK 0xFFFF 839#define lpfc_wq_db_list_fm_id_WORD word0 840#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 841#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 842#define lpfc_wq_db_ring_fm_num_posted_WORD word0 843#define lpfc_wq_db_ring_fm_id_SHIFT 0 844#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 845#define lpfc_wq_db_ring_fm_id_WORD word0 846 847#define LPFC_IF6_WQ_DOORBELL 0x0040 848#define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 849#define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 850#define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 851#define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 852#define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 853#define lpfc_if6_wq_db_list_fm_dpp_WORD word0 854#define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 855#define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 856#define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 857#define lpfc_if6_wq_db_list_fm_id_SHIFT 0 858#define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 859#define lpfc_if6_wq_db_list_fm_id_WORD word0 860 861#define LPFC_EQCQ_DOORBELL 0x0120 862#define lpfc_eqcq_doorbell_se_SHIFT 31 863#define lpfc_eqcq_doorbell_se_MASK 0x0001 864#define lpfc_eqcq_doorbell_se_WORD word0 865#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 866#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 867#define lpfc_eqcq_doorbell_arm_SHIFT 29 868#define lpfc_eqcq_doorbell_arm_MASK 0x0001 869#define lpfc_eqcq_doorbell_arm_WORD word0 870#define lpfc_eqcq_doorbell_num_released_SHIFT 16 871#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 872#define lpfc_eqcq_doorbell_num_released_WORD word0 873#define lpfc_eqcq_doorbell_qt_SHIFT 10 874#define lpfc_eqcq_doorbell_qt_MASK 0x0001 875#define lpfc_eqcq_doorbell_qt_WORD word0 876#define LPFC_QUEUE_TYPE_COMPLETION 0 877#define LPFC_QUEUE_TYPE_EVENT 1 878#define lpfc_eqcq_doorbell_eqci_SHIFT 9 879#define lpfc_eqcq_doorbell_eqci_MASK 0x0001 880#define lpfc_eqcq_doorbell_eqci_WORD word0 881#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 882#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 883#define lpfc_eqcq_doorbell_cqid_lo_WORD word0 884#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 885#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 886#define lpfc_eqcq_doorbell_cqid_hi_WORD word0 887#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 888#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 889#define lpfc_eqcq_doorbell_eqid_lo_WORD word0 890#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 891#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 892#define lpfc_eqcq_doorbell_eqid_hi_WORD word0 893#define LPFC_CQID_HI_FIELD_SHIFT 10 894#define LPFC_EQID_HI_FIELD_SHIFT 9 895 896#define LPFC_IF6_CQ_DOORBELL 0x00C0 897#define lpfc_if6_cq_doorbell_se_SHIFT 31 898#define lpfc_if6_cq_doorbell_se_MASK 0x0001 899#define lpfc_if6_cq_doorbell_se_WORD word0 900#define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 901#define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 902#define lpfc_if6_cq_doorbell_arm_SHIFT 29 903#define lpfc_if6_cq_doorbell_arm_MASK 0x0001 904#define lpfc_if6_cq_doorbell_arm_WORD word0 905#define lpfc_if6_cq_doorbell_num_released_SHIFT 16 906#define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 907#define lpfc_if6_cq_doorbell_num_released_WORD word0 908#define lpfc_if6_cq_doorbell_cqid_SHIFT 0 909#define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 910#define lpfc_if6_cq_doorbell_cqid_WORD word0 911 912#define LPFC_IF6_EQ_DOORBELL 0x0120 913#define lpfc_if6_eq_doorbell_io_SHIFT 31 914#define lpfc_if6_eq_doorbell_io_MASK 0x0001 915#define lpfc_if6_eq_doorbell_io_WORD word0 916#define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 917#define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 918#define lpfc_if6_eq_doorbell_arm_SHIFT 29 919#define lpfc_if6_eq_doorbell_arm_MASK 0x0001 920#define lpfc_if6_eq_doorbell_arm_WORD word0 921#define lpfc_if6_eq_doorbell_num_released_SHIFT 16 922#define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 923#define lpfc_if6_eq_doorbell_num_released_WORD word0 924#define lpfc_if6_eq_doorbell_eqid_SHIFT 0 925#define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 926#define lpfc_if6_eq_doorbell_eqid_WORD word0 927 928#define LPFC_BMBX 0x0160 929#define lpfc_bmbx_addr_SHIFT 2 930#define lpfc_bmbx_addr_MASK 0x3FFFFFFF 931#define lpfc_bmbx_addr_WORD word0 932#define lpfc_bmbx_hi_SHIFT 1 933#define lpfc_bmbx_hi_MASK 0x0001 934#define lpfc_bmbx_hi_WORD word0 935#define lpfc_bmbx_rdy_SHIFT 0 936#define lpfc_bmbx_rdy_MASK 0x0001 937#define lpfc_bmbx_rdy_WORD word0 938 939#define LPFC_MQ_DOORBELL 0x0140 940#define LPFC_IF6_MQ_DOORBELL 0x0160 941#define lpfc_mq_doorbell_num_posted_SHIFT 16 942#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 943#define lpfc_mq_doorbell_num_posted_WORD word0 944#define lpfc_mq_doorbell_id_SHIFT 0 945#define lpfc_mq_doorbell_id_MASK 0xFFFF 946#define lpfc_mq_doorbell_id_WORD word0 947 948struct lpfc_sli4_cfg_mhdr { 949 uint32_t word1; 950#define lpfc_mbox_hdr_emb_SHIFT 0 951#define lpfc_mbox_hdr_emb_MASK 0x00000001 952#define lpfc_mbox_hdr_emb_WORD word1 953#define lpfc_mbox_hdr_sge_cnt_SHIFT 3 954#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 955#define lpfc_mbox_hdr_sge_cnt_WORD word1 956 uint32_t payload_length; 957 uint32_t tag_lo; 958 uint32_t tag_hi; 959 uint32_t reserved5; 960}; 961 962union lpfc_sli4_cfg_shdr { 963 struct { 964 uint32_t word6; 965#define lpfc_mbox_hdr_opcode_SHIFT 0 966#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 967#define lpfc_mbox_hdr_opcode_WORD word6 968#define lpfc_mbox_hdr_subsystem_SHIFT 8 969#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 970#define lpfc_mbox_hdr_subsystem_WORD word6 971#define lpfc_mbox_hdr_port_number_SHIFT 16 972#define lpfc_mbox_hdr_port_number_MASK 0x000000FF 973#define lpfc_mbox_hdr_port_number_WORD word6 974#define lpfc_mbox_hdr_domain_SHIFT 24 975#define lpfc_mbox_hdr_domain_MASK 0x000000FF 976#define lpfc_mbox_hdr_domain_WORD word6 977 uint32_t timeout; 978 uint32_t request_length; 979 uint32_t word9; 980#define lpfc_mbox_hdr_version_SHIFT 0 981#define lpfc_mbox_hdr_version_MASK 0x000000FF 982#define lpfc_mbox_hdr_version_WORD word9 983#define lpfc_mbox_hdr_pf_num_SHIFT 16 984#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 985#define lpfc_mbox_hdr_pf_num_WORD word9 986#define lpfc_mbox_hdr_vh_num_SHIFT 24 987#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 988#define lpfc_mbox_hdr_vh_num_WORD word9 989#define LPFC_Q_CREATE_VERSION_2 2 990#define LPFC_Q_CREATE_VERSION_1 1 991#define LPFC_Q_CREATE_VERSION_0 0 992#define LPFC_OPCODE_VERSION_0 0 993#define LPFC_OPCODE_VERSION_1 1 994 } request; 995 struct { 996 uint32_t word6; 997#define lpfc_mbox_hdr_opcode_SHIFT 0 998#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 999#define lpfc_mbox_hdr_opcode_WORD word6 1000#define lpfc_mbox_hdr_subsystem_SHIFT 8 1001#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 1002#define lpfc_mbox_hdr_subsystem_WORD word6 1003#define lpfc_mbox_hdr_domain_SHIFT 24 1004#define lpfc_mbox_hdr_domain_MASK 0x000000FF 1005#define lpfc_mbox_hdr_domain_WORD word6 1006 uint32_t word7; 1007#define lpfc_mbox_hdr_status_SHIFT 0 1008#define lpfc_mbox_hdr_status_MASK 0x000000FF 1009#define lpfc_mbox_hdr_status_WORD word7 1010#define lpfc_mbox_hdr_add_status_SHIFT 8 1011#define lpfc_mbox_hdr_add_status_MASK 0x000000FF 1012#define lpfc_mbox_hdr_add_status_WORD word7 1013#define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 1014#define lpfc_mbox_hdr_add_status_2_SHIFT 16 1015#define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 1016#define lpfc_mbox_hdr_add_status_2_WORD word7 1017#define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 1018#define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 1019 uint32_t response_length; 1020 uint32_t actual_response_length; 1021 } response; 1022}; 1023 1024/* Mailbox Header structures. 1025 * struct mbox_header is defined for first generation SLI4_CFG mailbox 1026 * calls deployed for BE-based ports. 1027 * 1028 * struct sli4_mbox_header is defined for second generation SLI4 1029 * ports that don't deploy the SLI4_CFG mechanism. 1030 */ 1031struct mbox_header { 1032 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1033 union lpfc_sli4_cfg_shdr cfg_shdr; 1034}; 1035 1036#define LPFC_EXTENT_LOCAL 0 1037#define LPFC_TIMEOUT_DEFAULT 0 1038#define LPFC_EXTENT_VERSION_DEFAULT 0 1039 1040/* Subsystem Definitions */ 1041#define LPFC_MBOX_SUBSYSTEM_NA 0x0 1042#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 1043#define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 1044#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 1045 1046/* Device Specific Definitions */ 1047 1048/* The HOST ENDIAN defines are in Big Endian format. */ 1049#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1050#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1051 1052/* Common Opcodes */ 1053#define LPFC_MBOX_OPCODE_NA 0x00 1054#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1055#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1056#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1057#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1058#define LPFC_MBOX_OPCODE_NOP 0x21 1059#define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1060#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1061#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1062#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1063#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1064#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1065#define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1066#define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1067#define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1068#define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1069#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1070#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1071#define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1072#define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1073#define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1074#define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1075#define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E 1076#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1077#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1078#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1079#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1080#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1081#define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1082#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1083#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1084#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1085#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1086#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1087#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1088#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1089#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1090#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1091#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1092#define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1093 1094/* FCoE Opcodes */ 1095#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1096#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1097#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1098#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1099#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1100#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1101#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1102#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1103#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1104#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1105#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1106#define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1107#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1108#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1109#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1110#define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1111 1112/* Low level Opcodes */ 1113#define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1114 1115/* Mailbox command structures */ 1116struct eq_context { 1117 uint32_t word0; 1118#define lpfc_eq_context_size_SHIFT 31 1119#define lpfc_eq_context_size_MASK 0x00000001 1120#define lpfc_eq_context_size_WORD word0 1121#define LPFC_EQE_SIZE_4 0x0 1122#define LPFC_EQE_SIZE_16 0x1 1123#define lpfc_eq_context_valid_SHIFT 29 1124#define lpfc_eq_context_valid_MASK 0x00000001 1125#define lpfc_eq_context_valid_WORD word0 1126#define lpfc_eq_context_autovalid_SHIFT 28 1127#define lpfc_eq_context_autovalid_MASK 0x00000001 1128#define lpfc_eq_context_autovalid_WORD word0 1129 uint32_t word1; 1130#define lpfc_eq_context_count_SHIFT 26 1131#define lpfc_eq_context_count_MASK 0x00000003 1132#define lpfc_eq_context_count_WORD word1 1133#define LPFC_EQ_CNT_256 0x0 1134#define LPFC_EQ_CNT_512 0x1 1135#define LPFC_EQ_CNT_1024 0x2 1136#define LPFC_EQ_CNT_2048 0x3 1137#define LPFC_EQ_CNT_4096 0x4 1138 uint32_t word2; 1139#define lpfc_eq_context_delay_multi_SHIFT 13 1140#define lpfc_eq_context_delay_multi_MASK 0x000003FF 1141#define lpfc_eq_context_delay_multi_WORD word2 1142 uint32_t reserved3; 1143}; 1144 1145struct eq_delay_info { 1146 uint32_t eq_id; 1147 uint32_t phase; 1148 uint32_t delay_multi; 1149}; 1150#define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1151 1152struct sgl_page_pairs { 1153 uint32_t sgl_pg0_addr_lo; 1154 uint32_t sgl_pg0_addr_hi; 1155 uint32_t sgl_pg1_addr_lo; 1156 uint32_t sgl_pg1_addr_hi; 1157}; 1158 1159struct lpfc_mbx_post_sgl_pages { 1160 struct mbox_header header; 1161 uint32_t word0; 1162#define lpfc_post_sgl_pages_xri_SHIFT 0 1163#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1164#define lpfc_post_sgl_pages_xri_WORD word0 1165#define lpfc_post_sgl_pages_xricnt_SHIFT 16 1166#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1167#define lpfc_post_sgl_pages_xricnt_WORD word0 1168 struct sgl_page_pairs sgl_pg_pairs[1]; 1169}; 1170 1171/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1172struct lpfc_mbx_post_uembed_sgl_page1 { 1173 union lpfc_sli4_cfg_shdr cfg_shdr; 1174 uint32_t word0; 1175 struct sgl_page_pairs sgl_pg_pairs; 1176}; 1177 1178struct lpfc_mbx_sge { 1179 uint32_t pa_lo; 1180 uint32_t pa_hi; 1181 uint32_t length; 1182}; 1183 1184struct lpfc_mbx_host_buf { 1185 uint32_t length; 1186 uint32_t pa_lo; 1187 uint32_t pa_hi; 1188}; 1189 1190struct lpfc_mbx_nembed_cmd { 1191 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1192#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1193 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1194}; 1195 1196struct lpfc_mbx_nembed_sge_virt { 1197 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1198}; 1199 1200#define LPFC_MBX_OBJECT_NAME_LEN_DW 26 1201struct lpfc_mbx_read_object { /* Version 0 */ 1202 struct mbox_header header; 1203 union { 1204 struct { 1205 uint32_t word0; 1206#define lpfc_mbx_rd_object_rlen_SHIFT 0 1207#define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF 1208#define lpfc_mbx_rd_object_rlen_WORD word0 1209 uint32_t rd_object_offset; 1210 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 1211#define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */ 1212 uint32_t rd_object_cnt; 1213 struct lpfc_mbx_host_buf rd_object_hbuf[4]; 1214 } request; 1215 struct { 1216 uint32_t rd_object_actual_rlen; 1217 uint32_t word1; 1218#define lpfc_mbx_rd_object_eof_SHIFT 31 1219#define lpfc_mbx_rd_object_eof_MASK 0x1 1220#define lpfc_mbx_rd_object_eof_WORD word1 1221 } response; 1222 } u; 1223}; 1224 1225struct lpfc_mbx_eq_create { 1226 struct mbox_header header; 1227 union { 1228 struct { 1229 uint32_t word0; 1230#define lpfc_mbx_eq_create_num_pages_SHIFT 0 1231#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1232#define lpfc_mbx_eq_create_num_pages_WORD word0 1233 struct eq_context context; 1234 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1235 } request; 1236 struct { 1237 uint32_t word0; 1238#define lpfc_mbx_eq_create_q_id_SHIFT 0 1239#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1240#define lpfc_mbx_eq_create_q_id_WORD word0 1241 } response; 1242 } u; 1243}; 1244 1245struct lpfc_mbx_modify_eq_delay { 1246 struct mbox_header header; 1247 union { 1248 struct { 1249 uint32_t num_eq; 1250 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1251 } request; 1252 struct { 1253 uint32_t word0; 1254 } response; 1255 } u; 1256}; 1257 1258struct lpfc_mbx_eq_destroy { 1259 struct mbox_header header; 1260 union { 1261 struct { 1262 uint32_t word0; 1263#define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1264#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1265#define lpfc_mbx_eq_destroy_q_id_WORD word0 1266 } request; 1267 struct { 1268 uint32_t word0; 1269 } response; 1270 } u; 1271}; 1272 1273struct lpfc_mbx_nop { 1274 struct mbox_header header; 1275 uint32_t context[2]; 1276}; 1277 1278 1279 1280struct lpfc_mbx_set_ras_fwlog { 1281 struct mbox_header header; 1282 union { 1283 struct { 1284 uint32_t word4; 1285#define lpfc_fwlog_enable_SHIFT 0 1286#define lpfc_fwlog_enable_MASK 0x00000001 1287#define lpfc_fwlog_enable_WORD word4 1288#define lpfc_fwlog_loglvl_SHIFT 8 1289#define lpfc_fwlog_loglvl_MASK 0x0000000F 1290#define lpfc_fwlog_loglvl_WORD word4 1291#define lpfc_fwlog_ra_SHIFT 15 1292#define lpfc_fwlog_ra_WORD 0x00000008 1293#define lpfc_fwlog_buffcnt_SHIFT 16 1294#define lpfc_fwlog_buffcnt_MASK 0x000000FF 1295#define lpfc_fwlog_buffcnt_WORD word4 1296#define lpfc_fwlog_buffsz_SHIFT 24 1297#define lpfc_fwlog_buffsz_MASK 0x000000FF 1298#define lpfc_fwlog_buffsz_WORD word4 1299 uint32_t word5; 1300#define lpfc_fwlog_acqe_SHIFT 0 1301#define lpfc_fwlog_acqe_MASK 0x0000FFFF 1302#define lpfc_fwlog_acqe_WORD word5 1303#define lpfc_fwlog_cqid_SHIFT 16 1304#define lpfc_fwlog_cqid_MASK 0x0000FFFF 1305#define lpfc_fwlog_cqid_WORD word5 1306#define LPFC_MAX_FWLOG_PAGE 16 1307 struct dma_address lwpd; 1308 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1309 } request; 1310 struct { 1311 uint32_t word0; 1312 } response; 1313 } u; 1314}; 1315 1316 1317struct cq_context { 1318 uint32_t word0; 1319#define lpfc_cq_context_event_SHIFT 31 1320#define lpfc_cq_context_event_MASK 0x00000001 1321#define lpfc_cq_context_event_WORD word0 1322#define lpfc_cq_context_valid_SHIFT 29 1323#define lpfc_cq_context_valid_MASK 0x00000001 1324#define lpfc_cq_context_valid_WORD word0 1325#define lpfc_cq_context_count_SHIFT 27 1326#define lpfc_cq_context_count_MASK 0x00000003 1327#define lpfc_cq_context_count_WORD word0 1328#define LPFC_CQ_CNT_256 0x0 1329#define LPFC_CQ_CNT_512 0x1 1330#define LPFC_CQ_CNT_1024 0x2 1331#define LPFC_CQ_CNT_WORD7 0x3 1332#define lpfc_cq_context_autovalid_SHIFT 15 1333#define lpfc_cq_context_autovalid_MASK 0x00000001 1334#define lpfc_cq_context_autovalid_WORD word0 1335 uint32_t word1; 1336#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1337#define lpfc_cq_eq_id_MASK 0x000000FF 1338#define lpfc_cq_eq_id_WORD word1 1339#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1340#define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1341#define lpfc_cq_eq_id_2_WORD word1 1342 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1343 uint32_t reserved1; 1344}; 1345 1346struct lpfc_mbx_cq_create { 1347 struct mbox_header header; 1348 union { 1349 struct { 1350 uint32_t word0; 1351#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1352#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1353#define lpfc_mbx_cq_create_page_size_WORD word0 1354#define lpfc_mbx_cq_create_num_pages_SHIFT 0 1355#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1356#define lpfc_mbx_cq_create_num_pages_WORD word0 1357 struct cq_context context; 1358 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1359 } request; 1360 struct { 1361 uint32_t word0; 1362#define lpfc_mbx_cq_create_q_id_SHIFT 0 1363#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1364#define lpfc_mbx_cq_create_q_id_WORD word0 1365 } response; 1366 } u; 1367}; 1368 1369struct lpfc_mbx_cq_create_set { 1370 union lpfc_sli4_cfg_shdr cfg_shdr; 1371 union { 1372 struct { 1373 uint32_t word0; 1374#define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1375#define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1376#define lpfc_mbx_cq_create_set_page_size_WORD word0 1377#define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1378#define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1379#define lpfc_mbx_cq_create_set_num_pages_WORD word0 1380 uint32_t word1; 1381#define lpfc_mbx_cq_create_set_evt_SHIFT 31 1382#define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1383#define lpfc_mbx_cq_create_set_evt_WORD word1 1384#define lpfc_mbx_cq_create_set_valid_SHIFT 29 1385#define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1386#define lpfc_mbx_cq_create_set_valid_WORD word1 1387#define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1388#define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1389#define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1390#define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1391#define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1392#define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1393#define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1394#define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1395#define lpfc_mbx_cq_create_set_autovalid_WORD word1 1396#define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1397#define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1398#define lpfc_mbx_cq_create_set_nodelay_WORD word1 1399#define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1400#define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1401#define lpfc_mbx_cq_create_set_clswm_WORD word1 1402 uint32_t word2; 1403#define lpfc_mbx_cq_create_set_arm_SHIFT 31 1404#define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1405#define lpfc_mbx_cq_create_set_arm_WORD word2 1406#define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1407#define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1408#define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1409#define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1410#define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1411#define lpfc_mbx_cq_create_set_num_cq_WORD word2 1412 uint32_t word3; 1413#define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1414#define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1415#define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1416#define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1417#define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1418#define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1419 uint32_t word4; 1420#define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1421#define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1422#define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1423#define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1424#define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1425#define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1426 uint32_t word5; 1427#define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1428#define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1429#define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1430#define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1431#define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1432#define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1433 uint32_t word6; 1434#define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1435#define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1436#define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1437#define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1438#define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1439#define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1440 uint32_t word7; 1441#define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1442#define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1443#define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1444#define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1445#define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1446#define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1447 uint32_t word8; 1448#define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1449#define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1450#define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1451#define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1452#define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1453#define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1454 uint32_t word9; 1455#define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1456#define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1457#define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1458#define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1459#define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1460#define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1461 uint32_t word10; 1462#define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1463#define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1464#define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1465#define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1466#define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1467#define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1468 struct dma_address page[1]; 1469 } request; 1470 struct { 1471 uint32_t word0; 1472#define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1473#define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1474#define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1475#define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1476#define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1477#define lpfc_mbx_cq_create_set_base_id_WORD word0 1478 } response; 1479 } u; 1480}; 1481 1482struct lpfc_mbx_cq_destroy { 1483 struct mbox_header header; 1484 union { 1485 struct { 1486 uint32_t word0; 1487#define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1488#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1489#define lpfc_mbx_cq_destroy_q_id_WORD word0 1490 } request; 1491 struct { 1492 uint32_t word0; 1493 } response; 1494 } u; 1495}; 1496 1497struct wq_context { 1498 uint32_t reserved0; 1499 uint32_t reserved1; 1500 uint32_t reserved2; 1501 uint32_t reserved3; 1502}; 1503 1504struct lpfc_mbx_wq_create { 1505 struct mbox_header header; 1506 union { 1507 struct { /* Version 0 Request */ 1508 uint32_t word0; 1509#define lpfc_mbx_wq_create_num_pages_SHIFT 0 1510#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1511#define lpfc_mbx_wq_create_num_pages_WORD word0 1512#define lpfc_mbx_wq_create_dua_SHIFT 8 1513#define lpfc_mbx_wq_create_dua_MASK 0x00000001 1514#define lpfc_mbx_wq_create_dua_WORD word0 1515#define lpfc_mbx_wq_create_cq_id_SHIFT 16 1516#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1517#define lpfc_mbx_wq_create_cq_id_WORD word0 1518 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1519 uint32_t word9; 1520#define lpfc_mbx_wq_create_bua_SHIFT 0 1521#define lpfc_mbx_wq_create_bua_MASK 0x00000001 1522#define lpfc_mbx_wq_create_bua_WORD word9 1523#define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1524#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1525#define lpfc_mbx_wq_create_ulp_num_WORD word9 1526 } request; 1527 struct { /* Version 1 Request */ 1528 uint32_t word0; /* Word 0 is the same as in v0 */ 1529 uint32_t word1; 1530#define lpfc_mbx_wq_create_page_size_SHIFT 0 1531#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1532#define lpfc_mbx_wq_create_page_size_WORD word1 1533#define LPFC_WQ_PAGE_SIZE_4096 0x1 1534#define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1535#define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1536#define lpfc_mbx_wq_create_dpp_req_WORD word1 1537#define lpfc_mbx_wq_create_doe_SHIFT 14 1538#define lpfc_mbx_wq_create_doe_MASK 0x00000001 1539#define lpfc_mbx_wq_create_doe_WORD word1 1540#define lpfc_mbx_wq_create_toe_SHIFT 13 1541#define lpfc_mbx_wq_create_toe_MASK 0x00000001 1542#define lpfc_mbx_wq_create_toe_WORD word1 1543#define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1544#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1545#define lpfc_mbx_wq_create_wqe_size_WORD word1 1546#define LPFC_WQ_WQE_SIZE_64 0x5 1547#define LPFC_WQ_WQE_SIZE_128 0x6 1548#define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1549#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1550#define lpfc_mbx_wq_create_wqe_count_WORD word1 1551 uint32_t word2; 1552 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1553 } request_1; 1554 struct { 1555 uint32_t word0; 1556#define lpfc_mbx_wq_create_q_id_SHIFT 0 1557#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1558#define lpfc_mbx_wq_create_q_id_WORD word0 1559 uint32_t doorbell_offset; 1560 uint32_t word2; 1561#define lpfc_mbx_wq_create_bar_set_SHIFT 0 1562#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1563#define lpfc_mbx_wq_create_bar_set_WORD word2 1564#define WQ_PCI_BAR_0_AND_1 0x00 1565#define WQ_PCI_BAR_2_AND_3 0x01 1566#define WQ_PCI_BAR_4_AND_5 0x02 1567#define lpfc_mbx_wq_create_db_format_SHIFT 16 1568#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1569#define lpfc_mbx_wq_create_db_format_WORD word2 1570 } response; 1571 struct { 1572 uint32_t word0; 1573#define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1574#define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1575#define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1576#define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1577#define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1578#define lpfc_mbx_wq_create_v1_q_id_WORD word0 1579 uint32_t word1; 1580#define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1581#define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1582#define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1583 uint32_t doorbell_offset; 1584 uint32_t word3; 1585#define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1586#define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1587#define lpfc_mbx_wq_create_dpp_id_WORD word3 1588#define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1589#define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1590#define lpfc_mbx_wq_create_dpp_bar_WORD word3 1591 uint32_t dpp_offset; 1592 } response_1; 1593 } u; 1594}; 1595 1596struct lpfc_mbx_wq_destroy { 1597 struct mbox_header header; 1598 union { 1599 struct { 1600 uint32_t word0; 1601#define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1602#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1603#define lpfc_mbx_wq_destroy_q_id_WORD word0 1604 } request; 1605 struct { 1606 uint32_t word0; 1607 } response; 1608 } u; 1609}; 1610 1611#define LPFC_HDR_BUF_SIZE 128 1612#define LPFC_DATA_BUF_SIZE 2048 1613#define LPFC_NVMET_DATA_BUF_SIZE 128 1614struct rq_context { 1615 uint32_t word0; 1616#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1617#define lpfc_rq_context_rqe_count_MASK 0x0000000F 1618#define lpfc_rq_context_rqe_count_WORD word0 1619#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1620#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1621#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1622#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1623#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1624#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1625#define lpfc_rq_context_rqe_count_1_WORD word0 1626#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1627#define lpfc_rq_context_rqe_size_MASK 0x0000000F 1628#define lpfc_rq_context_rqe_size_WORD word0 1629#define LPFC_RQE_SIZE_8 2 1630#define LPFC_RQE_SIZE_16 3 1631#define LPFC_RQE_SIZE_32 4 1632#define LPFC_RQE_SIZE_64 5 1633#define LPFC_RQE_SIZE_128 6 1634#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1635#define lpfc_rq_context_page_size_MASK 0x000000FF 1636#define lpfc_rq_context_page_size_WORD word0 1637#define LPFC_RQ_PAGE_SIZE_4096 0x1 1638 uint32_t word1; 1639#define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1640#define lpfc_rq_context_data_size_MASK 0x0000FFFF 1641#define lpfc_rq_context_data_size_WORD word1 1642#define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1643#define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1644#define lpfc_rq_context_hdr_size_WORD word1 1645 uint32_t word2; 1646#define lpfc_rq_context_cq_id_SHIFT 16 1647#define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1648#define lpfc_rq_context_cq_id_WORD word2 1649#define lpfc_rq_context_buf_size_SHIFT 0 1650#define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1651#define lpfc_rq_context_buf_size_WORD word2 1652#define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1653#define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1654#define lpfc_rq_context_base_cq_WORD word2 1655 uint32_t buffer_size; /* Version 1 Only */ 1656}; 1657 1658struct lpfc_mbx_rq_create { 1659 struct mbox_header header; 1660 union { 1661 struct { 1662 uint32_t word0; 1663#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1664#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1665#define lpfc_mbx_rq_create_num_pages_WORD word0 1666#define lpfc_mbx_rq_create_dua_SHIFT 16 1667#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1668#define lpfc_mbx_rq_create_dua_WORD word0 1669#define lpfc_mbx_rq_create_bqu_SHIFT 17 1670#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1671#define lpfc_mbx_rq_create_bqu_WORD word0 1672#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1673#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1674#define lpfc_mbx_rq_create_ulp_num_WORD word0 1675 struct rq_context context; 1676 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1677 } request; 1678 struct { 1679 uint32_t word0; 1680#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1681#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1682#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1683#define lpfc_mbx_rq_create_q_id_SHIFT 0 1684#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1685#define lpfc_mbx_rq_create_q_id_WORD word0 1686 uint32_t doorbell_offset; 1687 uint32_t word2; 1688#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1689#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1690#define lpfc_mbx_rq_create_bar_set_WORD word2 1691#define lpfc_mbx_rq_create_db_format_SHIFT 16 1692#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1693#define lpfc_mbx_rq_create_db_format_WORD word2 1694 } response; 1695 } u; 1696}; 1697 1698struct lpfc_mbx_rq_create_v2 { 1699 union lpfc_sli4_cfg_shdr cfg_shdr; 1700 union { 1701 struct { 1702 uint32_t word0; 1703#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1704#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1705#define lpfc_mbx_rq_create_num_pages_WORD word0 1706#define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1707#define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1708#define lpfc_mbx_rq_create_rq_cnt_WORD word0 1709#define lpfc_mbx_rq_create_dua_SHIFT 16 1710#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1711#define lpfc_mbx_rq_create_dua_WORD word0 1712#define lpfc_mbx_rq_create_bqu_SHIFT 17 1713#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1714#define lpfc_mbx_rq_create_bqu_WORD word0 1715#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1716#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1717#define lpfc_mbx_rq_create_ulp_num_WORD word0 1718#define lpfc_mbx_rq_create_dim_SHIFT 29 1719#define lpfc_mbx_rq_create_dim_MASK 0x00000001 1720#define lpfc_mbx_rq_create_dim_WORD word0 1721#define lpfc_mbx_rq_create_dfd_SHIFT 30 1722#define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1723#define lpfc_mbx_rq_create_dfd_WORD word0 1724#define lpfc_mbx_rq_create_dnb_SHIFT 31 1725#define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1726#define lpfc_mbx_rq_create_dnb_WORD word0 1727 struct rq_context context; 1728 struct dma_address page[1]; 1729 } request; 1730 struct { 1731 uint32_t word0; 1732#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1733#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1734#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1735#define lpfc_mbx_rq_create_q_id_SHIFT 0 1736#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1737#define lpfc_mbx_rq_create_q_id_WORD word0 1738 uint32_t doorbell_offset; 1739 uint32_t word2; 1740#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1741#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1742#define lpfc_mbx_rq_create_bar_set_WORD word2 1743#define lpfc_mbx_rq_create_db_format_SHIFT 16 1744#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1745#define lpfc_mbx_rq_create_db_format_WORD word2 1746 } response; 1747 } u; 1748}; 1749 1750struct lpfc_mbx_rq_destroy { 1751 struct mbox_header header; 1752 union { 1753 struct { 1754 uint32_t word0; 1755#define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1756#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1757#define lpfc_mbx_rq_destroy_q_id_WORD word0 1758 } request; 1759 struct { 1760 uint32_t word0; 1761 } response; 1762 } u; 1763}; 1764 1765struct mq_context { 1766 uint32_t word0; 1767#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1768#define lpfc_mq_context_cq_id_MASK 0x000003FF 1769#define lpfc_mq_context_cq_id_WORD word0 1770#define lpfc_mq_context_ring_size_SHIFT 16 1771#define lpfc_mq_context_ring_size_MASK 0x0000000F 1772#define lpfc_mq_context_ring_size_WORD word0 1773#define LPFC_MQ_RING_SIZE_16 0x5 1774#define LPFC_MQ_RING_SIZE_32 0x6 1775#define LPFC_MQ_RING_SIZE_64 0x7 1776#define LPFC_MQ_RING_SIZE_128 0x8 1777 uint32_t word1; 1778#define lpfc_mq_context_valid_SHIFT 31 1779#define lpfc_mq_context_valid_MASK 0x00000001 1780#define lpfc_mq_context_valid_WORD word1 1781 uint32_t reserved2; 1782 uint32_t reserved3; 1783}; 1784 1785struct lpfc_mbx_mq_create { 1786 struct mbox_header header; 1787 union { 1788 struct { 1789 uint32_t word0; 1790#define lpfc_mbx_mq_create_num_pages_SHIFT 0 1791#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1792#define lpfc_mbx_mq_create_num_pages_WORD word0 1793 struct mq_context context; 1794 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1795 } request; 1796 struct { 1797 uint32_t word0; 1798#define lpfc_mbx_mq_create_q_id_SHIFT 0 1799#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1800#define lpfc_mbx_mq_create_q_id_WORD word0 1801 } response; 1802 } u; 1803}; 1804 1805struct lpfc_mbx_mq_create_ext { 1806 struct mbox_header header; 1807 union { 1808 struct { 1809 uint32_t word0; 1810#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1811#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1812#define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1813#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1814#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1815#define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1816 uint32_t async_evt_bmap; 1817#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1818#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1819#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1820#define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1821#define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1822#define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1823#define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1824#define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1825#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1826#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1827#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1828#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1829#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1830#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1831#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1832#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1833#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1834#define LPFC_EVT_CODE_FC_NO_LINK 0x0 1835#define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1836#define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1837#define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1838#define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1839#define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1840#define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1841#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1842#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1843#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1844 struct mq_context context; 1845 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1846 } request; 1847 struct { 1848 uint32_t word0; 1849#define lpfc_mbx_mq_create_q_id_SHIFT 0 1850#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1851#define lpfc_mbx_mq_create_q_id_WORD word0 1852 } response; 1853 } u; 1854#define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1855#define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1856#define LPFC_ASYNC_EVENT_GROUP5 0x20 1857}; 1858 1859struct lpfc_mbx_mq_destroy { 1860 struct mbox_header header; 1861 union { 1862 struct { 1863 uint32_t word0; 1864#define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1865#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1866#define lpfc_mbx_mq_destroy_q_id_WORD word0 1867 } request; 1868 struct { 1869 uint32_t word0; 1870 } response; 1871 } u; 1872}; 1873 1874/* Start Gen 2 SLI4 Mailbox definitions: */ 1875 1876/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1877#define LPFC_RSC_TYPE_FCOE_VFI 0x20 1878#define LPFC_RSC_TYPE_FCOE_VPI 0x21 1879#define LPFC_RSC_TYPE_FCOE_RPI 0x22 1880#define LPFC_RSC_TYPE_FCOE_XRI 0x23 1881 1882struct lpfc_mbx_get_rsrc_extent_info { 1883 struct mbox_header header; 1884 union { 1885 struct { 1886 uint32_t word4; 1887#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1888#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1889#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1890 } req; 1891 struct { 1892 uint32_t word4; 1893#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1894#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1895#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1896#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1897#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1898#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1899 } rsp; 1900 } u; 1901}; 1902 1903struct lpfc_mbx_query_fw_config { 1904 struct mbox_header header; 1905 struct { 1906 uint32_t config_number; 1907#define LPFC_FC_FCOE 0x00000007 1908 uint32_t asic_revision; 1909 uint32_t physical_port; 1910 uint32_t function_mode; 1911#define LPFC_FCOE_INI_MODE 0x00000040 1912#define LPFC_FCOE_TGT_MODE 0x00000080 1913#define LPFC_DUA_MODE 0x00000800 1914 uint32_t ulp0_mode; 1915#define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1916#define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1917 uint32_t ulp0_nap_words[12]; 1918 uint32_t ulp1_mode; 1919 uint32_t ulp1_nap_words[12]; 1920 uint32_t function_capabilities; 1921 uint32_t cqid_base; 1922 uint32_t cqid_tot; 1923 uint32_t eqid_base; 1924 uint32_t eqid_tot; 1925 uint32_t ulp0_nap2_words[2]; 1926 uint32_t ulp1_nap2_words[2]; 1927 } rsp; 1928}; 1929 1930struct lpfc_mbx_set_beacon_config { 1931 struct mbox_header header; 1932 uint32_t word4; 1933#define lpfc_mbx_set_beacon_port_num_SHIFT 0 1934#define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1935#define lpfc_mbx_set_beacon_port_num_WORD word4 1936#define lpfc_mbx_set_beacon_port_type_SHIFT 6 1937#define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1938#define lpfc_mbx_set_beacon_port_type_WORD word4 1939#define lpfc_mbx_set_beacon_state_SHIFT 8 1940#define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1941#define lpfc_mbx_set_beacon_state_WORD word4 1942#define lpfc_mbx_set_beacon_duration_SHIFT 16 1943#define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1944#define lpfc_mbx_set_beacon_duration_WORD word4 1945 1946/* COMMON_SET_BEACON_CONFIG_V1 */ 1947#define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1948#define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1949#define lpfc_mbx_set_beacon_duration_v1_WORD word4 1950 uint32_t word5; /* RESERVED */ 1951}; 1952 1953struct lpfc_id_range { 1954 uint32_t word5; 1955#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1956#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1957#define lpfc_mbx_rsrc_id_word4_0_WORD word5 1958#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1959#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1960#define lpfc_mbx_rsrc_id_word4_1_WORD word5 1961}; 1962 1963struct lpfc_mbx_set_link_diag_state { 1964 struct mbox_header header; 1965 union { 1966 struct { 1967 uint32_t word0; 1968#define lpfc_mbx_set_diag_state_diag_SHIFT 0 1969#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1970#define lpfc_mbx_set_diag_state_diag_WORD word0 1971#define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1972#define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1973#define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1974#define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1975#define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1976#define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1977#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1978#define lpfc_mbx_set_diag_state_link_num_WORD word0 1979#define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1980#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1981#define lpfc_mbx_set_diag_state_link_type_WORD word0 1982 } req; 1983 struct { 1984 uint32_t word0; 1985 } rsp; 1986 } u; 1987}; 1988 1989struct lpfc_mbx_set_link_diag_loopback { 1990 struct mbox_header header; 1991 union { 1992 struct { 1993 uint32_t word0; 1994#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1995#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1996#define lpfc_mbx_set_diag_lpbk_type_WORD word0 1997#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1998#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1999#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 2000#define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 2001#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 2002#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 2003#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 2004#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 2005#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 2006#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 2007 } req; 2008 struct { 2009 uint32_t word0; 2010 } rsp; 2011 } u; 2012}; 2013 2014struct lpfc_mbx_run_link_diag_test { 2015 struct mbox_header header; 2016 union { 2017 struct { 2018 uint32_t word0; 2019#define lpfc_mbx_run_diag_test_link_num_SHIFT 16 2020#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 2021#define lpfc_mbx_run_diag_test_link_num_WORD word0 2022#define lpfc_mbx_run_diag_test_link_type_SHIFT 22 2023#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 2024#define lpfc_mbx_run_diag_test_link_type_WORD word0 2025 uint32_t word1; 2026#define lpfc_mbx_run_diag_test_test_id_SHIFT 0 2027#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 2028#define lpfc_mbx_run_diag_test_test_id_WORD word1 2029#define lpfc_mbx_run_diag_test_loops_SHIFT 16 2030#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 2031#define lpfc_mbx_run_diag_test_loops_WORD word1 2032 uint32_t word2; 2033#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 2034#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 2035#define lpfc_mbx_run_diag_test_test_ver_WORD word2 2036#define lpfc_mbx_run_diag_test_err_act_SHIFT 16 2037#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 2038#define lpfc_mbx_run_diag_test_err_act_WORD word2 2039 } req; 2040 struct { 2041 uint32_t word0; 2042 } rsp; 2043 } u; 2044}; 2045 2046/* 2047 * struct lpfc_mbx_alloc_rsrc_extents: 2048 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 2049 * 6 words of header + 4 words of shared subcommand header + 2050 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 2051 * 2052 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 2053 * for extents payload. 2054 * 2055 * 212/2 (bytes per extent) = 106 extents. 2056 * 106/2 (extents per word) = 53 words. 2057 * lpfc_id_range id is statically size to 53. 2058 * 2059 * This mailbox definition is used for ALLOC or GET_ALLOCATED 2060 * extent ranges. For ALLOC, the type and cnt are required. 2061 * For GET_ALLOCATED, only the type is required. 2062 */ 2063struct lpfc_mbx_alloc_rsrc_extents { 2064 struct mbox_header header; 2065 union { 2066 struct { 2067 uint32_t word4; 2068#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 2069#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 2070#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 2071#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 2072#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 2073#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 2074 } req; 2075 struct { 2076 uint32_t word4; 2077#define lpfc_mbx_rsrc_cnt_SHIFT 0 2078#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 2079#define lpfc_mbx_rsrc_cnt_WORD word4 2080 struct lpfc_id_range id[53]; 2081 } rsp; 2082 } u; 2083}; 2084 2085/* 2086 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2087 * structure shares the same SHIFT/MASK/WORD defines provided in the 2088 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2089 * the structures defined above. This non-embedded structure provides for the 2090 * maximum number of extents supported by the port. 2091 */ 2092struct lpfc_mbx_nembed_rsrc_extent { 2093 union lpfc_sli4_cfg_shdr cfg_shdr; 2094 uint32_t word4; 2095 struct lpfc_id_range id; 2096}; 2097 2098struct lpfc_mbx_dealloc_rsrc_extents { 2099 struct mbox_header header; 2100 struct { 2101 uint32_t word4; 2102#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2103#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2104#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2105 } req; 2106 2107}; 2108 2109/* Start SLI4 FCoE specific mbox structures. */ 2110 2111struct lpfc_mbx_post_hdr_tmpl { 2112 struct mbox_header header; 2113 uint32_t word10; 2114#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2115#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2116#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2117#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2118#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2119#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2120 uint32_t rpi_paddr_lo; 2121 uint32_t rpi_paddr_hi; 2122}; 2123 2124struct sli4_sge { /* SLI-4 */ 2125 uint32_t addr_hi; 2126 uint32_t addr_lo; 2127 2128 uint32_t word2; 2129#define lpfc_sli4_sge_offset_SHIFT 0 2130#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2131#define lpfc_sli4_sge_offset_WORD word2 2132#define lpfc_sli4_sge_type_SHIFT 27 2133#define lpfc_sli4_sge_type_MASK 0x0000000F 2134#define lpfc_sli4_sge_type_WORD word2 2135#define LPFC_SGE_TYPE_DATA 0x0 2136#define LPFC_SGE_TYPE_DIF 0x4 2137#define LPFC_SGE_TYPE_LSP 0x5 2138#define LPFC_SGE_TYPE_PEDIF 0x6 2139#define LPFC_SGE_TYPE_PESEED 0x7 2140#define LPFC_SGE_TYPE_DISEED 0x8 2141#define LPFC_SGE_TYPE_ENC 0x9 2142#define LPFC_SGE_TYPE_ATM 0xA 2143#define LPFC_SGE_TYPE_SKIP 0xC 2144#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2145#define lpfc_sli4_sge_last_MASK 0x00000001 2146#define lpfc_sli4_sge_last_WORD word2 2147 uint32_t sge_len; 2148}; 2149 2150struct sli4_hybrid_sgl { 2151 struct list_head list_node; 2152 struct sli4_sge *dma_sgl; 2153 dma_addr_t dma_phys_sgl; 2154}; 2155 2156struct fcp_cmd_rsp_buf { 2157 struct list_head list_node; 2158 2159 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2160 struct fcp_cmnd *fcp_cmnd; 2161 struct fcp_rsp *fcp_rsp; 2162 2163 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2164 dma_addr_t fcp_cmd_rsp_dma_handle; 2165}; 2166 2167struct sli4_sge_diseed { /* SLI-4 */ 2168 uint32_t ref_tag; 2169 uint32_t ref_tag_tran; 2170 2171 uint32_t word2; 2172#define lpfc_sli4_sge_dif_apptran_SHIFT 0 2173#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2174#define lpfc_sli4_sge_dif_apptran_WORD word2 2175#define lpfc_sli4_sge_dif_af_SHIFT 24 2176#define lpfc_sli4_sge_dif_af_MASK 0x00000001 2177#define lpfc_sli4_sge_dif_af_WORD word2 2178#define lpfc_sli4_sge_dif_na_SHIFT 25 2179#define lpfc_sli4_sge_dif_na_MASK 0x00000001 2180#define lpfc_sli4_sge_dif_na_WORD word2 2181#define lpfc_sli4_sge_dif_hi_SHIFT 26 2182#define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2183#define lpfc_sli4_sge_dif_hi_WORD word2 2184#define lpfc_sli4_sge_dif_type_SHIFT 27 2185#define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2186#define lpfc_sli4_sge_dif_type_WORD word2 2187#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2188#define lpfc_sli4_sge_dif_last_MASK 0x00000001 2189#define lpfc_sli4_sge_dif_last_WORD word2 2190 uint32_t word3; 2191#define lpfc_sli4_sge_dif_apptag_SHIFT 0 2192#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2193#define lpfc_sli4_sge_dif_apptag_WORD word3 2194#define lpfc_sli4_sge_dif_bs_SHIFT 16 2195#define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2196#define lpfc_sli4_sge_dif_bs_WORD word3 2197#define lpfc_sli4_sge_dif_ai_SHIFT 19 2198#define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2199#define lpfc_sli4_sge_dif_ai_WORD word3 2200#define lpfc_sli4_sge_dif_me_SHIFT 20 2201#define lpfc_sli4_sge_dif_me_MASK 0x00000001 2202#define lpfc_sli4_sge_dif_me_WORD word3 2203#define lpfc_sli4_sge_dif_re_SHIFT 21 2204#define lpfc_sli4_sge_dif_re_MASK 0x00000001 2205#define lpfc_sli4_sge_dif_re_WORD word3 2206#define lpfc_sli4_sge_dif_ce_SHIFT 22 2207#define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2208#define lpfc_sli4_sge_dif_ce_WORD word3 2209#define lpfc_sli4_sge_dif_nr_SHIFT 23 2210#define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2211#define lpfc_sli4_sge_dif_nr_WORD word3 2212#define lpfc_sli4_sge_dif_oprx_SHIFT 24 2213#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2214#define lpfc_sli4_sge_dif_oprx_WORD word3 2215#define lpfc_sli4_sge_dif_optx_SHIFT 28 2216#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2217#define lpfc_sli4_sge_dif_optx_WORD word3 2218/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2219}; 2220 2221struct fcf_record { 2222 uint32_t max_rcv_size; 2223 uint32_t fka_adv_period; 2224 uint32_t fip_priority; 2225 uint32_t word3; 2226#define lpfc_fcf_record_mac_0_SHIFT 0 2227#define lpfc_fcf_record_mac_0_MASK 0x000000FF 2228#define lpfc_fcf_record_mac_0_WORD word3 2229#define lpfc_fcf_record_mac_1_SHIFT 8 2230#define lpfc_fcf_record_mac_1_MASK 0x000000FF 2231#define lpfc_fcf_record_mac_1_WORD word3 2232#define lpfc_fcf_record_mac_2_SHIFT 16 2233#define lpfc_fcf_record_mac_2_MASK 0x000000FF 2234#define lpfc_fcf_record_mac_2_WORD word3 2235#define lpfc_fcf_record_mac_3_SHIFT 24 2236#define lpfc_fcf_record_mac_3_MASK 0x000000FF 2237#define lpfc_fcf_record_mac_3_WORD word3 2238 uint32_t word4; 2239#define lpfc_fcf_record_mac_4_SHIFT 0 2240#define lpfc_fcf_record_mac_4_MASK 0x000000FF 2241#define lpfc_fcf_record_mac_4_WORD word4 2242#define lpfc_fcf_record_mac_5_SHIFT 8 2243#define lpfc_fcf_record_mac_5_MASK 0x000000FF 2244#define lpfc_fcf_record_mac_5_WORD word4 2245#define lpfc_fcf_record_fcf_avail_SHIFT 16 2246#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2247#define lpfc_fcf_record_fcf_avail_WORD word4 2248#define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2249#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2250#define lpfc_fcf_record_mac_addr_prov_WORD word4 2251#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2252#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2253 uint32_t word5; 2254#define lpfc_fcf_record_fab_name_0_SHIFT 0 2255#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2256#define lpfc_fcf_record_fab_name_0_WORD word5 2257#define lpfc_fcf_record_fab_name_1_SHIFT 8 2258#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2259#define lpfc_fcf_record_fab_name_1_WORD word5 2260#define lpfc_fcf_record_fab_name_2_SHIFT 16 2261#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2262#define lpfc_fcf_record_fab_name_2_WORD word5 2263#define lpfc_fcf_record_fab_name_3_SHIFT 24 2264#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2265#define lpfc_fcf_record_fab_name_3_WORD word5 2266 uint32_t word6; 2267#define lpfc_fcf_record_fab_name_4_SHIFT 0 2268#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2269#define lpfc_fcf_record_fab_name_4_WORD word6 2270#define lpfc_fcf_record_fab_name_5_SHIFT 8 2271#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2272#define lpfc_fcf_record_fab_name_5_WORD word6 2273#define lpfc_fcf_record_fab_name_6_SHIFT 16 2274#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2275#define lpfc_fcf_record_fab_name_6_WORD word6 2276#define lpfc_fcf_record_fab_name_7_SHIFT 24 2277#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2278#define lpfc_fcf_record_fab_name_7_WORD word6 2279 uint32_t word7; 2280#define lpfc_fcf_record_fc_map_0_SHIFT 0 2281#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2282#define lpfc_fcf_record_fc_map_0_WORD word7 2283#define lpfc_fcf_record_fc_map_1_SHIFT 8 2284#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2285#define lpfc_fcf_record_fc_map_1_WORD word7 2286#define lpfc_fcf_record_fc_map_2_SHIFT 16 2287#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2288#define lpfc_fcf_record_fc_map_2_WORD word7 2289#define lpfc_fcf_record_fcf_valid_SHIFT 24 2290#define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2291#define lpfc_fcf_record_fcf_valid_WORD word7 2292#define lpfc_fcf_record_fcf_fc_SHIFT 25 2293#define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2294#define lpfc_fcf_record_fcf_fc_WORD word7 2295#define lpfc_fcf_record_fcf_sol_SHIFT 31 2296#define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2297#define lpfc_fcf_record_fcf_sol_WORD word7 2298 uint32_t word8; 2299#define lpfc_fcf_record_fcf_index_SHIFT 0 2300#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2301#define lpfc_fcf_record_fcf_index_WORD word8 2302#define lpfc_fcf_record_fcf_state_SHIFT 16 2303#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2304#define lpfc_fcf_record_fcf_state_WORD word8 2305 uint8_t vlan_bitmap[512]; 2306 uint32_t word137; 2307#define lpfc_fcf_record_switch_name_0_SHIFT 0 2308#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2309#define lpfc_fcf_record_switch_name_0_WORD word137 2310#define lpfc_fcf_record_switch_name_1_SHIFT 8 2311#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2312#define lpfc_fcf_record_switch_name_1_WORD word137 2313#define lpfc_fcf_record_switch_name_2_SHIFT 16 2314#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2315#define lpfc_fcf_record_switch_name_2_WORD word137 2316#define lpfc_fcf_record_switch_name_3_SHIFT 24 2317#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2318#define lpfc_fcf_record_switch_name_3_WORD word137 2319 uint32_t word138; 2320#define lpfc_fcf_record_switch_name_4_SHIFT 0 2321#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2322#define lpfc_fcf_record_switch_name_4_WORD word138 2323#define lpfc_fcf_record_switch_name_5_SHIFT 8 2324#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2325#define lpfc_fcf_record_switch_name_5_WORD word138 2326#define lpfc_fcf_record_switch_name_6_SHIFT 16 2327#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2328#define lpfc_fcf_record_switch_name_6_WORD word138 2329#define lpfc_fcf_record_switch_name_7_SHIFT 24 2330#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2331#define lpfc_fcf_record_switch_name_7_WORD word138 2332}; 2333 2334struct lpfc_mbx_read_fcf_tbl { 2335 union lpfc_sli4_cfg_shdr cfg_shdr; 2336 union { 2337 struct { 2338 uint32_t word10; 2339#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2340#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2341#define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2342 } request; 2343 struct { 2344 uint32_t eventag; 2345 } response; 2346 } u; 2347 uint32_t word11; 2348#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2349#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2350#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2351}; 2352 2353struct lpfc_mbx_add_fcf_tbl_entry { 2354 union lpfc_sli4_cfg_shdr cfg_shdr; 2355 uint32_t word10; 2356#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2357#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2358#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2359 struct lpfc_mbx_sge fcf_sge; 2360}; 2361 2362struct lpfc_mbx_del_fcf_tbl_entry { 2363 struct mbox_header header; 2364 uint32_t word10; 2365#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2366#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2367#define lpfc_mbx_del_fcf_tbl_count_WORD word10 2368#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2369#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2370#define lpfc_mbx_del_fcf_tbl_index_WORD word10 2371}; 2372 2373struct lpfc_mbx_redisc_fcf_tbl { 2374 struct mbox_header header; 2375 uint32_t word10; 2376#define lpfc_mbx_redisc_fcf_count_SHIFT 0 2377#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2378#define lpfc_mbx_redisc_fcf_count_WORD word10 2379 uint32_t resvd; 2380 uint32_t word12; 2381#define lpfc_mbx_redisc_fcf_index_SHIFT 0 2382#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2383#define lpfc_mbx_redisc_fcf_index_WORD word12 2384}; 2385 2386/* Status field for embedded SLI_CONFIG mailbox command */ 2387#define STATUS_SUCCESS 0x0 2388#define STATUS_FAILED 0x1 2389#define STATUS_ILLEGAL_REQUEST 0x2 2390#define STATUS_ILLEGAL_FIELD 0x3 2391#define STATUS_INSUFFICIENT_BUFFER 0x4 2392#define STATUS_UNAUTHORIZED_REQUEST 0x5 2393#define STATUS_FLASHROM_SAVE_FAILED 0x17 2394#define STATUS_FLASHROM_RESTORE_FAILED 0x18 2395#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2396#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2397#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2398#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2399#define STATUS_ASSERT_FAILED 0x1e 2400#define STATUS_INVALID_SESSION 0x1f 2401#define STATUS_INVALID_CONNECTION 0x20 2402#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2403#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2404#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2405#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2406#define STATUS_FLASHROM_READ_FAILED 0x27 2407#define STATUS_POLL_IOCTL_TIMEOUT 0x28 2408#define STATUS_ERROR_ACITMAIN 0x2a 2409#define STATUS_REBOOT_REQUIRED 0x2c 2410#define STATUS_FCF_IN_USE 0x3a 2411#define STATUS_FCF_TABLE_EMPTY 0x43 2412 2413/* 2414 * Additional status field for embedded SLI_CONFIG mailbox 2415 * command. 2416 */ 2417#define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2418#define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2419#define ADD_STATUS_INVALID_REQUEST 0x4B 2420#define ADD_STATUS_INVALID_OBJECT_NAME 0xA0 2421#define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2422 2423struct lpfc_mbx_sli4_config { 2424 struct mbox_header header; 2425}; 2426 2427struct lpfc_mbx_init_vfi { 2428 uint32_t word1; 2429#define lpfc_init_vfi_vr_SHIFT 31 2430#define lpfc_init_vfi_vr_MASK 0x00000001 2431#define lpfc_init_vfi_vr_WORD word1 2432#define lpfc_init_vfi_vt_SHIFT 30 2433#define lpfc_init_vfi_vt_MASK 0x00000001 2434#define lpfc_init_vfi_vt_WORD word1 2435#define lpfc_init_vfi_vf_SHIFT 29 2436#define lpfc_init_vfi_vf_MASK 0x00000001 2437#define lpfc_init_vfi_vf_WORD word1 2438#define lpfc_init_vfi_vp_SHIFT 28 2439#define lpfc_init_vfi_vp_MASK 0x00000001 2440#define lpfc_init_vfi_vp_WORD word1 2441#define lpfc_init_vfi_vfi_SHIFT 0 2442#define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2443#define lpfc_init_vfi_vfi_WORD word1 2444 uint32_t word2; 2445#define lpfc_init_vfi_vpi_SHIFT 16 2446#define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2447#define lpfc_init_vfi_vpi_WORD word2 2448#define lpfc_init_vfi_fcfi_SHIFT 0 2449#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2450#define lpfc_init_vfi_fcfi_WORD word2 2451 uint32_t word3; 2452#define lpfc_init_vfi_pri_SHIFT 13 2453#define lpfc_init_vfi_pri_MASK 0x00000007 2454#define lpfc_init_vfi_pri_WORD word3 2455#define lpfc_init_vfi_vf_id_SHIFT 1 2456#define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2457#define lpfc_init_vfi_vf_id_WORD word3 2458 uint32_t word4; 2459#define lpfc_init_vfi_hop_count_SHIFT 24 2460#define lpfc_init_vfi_hop_count_MASK 0x000000FF 2461#define lpfc_init_vfi_hop_count_WORD word4 2462}; 2463#define MBX_VFI_IN_USE 0x9F02 2464 2465 2466struct lpfc_mbx_reg_vfi { 2467 uint32_t word1; 2468#define lpfc_reg_vfi_upd_SHIFT 29 2469#define lpfc_reg_vfi_upd_MASK 0x00000001 2470#define lpfc_reg_vfi_upd_WORD word1 2471#define lpfc_reg_vfi_vp_SHIFT 28 2472#define lpfc_reg_vfi_vp_MASK 0x00000001 2473#define lpfc_reg_vfi_vp_WORD word1 2474#define lpfc_reg_vfi_vfi_SHIFT 0 2475#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2476#define lpfc_reg_vfi_vfi_WORD word1 2477 uint32_t word2; 2478#define lpfc_reg_vfi_vpi_SHIFT 16 2479#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2480#define lpfc_reg_vfi_vpi_WORD word2 2481#define lpfc_reg_vfi_fcfi_SHIFT 0 2482#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2483#define lpfc_reg_vfi_fcfi_WORD word2 2484 uint32_t wwn[2]; 2485 struct ulp_bde64 bde; 2486 uint32_t e_d_tov; 2487 uint32_t r_a_tov; 2488 uint32_t word10; 2489#define lpfc_reg_vfi_nport_id_SHIFT 0 2490#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2491#define lpfc_reg_vfi_nport_id_WORD word10 2492#define lpfc_reg_vfi_bbcr_SHIFT 27 2493#define lpfc_reg_vfi_bbcr_MASK 0x00000001 2494#define lpfc_reg_vfi_bbcr_WORD word10 2495#define lpfc_reg_vfi_bbscn_SHIFT 28 2496#define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2497#define lpfc_reg_vfi_bbscn_WORD word10 2498}; 2499 2500struct lpfc_mbx_init_vpi { 2501 uint32_t word1; 2502#define lpfc_init_vpi_vfi_SHIFT 16 2503#define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2504#define lpfc_init_vpi_vfi_WORD word1 2505#define lpfc_init_vpi_vpi_SHIFT 0 2506#define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2507#define lpfc_init_vpi_vpi_WORD word1 2508}; 2509 2510struct lpfc_mbx_read_vpi { 2511 uint32_t word1_rsvd; 2512 uint32_t word2; 2513#define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2514#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2515#define lpfc_mbx_read_vpi_vnportid_WORD word2 2516 uint32_t word3_rsvd; 2517 uint32_t word4; 2518#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2519#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2520#define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2521#define lpfc_mbx_read_vpi_pb_SHIFT 15 2522#define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2523#define lpfc_mbx_read_vpi_pb_WORD word4 2524#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2525#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2526#define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2527#define lpfc_mbx_read_vpi_ns_SHIFT 30 2528#define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2529#define lpfc_mbx_read_vpi_ns_WORD word4 2530#define lpfc_mbx_read_vpi_hl_SHIFT 31 2531#define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2532#define lpfc_mbx_read_vpi_hl_WORD word4 2533 uint32_t word5_rsvd; 2534 uint32_t word6; 2535#define lpfc_mbx_read_vpi_vpi_SHIFT 0 2536#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2537#define lpfc_mbx_read_vpi_vpi_WORD word6 2538 uint32_t word7; 2539#define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2540#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2541#define lpfc_mbx_read_vpi_mac_0_WORD word7 2542#define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2543#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2544#define lpfc_mbx_read_vpi_mac_1_WORD word7 2545#define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2546#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2547#define lpfc_mbx_read_vpi_mac_2_WORD word7 2548#define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2549#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2550#define lpfc_mbx_read_vpi_mac_3_WORD word7 2551 uint32_t word8; 2552#define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2553#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2554#define lpfc_mbx_read_vpi_mac_4_WORD word8 2555#define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2556#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2557#define lpfc_mbx_read_vpi_mac_5_WORD word8 2558#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2559#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2560#define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2561#define lpfc_mbx_read_vpi_vv_SHIFT 28 2562#define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2563#define lpfc_mbx_read_vpi_vv_WORD word8 2564}; 2565 2566struct lpfc_mbx_unreg_vfi { 2567 uint32_t word1_rsvd; 2568 uint32_t word2; 2569#define lpfc_unreg_vfi_vfi_SHIFT 0 2570#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2571#define lpfc_unreg_vfi_vfi_WORD word2 2572}; 2573 2574struct lpfc_mbx_resume_rpi { 2575 uint32_t word1; 2576#define lpfc_resume_rpi_index_SHIFT 0 2577#define lpfc_resume_rpi_index_MASK 0x0000FFFF 2578#define lpfc_resume_rpi_index_WORD word1 2579#define lpfc_resume_rpi_ii_SHIFT 30 2580#define lpfc_resume_rpi_ii_MASK 0x00000003 2581#define lpfc_resume_rpi_ii_WORD word1 2582#define RESUME_INDEX_RPI 0 2583#define RESUME_INDEX_VPI 1 2584#define RESUME_INDEX_VFI 2 2585#define RESUME_INDEX_FCFI 3 2586 uint32_t event_tag; 2587}; 2588 2589#define REG_FCF_INVALID_QID 0xFFFF 2590struct lpfc_mbx_reg_fcfi { 2591 uint32_t word1; 2592#define lpfc_reg_fcfi_info_index_SHIFT 0 2593#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2594#define lpfc_reg_fcfi_info_index_WORD word1 2595#define lpfc_reg_fcfi_fcfi_SHIFT 16 2596#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2597#define lpfc_reg_fcfi_fcfi_WORD word1 2598 uint32_t word2; 2599#define lpfc_reg_fcfi_rq_id1_SHIFT 0 2600#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2601#define lpfc_reg_fcfi_rq_id1_WORD word2 2602#define lpfc_reg_fcfi_rq_id0_SHIFT 16 2603#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2604#define lpfc_reg_fcfi_rq_id0_WORD word2 2605 uint32_t word3; 2606#define lpfc_reg_fcfi_rq_id3_SHIFT 0 2607#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2608#define lpfc_reg_fcfi_rq_id3_WORD word3 2609#define lpfc_reg_fcfi_rq_id2_SHIFT 16 2610#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2611#define lpfc_reg_fcfi_rq_id2_WORD word3 2612 uint32_t word4; 2613#define lpfc_reg_fcfi_type_match0_SHIFT 24 2614#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2615#define lpfc_reg_fcfi_type_match0_WORD word4 2616#define lpfc_reg_fcfi_type_mask0_SHIFT 16 2617#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2618#define lpfc_reg_fcfi_type_mask0_WORD word4 2619#define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2620#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2621#define lpfc_reg_fcfi_rctl_match0_WORD word4 2622#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2623#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2624#define lpfc_reg_fcfi_rctl_mask0_WORD word4 2625 uint32_t word5; 2626#define lpfc_reg_fcfi_type_match1_SHIFT 24 2627#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2628#define lpfc_reg_fcfi_type_match1_WORD word5 2629#define lpfc_reg_fcfi_type_mask1_SHIFT 16 2630#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2631#define lpfc_reg_fcfi_type_mask1_WORD word5 2632#define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2633#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2634#define lpfc_reg_fcfi_rctl_match1_WORD word5 2635#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2636#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2637#define lpfc_reg_fcfi_rctl_mask1_WORD word5 2638 uint32_t word6; 2639#define lpfc_reg_fcfi_type_match2_SHIFT 24 2640#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2641#define lpfc_reg_fcfi_type_match2_WORD word6 2642#define lpfc_reg_fcfi_type_mask2_SHIFT 16 2643#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2644#define lpfc_reg_fcfi_type_mask2_WORD word6 2645#define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2646#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2647#define lpfc_reg_fcfi_rctl_match2_WORD word6 2648#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2649#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2650#define lpfc_reg_fcfi_rctl_mask2_WORD word6 2651 uint32_t word7; 2652#define lpfc_reg_fcfi_type_match3_SHIFT 24 2653#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2654#define lpfc_reg_fcfi_type_match3_WORD word7 2655#define lpfc_reg_fcfi_type_mask3_SHIFT 16 2656#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2657#define lpfc_reg_fcfi_type_mask3_WORD word7 2658#define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2659#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2660#define lpfc_reg_fcfi_rctl_match3_WORD word7 2661#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2662#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2663#define lpfc_reg_fcfi_rctl_mask3_WORD word7 2664 uint32_t word8; 2665#define lpfc_reg_fcfi_mam_SHIFT 13 2666#define lpfc_reg_fcfi_mam_MASK 0x00000003 2667#define lpfc_reg_fcfi_mam_WORD word8 2668#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2669#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2670#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2671#define lpfc_reg_fcfi_vv_SHIFT 12 2672#define lpfc_reg_fcfi_vv_MASK 0x00000001 2673#define lpfc_reg_fcfi_vv_WORD word8 2674#define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2675#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2676#define lpfc_reg_fcfi_vlan_tag_WORD word8 2677}; 2678 2679struct lpfc_mbx_reg_fcfi_mrq { 2680 uint32_t word1; 2681#define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2682#define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2683#define lpfc_reg_fcfi_mrq_info_index_WORD word1 2684#define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2685#define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2686#define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2687 uint32_t word2; 2688#define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2689#define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2690#define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2691#define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2692#define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2693#define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2694 uint32_t word3; 2695#define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2696#define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2697#define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2698#define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2699#define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2700#define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2701 uint32_t word4; 2702#define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2703#define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2704#define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2705#define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2706#define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2707#define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2708#define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2709#define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2710#define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2711#define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2712#define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2713#define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2714 uint32_t word5; 2715#define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2716#define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2717#define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2718#define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2719#define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2720#define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2721#define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2722#define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2723#define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2724#define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2725#define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2726#define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2727 uint32_t word6; 2728#define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2729#define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2730#define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2731#define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2732#define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2733#define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2734#define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2735#define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2736#define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2737#define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2738#define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2739#define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2740 uint32_t word7; 2741#define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2742#define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2743#define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2744#define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2745#define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2746#define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2747#define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2748#define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2749#define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2750#define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2751#define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2752#define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2753 uint32_t word8; 2754#define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2755#define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2756#define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2757#define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2758#define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2759#define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2760#define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2761#define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2762#define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2763#define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2764#define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2765#define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2766#define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2767#define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2768#define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2769#define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2770#define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2771#define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2772#define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2773#define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2774#define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2775#define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2776#define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2777#define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2778#define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2779#define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2780#define lpfc_reg_fcfi_mrq_pt7_WORD word8 2781#define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2782#define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2783#define lpfc_reg_fcfi_mrq_pt6_WORD word8 2784#define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2785#define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2786#define lpfc_reg_fcfi_mrq_pt5_WORD word8 2787#define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2788#define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2789#define lpfc_reg_fcfi_mrq_pt4_WORD word8 2790#define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2791#define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2792#define lpfc_reg_fcfi_mrq_pt3_WORD word8 2793#define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2794#define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2795#define lpfc_reg_fcfi_mrq_pt2_WORD word8 2796#define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2797#define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2798#define lpfc_reg_fcfi_mrq_pt1_WORD word8 2799#define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2800#define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2801#define lpfc_reg_fcfi_mrq_pt0_WORD word8 2802#define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2803#define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2804#define lpfc_reg_fcfi_mrq_xmv_WORD word8 2805#define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2806#define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2807#define lpfc_reg_fcfi_mrq_mode_WORD word8 2808#define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2809#define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2810#define lpfc_reg_fcfi_mrq_vv_WORD word8 2811#define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2812#define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2813#define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2814 uint32_t word9; 2815#define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2816#define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2817#define lpfc_reg_fcfi_mrq_policy_WORD word9 2818#define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2819#define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2820#define lpfc_reg_fcfi_mrq_filter_WORD word9 2821#define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2822#define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2823#define lpfc_reg_fcfi_mrq_npairs_WORD word9 2824 uint32_t word10; 2825 uint32_t word11; 2826 uint32_t word12; 2827 uint32_t word13; 2828 uint32_t word14; 2829 uint32_t word15; 2830 uint32_t word16; 2831}; 2832 2833struct lpfc_mbx_unreg_fcfi { 2834 uint32_t word1_rsv; 2835 uint32_t word2; 2836#define lpfc_unreg_fcfi_SHIFT 0 2837#define lpfc_unreg_fcfi_MASK 0x0000FFFF 2838#define lpfc_unreg_fcfi_WORD word2 2839}; 2840 2841struct lpfc_mbx_read_rev { 2842 uint32_t word1; 2843#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2844#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2845#define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2846#define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2847#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2848#define lpfc_mbx_rd_rev_fcoe_WORD word1 2849#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2850#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2851#define lpfc_mbx_rd_rev_cee_ver_WORD word1 2852#define LPFC_PREDCBX_CEE_MODE 0 2853#define LPFC_DCBX_CEE_MODE 1 2854#define lpfc_mbx_rd_rev_vpd_SHIFT 29 2855#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2856#define lpfc_mbx_rd_rev_vpd_WORD word1 2857 uint32_t first_hw_rev; 2858#define LPFC_G7_ASIC_1 0xd 2859 uint32_t second_hw_rev; 2860 uint32_t word4_rsvd; 2861 uint32_t third_hw_rev; 2862 uint32_t word6; 2863#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2864#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2865#define lpfc_mbx_rd_rev_fcph_low_WORD word6 2866#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2867#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2868#define lpfc_mbx_rd_rev_fcph_high_WORD word6 2869#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2870#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2871#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2872#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2873#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2874#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2875 uint32_t word7_rsvd; 2876 uint32_t fw_id_rev; 2877 uint8_t fw_name[16]; 2878 uint32_t ulp_fw_id_rev; 2879 uint8_t ulp_fw_name[16]; 2880 uint32_t word18_47_rsvd[30]; 2881 uint32_t word48; 2882#define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2883#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2884#define lpfc_mbx_rd_rev_avail_len_WORD word48 2885 uint32_t vpd_paddr_low; 2886 uint32_t vpd_paddr_high; 2887 uint32_t avail_vpd_len; 2888 uint32_t rsvd_52_63[12]; 2889}; 2890 2891struct lpfc_mbx_read_config { 2892 uint32_t word1; 2893#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2894#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2895#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2896#define lpfc_mbx_rd_conf_fawwpn_SHIFT 30 2897#define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001 2898#define lpfc_mbx_rd_conf_fawwpn_WORD word1 2899#define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */ 2900#define lpfc_mbx_rd_conf_wcs_MASK 0x00000001 2901#define lpfc_mbx_rd_conf_wcs_WORD word1 2902#define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */ 2903#define lpfc_mbx_rd_conf_acs_MASK 0x00000001 2904#define lpfc_mbx_rd_conf_acs_WORD word1 2905 uint32_t word2; 2906#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2907#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2908#define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2909#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2910#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2911#define lpfc_mbx_rd_conf_lnk_type_WORD word2 2912#define LPFC_LNK_TYPE_GE 0 2913#define LPFC_LNK_TYPE_FC 1 2914#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2915#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2916#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2917#define lpfc_mbx_rd_conf_trunk_SHIFT 12 2918#define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2919#define lpfc_mbx_rd_conf_trunk_WORD word2 2920#define lpfc_mbx_rd_conf_pt_SHIFT 20 2921#define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2922#define lpfc_mbx_rd_conf_pt_WORD word2 2923#define lpfc_mbx_rd_conf_tf_SHIFT 22 2924#define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2925#define lpfc_mbx_rd_conf_tf_WORD word2 2926#define lpfc_mbx_rd_conf_ptv_SHIFT 23 2927#define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2928#define lpfc_mbx_rd_conf_ptv_WORD word2 2929#define lpfc_mbx_rd_conf_topology_SHIFT 24 2930#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2931#define lpfc_mbx_rd_conf_topology_WORD word2 2932 uint32_t rsvd_3; 2933 uint32_t word4; 2934#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2935#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2936#define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2937 uint32_t rsvd_5; 2938 uint32_t word6; 2939#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2940#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2941#define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2942#define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2943#define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2944#define lpfc_mbx_rd_conf_link_speed_WORD word6 2945 uint32_t rsvd_7; 2946 uint32_t word8; 2947#define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2948#define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2949#define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2950#define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2951#define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2952#define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2953#define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2954#define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2955#define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2956 uint32_t word9; 2957#define lpfc_mbx_rd_conf_lmt_SHIFT 0 2958#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2959#define lpfc_mbx_rd_conf_lmt_WORD word9 2960 uint32_t rsvd_10; 2961 uint32_t rsvd_11; 2962 uint32_t word12; 2963#define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2964#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2965#define lpfc_mbx_rd_conf_xri_base_WORD word12 2966#define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2967#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2968#define lpfc_mbx_rd_conf_xri_count_WORD word12 2969 uint32_t word13; 2970#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2971#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2972#define lpfc_mbx_rd_conf_rpi_base_WORD word13 2973#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2974#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2975#define lpfc_mbx_rd_conf_rpi_count_WORD word13 2976 uint32_t word14; 2977#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2978#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2979#define lpfc_mbx_rd_conf_vpi_base_WORD word14 2980#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2981#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2982#define lpfc_mbx_rd_conf_vpi_count_WORD word14 2983 uint32_t word15; 2984#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2985#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2986#define lpfc_mbx_rd_conf_vfi_base_WORD word15 2987#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2988#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2989#define lpfc_mbx_rd_conf_vfi_count_WORD word15 2990 uint32_t word16; 2991#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2992#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2993#define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2994 uint32_t word17; 2995#define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2996#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2997#define lpfc_mbx_rd_conf_rq_count_WORD word17 2998#define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2999#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 3000#define lpfc_mbx_rd_conf_eq_count_WORD word17 3001 uint32_t word18; 3002#define lpfc_mbx_rd_conf_wq_count_SHIFT 0 3003#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 3004#define lpfc_mbx_rd_conf_wq_count_WORD word18 3005#define lpfc_mbx_rd_conf_cq_count_SHIFT 16 3006#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 3007#define lpfc_mbx_rd_conf_cq_count_WORD word18 3008}; 3009 3010struct lpfc_mbx_request_features { 3011 uint32_t word1; 3012#define lpfc_mbx_rq_ftr_qry_SHIFT 0 3013#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 3014#define lpfc_mbx_rq_ftr_qry_WORD word1 3015 uint32_t word2; 3016#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 3017#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 3018#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 3019#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 3020#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 3021#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 3022#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 3023#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 3024#define lpfc_mbx_rq_ftr_rq_dif_WORD word2 3025#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 3026#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 3027#define lpfc_mbx_rq_ftr_rq_vf_WORD word2 3028#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 3029#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 3030#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 3031#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 3032#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 3033#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 3034#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 3035#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 3036#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 3037#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 3038#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 3039#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 3040#define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3041#define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3042#define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3043#define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3044#define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3045#define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3046#define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3047#define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3048#define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 3049#define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 3050#define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 3051#define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 3052 uint32_t word3; 3053#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 3054#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 3055#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 3056#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 3057#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 3058#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 3059#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 3060#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 3061#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 3062#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 3063#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 3064#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 3065#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 3066#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 3067#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 3068#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 3069#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 3070#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 3071#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 3072#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 3073#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 3074#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3075#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3076#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3077#define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3078#define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3079#define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3080#define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3081#define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3082#define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 3083#define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 3084#define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 3085#define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 3086}; 3087 3088struct lpfc_mbx_memory_dump_type3 { 3089 uint32_t word1; 3090#define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3091#define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3092#define lpfc_mbx_memory_dump_type3_type_WORD word1 3093#define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3094#define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3095#define lpfc_mbx_memory_dump_type3_link_WORD word1 3096 uint32_t word2; 3097#define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3098#define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3099#define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3100#define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3101#define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3102#define lpfc_mbx_memory_dump_type3_offset_WORD word2 3103 uint32_t word3; 3104#define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3105#define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3106#define lpfc_mbx_memory_dump_type3_length_WORD word3 3107 uint32_t addr_lo; 3108 uint32_t addr_hi; 3109 uint32_t return_len; 3110}; 3111 3112#define DMP_PAGE_A0 0xa0 3113#define DMP_PAGE_A2 0xa2 3114#define DMP_SFF_PAGE_A0_SIZE 256 3115#define DMP_SFF_PAGE_A2_SIZE 256 3116 3117#define SFP_WAVELENGTH_LC1310 1310 3118#define SFP_WAVELENGTH_LL1550 1550 3119 3120 3121/* 3122 * * SFF-8472 TABLE 3.4 3123 * */ 3124#define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3125#define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3126#define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3127#define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3128#define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3129#define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3130#define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3131#define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3132#define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3133#define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3134#define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3135#define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3136#define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3137#define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3138#define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3139#define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3140 3141/* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3142 3143#define SSF_IDENTIFIER 0 3144#define SSF_EXT_IDENTIFIER 1 3145#define SSF_CONNECTOR 2 3146#define SSF_TRANSCEIVER_CODE_B0 3 3147#define SSF_TRANSCEIVER_CODE_B1 4 3148#define SSF_TRANSCEIVER_CODE_B2 5 3149#define SSF_TRANSCEIVER_CODE_B3 6 3150#define SSF_TRANSCEIVER_CODE_B4 7 3151#define SSF_TRANSCEIVER_CODE_B5 8 3152#define SSF_TRANSCEIVER_CODE_B6 9 3153#define SSF_TRANSCEIVER_CODE_B7 10 3154#define SSF_ENCODING 11 3155#define SSF_BR_NOMINAL 12 3156#define SSF_RATE_IDENTIFIER 13 3157#define SSF_LENGTH_9UM_KM 14 3158#define SSF_LENGTH_9UM 15 3159#define SSF_LENGTH_50UM_OM2 16 3160#define SSF_LENGTH_62UM_OM1 17 3161#define SFF_LENGTH_COPPER 18 3162#define SSF_LENGTH_50UM_OM3 19 3163#define SSF_VENDOR_NAME 20 3164#define SSF_VENDOR_OUI 36 3165#define SSF_VENDOR_PN 40 3166#define SSF_VENDOR_REV 56 3167#define SSF_WAVELENGTH_B1 60 3168#define SSF_WAVELENGTH_B0 61 3169#define SSF_CC_BASE 63 3170#define SSF_OPTIONS_B1 64 3171#define SSF_OPTIONS_B0 65 3172#define SSF_BR_MAX 66 3173#define SSF_BR_MIN 67 3174#define SSF_VENDOR_SN 68 3175#define SSF_DATE_CODE 84 3176#define SSF_MONITORING_TYPEDIAGNOSTIC 92 3177#define SSF_ENHANCED_OPTIONS 93 3178#define SFF_8472_COMPLIANCE 94 3179#define SSF_CC_EXT 95 3180#define SSF_A0_VENDOR_SPECIFIC 96 3181 3182/* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3183 3184#define SSF_TEMP_HIGH_ALARM 0 3185#define SSF_TEMP_LOW_ALARM 2 3186#define SSF_TEMP_HIGH_WARNING 4 3187#define SSF_TEMP_LOW_WARNING 6 3188#define SSF_VOLTAGE_HIGH_ALARM 8 3189#define SSF_VOLTAGE_LOW_ALARM 10 3190#define SSF_VOLTAGE_HIGH_WARNING 12 3191#define SSF_VOLTAGE_LOW_WARNING 14 3192#define SSF_BIAS_HIGH_ALARM 16 3193#define SSF_BIAS_LOW_ALARM 18 3194#define SSF_BIAS_HIGH_WARNING 20 3195#define SSF_BIAS_LOW_WARNING 22 3196#define SSF_TXPOWER_HIGH_ALARM 24 3197#define SSF_TXPOWER_LOW_ALARM 26 3198#define SSF_TXPOWER_HIGH_WARNING 28 3199#define SSF_TXPOWER_LOW_WARNING 30 3200#define SSF_RXPOWER_HIGH_ALARM 32 3201#define SSF_RXPOWER_LOW_ALARM 34 3202#define SSF_RXPOWER_HIGH_WARNING 36 3203#define SSF_RXPOWER_LOW_WARNING 38 3204#define SSF_EXT_CAL_CONSTANTS 56 3205#define SSF_CC_DMI 95 3206#define SFF_TEMPERATURE_B1 96 3207#define SFF_TEMPERATURE_B0 97 3208#define SFF_VCC_B1 98 3209#define SFF_VCC_B0 99 3210#define SFF_TX_BIAS_CURRENT_B1 100 3211#define SFF_TX_BIAS_CURRENT_B0 101 3212#define SFF_TXPOWER_B1 102 3213#define SFF_TXPOWER_B0 103 3214#define SFF_RXPOWER_B1 104 3215#define SFF_RXPOWER_B0 105 3216#define SSF_STATUS_CONTROL 110 3217#define SSF_ALARM_FLAGS 112 3218#define SSF_WARNING_FLAGS 116 3219#define SSF_EXT_TATUS_CONTROL_B1 118 3220#define SSF_EXT_TATUS_CONTROL_B0 119 3221#define SSF_A2_VENDOR_SPECIFIC 120 3222#define SSF_USER_EEPROM 128 3223#define SSF_VENDOR_CONTROL 148 3224 3225 3226/* 3227 * Tranceiver codes Fibre Channel SFF-8472 3228 * Table 3.5. 3229 */ 3230 3231struct sff_trasnceiver_codes_byte0 { 3232 uint8_t inifiband:4; 3233 uint8_t teng_ethernet:4; 3234}; 3235 3236struct sff_trasnceiver_codes_byte1 { 3237 uint8_t sonet:6; 3238 uint8_t escon:2; 3239}; 3240 3241struct sff_trasnceiver_codes_byte2 { 3242 uint8_t soNet:8; 3243}; 3244 3245struct sff_trasnceiver_codes_byte3 { 3246 uint8_t ethernet:8; 3247}; 3248 3249struct sff_trasnceiver_codes_byte4 { 3250 uint8_t fc_el_lo:1; 3251 uint8_t fc_lw_laser:1; 3252 uint8_t fc_sw_laser:1; 3253 uint8_t fc_md_distance:1; 3254 uint8_t fc_lg_distance:1; 3255 uint8_t fc_int_distance:1; 3256 uint8_t fc_short_distance:1; 3257 uint8_t fc_vld_distance:1; 3258}; 3259 3260struct sff_trasnceiver_codes_byte5 { 3261 uint8_t reserved1:1; 3262 uint8_t reserved2:1; 3263 uint8_t fc_sfp_active:1; /* Active cable */ 3264 uint8_t fc_sfp_passive:1; /* Passive cable */ 3265 uint8_t fc_lw_laser:1; /* Longwave laser */ 3266 uint8_t fc_sw_laser_sl:1; 3267 uint8_t fc_sw_laser_sn:1; 3268 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3269}; 3270 3271struct sff_trasnceiver_codes_byte6 { 3272 uint8_t fc_tm_sm:1; /* Single Mode */ 3273 uint8_t reserved:1; 3274 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3275 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3276 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3277 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3278 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3279}; 3280 3281struct sff_trasnceiver_codes_byte7 { 3282 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3283 uint8_t reserve:1; 3284 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3285 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3286 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3287 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3288 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3289 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3290}; 3291 3292/* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3293struct user_eeprom { 3294 uint8_t vendor_name[16]; 3295 uint8_t vendor_oui[3]; 3296 uint8_t vendor_pn[816]; 3297 uint8_t vendor_rev[4]; 3298 uint8_t vendor_sn[16]; 3299 uint8_t datecode[6]; 3300 uint8_t lot_code[2]; 3301 uint8_t reserved191[57]; 3302}; 3303 3304#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3305 &(~((SLI4_PAGE_SIZE)-1))) 3306 3307struct lpfc_sli4_parameters { 3308 uint32_t word0; 3309#define cfg_prot_type_SHIFT 0 3310#define cfg_prot_type_MASK 0x000000FF 3311#define cfg_prot_type_WORD word0 3312 uint32_t word1; 3313#define cfg_ft_SHIFT 0 3314#define cfg_ft_MASK 0x00000001 3315#define cfg_ft_WORD word1 3316#define cfg_sli_rev_SHIFT 4 3317#define cfg_sli_rev_MASK 0x0000000f 3318#define cfg_sli_rev_WORD word1 3319#define cfg_sli_family_SHIFT 8 3320#define cfg_sli_family_MASK 0x0000000f 3321#define cfg_sli_family_WORD word1 3322#define cfg_if_type_SHIFT 12 3323#define cfg_if_type_MASK 0x0000000f 3324#define cfg_if_type_WORD word1 3325#define cfg_sli_hint_1_SHIFT 16 3326#define cfg_sli_hint_1_MASK 0x000000ff 3327#define cfg_sli_hint_1_WORD word1 3328#define cfg_sli_hint_2_SHIFT 24 3329#define cfg_sli_hint_2_MASK 0x0000001f 3330#define cfg_sli_hint_2_WORD word1 3331 uint32_t word2; 3332#define cfg_eqav_SHIFT 31 3333#define cfg_eqav_MASK 0x00000001 3334#define cfg_eqav_WORD word2 3335 uint32_t word3; 3336 uint32_t word4; 3337#define cfg_cqv_SHIFT 14 3338#define cfg_cqv_MASK 0x00000003 3339#define cfg_cqv_WORD word4 3340#define cfg_cqpsize_SHIFT 16 3341#define cfg_cqpsize_MASK 0x000000ff 3342#define cfg_cqpsize_WORD word4 3343#define cfg_cqav_SHIFT 31 3344#define cfg_cqav_MASK 0x00000001 3345#define cfg_cqav_WORD word4 3346 uint32_t word5; 3347 uint32_t word6; 3348#define cfg_mqv_SHIFT 14 3349#define cfg_mqv_MASK 0x00000003 3350#define cfg_mqv_WORD word6 3351 uint32_t word7; 3352 uint32_t word8; 3353#define cfg_wqpcnt_SHIFT 0 3354#define cfg_wqpcnt_MASK 0x0000000f 3355#define cfg_wqpcnt_WORD word8 3356#define cfg_wqsize_SHIFT 8 3357#define cfg_wqsize_MASK 0x0000000f 3358#define cfg_wqsize_WORD word8 3359#define cfg_wqv_SHIFT 14 3360#define cfg_wqv_MASK 0x00000003 3361#define cfg_wqv_WORD word8 3362#define cfg_wqpsize_SHIFT 16 3363#define cfg_wqpsize_MASK 0x000000ff 3364#define cfg_wqpsize_WORD word8 3365 uint32_t word9; 3366 uint32_t word10; 3367#define cfg_rqv_SHIFT 14 3368#define cfg_rqv_MASK 0x00000003 3369#define cfg_rqv_WORD word10 3370 uint32_t word11; 3371#define cfg_rq_db_window_SHIFT 28 3372#define cfg_rq_db_window_MASK 0x0000000f 3373#define cfg_rq_db_window_WORD word11 3374 uint32_t word12; 3375#define cfg_fcoe_SHIFT 0 3376#define cfg_fcoe_MASK 0x00000001 3377#define cfg_fcoe_WORD word12 3378#define cfg_ext_SHIFT 1 3379#define cfg_ext_MASK 0x00000001 3380#define cfg_ext_WORD word12 3381#define cfg_hdrr_SHIFT 2 3382#define cfg_hdrr_MASK 0x00000001 3383#define cfg_hdrr_WORD word12 3384#define cfg_phwq_SHIFT 15 3385#define cfg_phwq_MASK 0x00000001 3386#define cfg_phwq_WORD word12 3387#define cfg_oas_SHIFT 25 3388#define cfg_oas_MASK 0x00000001 3389#define cfg_oas_WORD word12 3390#define cfg_loopbk_scope_SHIFT 28 3391#define cfg_loopbk_scope_MASK 0x0000000f 3392#define cfg_loopbk_scope_WORD word12 3393 uint32_t sge_supp_len; 3394 uint32_t word14; 3395#define cfg_sgl_page_cnt_SHIFT 0 3396#define cfg_sgl_page_cnt_MASK 0x0000000f 3397#define cfg_sgl_page_cnt_WORD word14 3398#define cfg_sgl_page_size_SHIFT 8 3399#define cfg_sgl_page_size_MASK 0x000000ff 3400#define cfg_sgl_page_size_WORD word14 3401#define cfg_sgl_pp_align_SHIFT 16 3402#define cfg_sgl_pp_align_MASK 0x000000ff 3403#define cfg_sgl_pp_align_WORD word14 3404 uint32_t word15; 3405 uint32_t word16; 3406 uint32_t word17; 3407 uint32_t word18; 3408 uint32_t word19; 3409#define cfg_ext_embed_cb_SHIFT 0 3410#define cfg_ext_embed_cb_MASK 0x00000001 3411#define cfg_ext_embed_cb_WORD word19 3412#define cfg_mds_diags_SHIFT 1 3413#define cfg_mds_diags_MASK 0x00000001 3414#define cfg_mds_diags_WORD word19 3415#define cfg_nvme_SHIFT 3 3416#define cfg_nvme_MASK 0x00000001 3417#define cfg_nvme_WORD word19 3418#define cfg_xib_SHIFT 4 3419#define cfg_xib_MASK 0x00000001 3420#define cfg_xib_WORD word19 3421#define cfg_xpsgl_SHIFT 6 3422#define cfg_xpsgl_MASK 0x00000001 3423#define cfg_xpsgl_WORD word19 3424#define cfg_eqdr_SHIFT 8 3425#define cfg_eqdr_MASK 0x00000001 3426#define cfg_eqdr_WORD word19 3427#define cfg_nosr_SHIFT 9 3428#define cfg_nosr_MASK 0x00000001 3429#define cfg_nosr_WORD word19 3430#define cfg_bv1s_SHIFT 10 3431#define cfg_bv1s_MASK 0x00000001 3432#define cfg_bv1s_WORD word19 3433 3434#define cfg_nsler_SHIFT 12 3435#define cfg_nsler_MASK 0x00000001 3436#define cfg_nsler_WORD word19 3437#define cfg_pvl_SHIFT 13 3438#define cfg_pvl_MASK 0x00000001 3439#define cfg_pvl_WORD word19 3440 3441#define cfg_pbde_SHIFT 20 3442#define cfg_pbde_MASK 0x00000001 3443#define cfg_pbde_WORD word19 3444 3445 uint32_t word20; 3446#define cfg_max_tow_xri_SHIFT 0 3447#define cfg_max_tow_xri_MASK 0x0000ffff 3448#define cfg_max_tow_xri_WORD word20 3449 3450 uint32_t word21; 3451#define cfg_mi_ver_SHIFT 0 3452#define cfg_mi_ver_MASK 0x0000ffff 3453#define cfg_mi_ver_WORD word21 3454#define cfg_cmf_SHIFT 24 3455#define cfg_cmf_MASK 0x000000ff 3456#define cfg_cmf_WORD word21 3457 3458 uint32_t mib_size; 3459 uint32_t word23; /* RESERVED */ 3460 3461 uint32_t word24; 3462#define cfg_frag_field_offset_SHIFT 0 3463#define cfg_frag_field_offset_MASK 0x0000ffff 3464#define cfg_frag_field_offset_WORD word24 3465 3466#define cfg_frag_field_size_SHIFT 16 3467#define cfg_frag_field_size_MASK 0x0000ffff 3468#define cfg_frag_field_size_WORD word24 3469 3470 uint32_t word25; 3471#define cfg_sgl_field_offset_SHIFT 0 3472#define cfg_sgl_field_offset_MASK 0x0000ffff 3473#define cfg_sgl_field_offset_WORD word25 3474 3475#define cfg_sgl_field_size_SHIFT 16 3476#define cfg_sgl_field_size_MASK 0x0000ffff 3477#define cfg_sgl_field_size_WORD word25 3478 3479 uint32_t word26; /* Chain SGE initial value LOW */ 3480 uint32_t word27; /* Chain SGE initial value HIGH */ 3481#define LPFC_NODELAY_MAX_IO 32 3482}; 3483 3484#define LPFC_SET_UE_RECOVERY 0x10 3485#define LPFC_SET_MDS_DIAGS 0x12 3486#define LPFC_SET_CGN_SIGNAL 0x1f 3487#define LPFC_SET_DUAL_DUMP 0x1e 3488#define LPFC_SET_ENABLE_MI 0x21 3489#define LPFC_SET_ENABLE_CMF 0x24 3490struct lpfc_mbx_set_feature { 3491 struct mbox_header header; 3492 uint32_t feature; 3493 uint32_t param_len; 3494 uint32_t word6; 3495#define lpfc_mbx_set_feature_UER_SHIFT 0 3496#define lpfc_mbx_set_feature_UER_MASK 0x00000001 3497#define lpfc_mbx_set_feature_UER_WORD word6 3498#define lpfc_mbx_set_feature_mds_SHIFT 2 3499#define lpfc_mbx_set_feature_mds_MASK 0x00000001 3500#define lpfc_mbx_set_feature_mds_WORD word6 3501#define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3502#define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3503#define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3504#define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0 3505#define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff 3506#define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6 3507#define lpfc_mbx_set_feature_dd_SHIFT 0 3508#define lpfc_mbx_set_feature_dd_MASK 0x00000001 3509#define lpfc_mbx_set_feature_dd_WORD word6 3510#define lpfc_mbx_set_feature_ddquery_SHIFT 1 3511#define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3512#define lpfc_mbx_set_feature_ddquery_WORD word6 3513#define LPFC_DISABLE_DUAL_DUMP 0 3514#define LPFC_ENABLE_DUAL_DUMP 1 3515#define LPFC_QUERY_OP_DUAL_DUMP 2 3516#define lpfc_mbx_set_feature_cmf_SHIFT 0 3517#define lpfc_mbx_set_feature_cmf_MASK 0x00000001 3518#define lpfc_mbx_set_feature_cmf_WORD word6 3519#define lpfc_mbx_set_feature_mi_SHIFT 0 3520#define lpfc_mbx_set_feature_mi_MASK 0x0000ffff 3521#define lpfc_mbx_set_feature_mi_WORD word6 3522#define lpfc_mbx_set_feature_milunq_SHIFT 16 3523#define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff 3524#define lpfc_mbx_set_feature_milunq_WORD word6 3525 uint32_t word7; 3526#define lpfc_mbx_set_feature_UERP_SHIFT 0 3527#define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3528#define lpfc_mbx_set_feature_UERP_WORD word7 3529#define lpfc_mbx_set_feature_UESR_SHIFT 16 3530#define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3531#define lpfc_mbx_set_feature_UESR_WORD word7 3532#define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0 3533#define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff 3534#define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7 3535 u32 word8; 3536#define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0 3537#define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff 3538#define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8 3539}; 3540 3541 3542#define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3543#define LPFC_SET_HOST_DATE_TIME 0x4 3544 3545struct lpfc_mbx_set_host_date_time { 3546 uint32_t word6; 3547#define lpfc_mbx_set_host_month_WORD word6 3548#define lpfc_mbx_set_host_month_SHIFT 16 3549#define lpfc_mbx_set_host_month_MASK 0xFF 3550#define lpfc_mbx_set_host_day_WORD word6 3551#define lpfc_mbx_set_host_day_SHIFT 8 3552#define lpfc_mbx_set_host_day_MASK 0xFF 3553#define lpfc_mbx_set_host_year_WORD word6 3554#define lpfc_mbx_set_host_year_SHIFT 0 3555#define lpfc_mbx_set_host_year_MASK 0xFF 3556 uint32_t word7; 3557#define lpfc_mbx_set_host_hour_WORD word7 3558#define lpfc_mbx_set_host_hour_SHIFT 16 3559#define lpfc_mbx_set_host_hour_MASK 0xFF 3560#define lpfc_mbx_set_host_min_WORD word7 3561#define lpfc_mbx_set_host_min_SHIFT 8 3562#define lpfc_mbx_set_host_min_MASK 0xFF 3563#define lpfc_mbx_set_host_sec_WORD word7 3564#define lpfc_mbx_set_host_sec_SHIFT 0 3565#define lpfc_mbx_set_host_sec_MASK 0xFF 3566}; 3567 3568struct lpfc_mbx_set_host_data { 3569#define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3570 struct mbox_header header; 3571 uint32_t param_id; 3572 uint32_t param_len; 3573 union { 3574 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3575 struct lpfc_mbx_set_host_date_time tm; 3576 } un; 3577}; 3578 3579struct lpfc_mbx_set_trunk_mode { 3580 struct mbox_header header; 3581 uint32_t word0; 3582#define lpfc_mbx_set_trunk_mode_WORD word0 3583#define lpfc_mbx_set_trunk_mode_SHIFT 0 3584#define lpfc_mbx_set_trunk_mode_MASK 0xFF 3585 uint32_t word1; 3586 uint32_t word2; 3587}; 3588 3589struct lpfc_mbx_get_sli4_parameters { 3590 struct mbox_header header; 3591 struct lpfc_sli4_parameters sli4_parameters; 3592}; 3593 3594struct lpfc_mbx_reg_congestion_buf { 3595 struct mbox_header header; 3596 uint32_t word0; 3597#define lpfc_mbx_reg_cgn_buf_type_WORD word0 3598#define lpfc_mbx_reg_cgn_buf_type_SHIFT 0 3599#define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF 3600#define lpfc_mbx_reg_cgn_buf_cnt_WORD word0 3601#define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16 3602#define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF 3603 uint32_t word1; 3604 uint32_t length; 3605 uint32_t addr_lo; 3606 uint32_t addr_hi; 3607}; 3608 3609struct lpfc_rscr_desc_generic { 3610#define LPFC_RSRC_DESC_WSIZE 22 3611 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3612}; 3613 3614struct lpfc_rsrc_desc_pcie { 3615 uint32_t word0; 3616#define lpfc_rsrc_desc_pcie_type_SHIFT 0 3617#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3618#define lpfc_rsrc_desc_pcie_type_WORD word0 3619#define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3620#define lpfc_rsrc_desc_pcie_length_SHIFT 8 3621#define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3622#define lpfc_rsrc_desc_pcie_length_WORD word0 3623 uint32_t word1; 3624#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3625#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3626#define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3627 uint32_t reserved; 3628 uint32_t word3; 3629#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3630#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3631#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3632#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3633#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3634#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3635#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3636#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3637#define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3638 uint32_t word4; 3639#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3640#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3641#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3642}; 3643 3644struct lpfc_rsrc_desc_fcfcoe { 3645 uint32_t word0; 3646#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3647#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3648#define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3649#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3650#define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3651#define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3652#define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3653#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3654#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3655#define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3656 uint32_t word1; 3657#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3658#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3659#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3660#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3661#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3662#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3663 uint32_t word2; 3664#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3665#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3666#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3667#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3668#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3669#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3670 uint32_t word3; 3671#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3672#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3673#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3674#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3675#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3676#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3677 uint32_t word4; 3678#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3679#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3680#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3681#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3682#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3683#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3684 uint32_t word5; 3685#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3686#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3687#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3688#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3689#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3690#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3691 uint32_t word6; 3692 uint32_t word7; 3693 uint32_t word8; 3694 uint32_t word9; 3695 uint32_t word10; 3696 uint32_t word11; 3697 uint32_t word12; 3698 uint32_t word13; 3699#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3700#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3701#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3702#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3703#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3704#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3705#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3706#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3707#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3708#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3709#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3710#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3711#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3712#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3713#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3714/* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3715 uint32_t bw_min; 3716 uint32_t bw_max; 3717 uint32_t iops_min; 3718 uint32_t iops_max; 3719 uint32_t reserved[4]; 3720}; 3721 3722struct lpfc_func_cfg { 3723#define LPFC_RSRC_DESC_MAX_NUM 2 3724 uint32_t rsrc_desc_count; 3725 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3726}; 3727 3728struct lpfc_mbx_get_func_cfg { 3729 struct mbox_header header; 3730#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3731#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3732#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3733 struct lpfc_func_cfg func_cfg; 3734}; 3735 3736struct lpfc_prof_cfg { 3737#define LPFC_RSRC_DESC_MAX_NUM 2 3738 uint32_t rsrc_desc_count; 3739 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3740}; 3741 3742struct lpfc_mbx_get_prof_cfg { 3743 struct mbox_header header; 3744#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3745#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3746#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3747 union { 3748 struct { 3749 uint32_t word10; 3750#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3751#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3752#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3753#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3754#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3755#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3756 } request; 3757 struct { 3758 struct lpfc_prof_cfg prof_cfg; 3759 } response; 3760 } u; 3761}; 3762 3763struct lpfc_controller_attribute { 3764 uint32_t version_string[8]; 3765 uint32_t manufacturer_name[8]; 3766 uint32_t supported_modes; 3767 uint32_t word17; 3768#define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3769#define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3770#define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3771#define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3772#define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3773#define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3774#define lpfc_cntl_attr_flash_id_SHIFT 16 3775#define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3776#define lpfc_cntl_attr_flash_id_WORD word17 3777 uint32_t mbx_da_struct_ver; 3778 uint32_t ep_fw_da_struct_ver; 3779 uint32_t ncsi_ver_str[3]; 3780 uint32_t dflt_ext_timeout; 3781 uint32_t model_number[8]; 3782 uint32_t description[16]; 3783 uint32_t serial_number[8]; 3784 uint32_t ip_ver_str[8]; 3785 uint32_t fw_ver_str[8]; 3786 uint32_t bios_ver_str[8]; 3787 uint32_t redboot_ver_str[8]; 3788 uint32_t driver_ver_str[8]; 3789 uint32_t flash_fw_ver_str[8]; 3790 uint32_t functionality; 3791 uint32_t word105; 3792#define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3793#define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3794#define lpfc_cntl_attr_max_cbd_len_WORD word105 3795#define lpfc_cntl_attr_asic_rev_SHIFT 16 3796#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3797#define lpfc_cntl_attr_asic_rev_WORD word105 3798#define lpfc_cntl_attr_gen_guid0_SHIFT 24 3799#define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3800#define lpfc_cntl_attr_gen_guid0_WORD word105 3801 uint32_t gen_guid1_12[3]; 3802 uint32_t word109; 3803#define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3804#define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3805#define lpfc_cntl_attr_gen_guid13_14_WORD word109 3806#define lpfc_cntl_attr_gen_guid15_SHIFT 16 3807#define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3808#define lpfc_cntl_attr_gen_guid15_WORD word109 3809#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3810#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3811#define lpfc_cntl_attr_hba_port_cnt_WORD word109 3812 uint32_t word110; 3813#define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3814#define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3815#define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3816#define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3817#define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3818#define lpfc_cntl_attr_multi_func_dev_WORD word110 3819 uint32_t word111; 3820#define lpfc_cntl_attr_cache_valid_SHIFT 0 3821#define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3822#define lpfc_cntl_attr_cache_valid_WORD word111 3823#define lpfc_cntl_attr_hba_status_SHIFT 8 3824#define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3825#define lpfc_cntl_attr_hba_status_WORD word111 3826#define lpfc_cntl_attr_max_domain_SHIFT 16 3827#define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3828#define lpfc_cntl_attr_max_domain_WORD word111 3829#define lpfc_cntl_attr_lnk_numb_SHIFT 24 3830#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3831#define lpfc_cntl_attr_lnk_numb_WORD word111 3832#define lpfc_cntl_attr_lnk_type_SHIFT 30 3833#define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3834#define lpfc_cntl_attr_lnk_type_WORD word111 3835 uint32_t fw_post_status; 3836 uint32_t hba_mtu[8]; 3837 uint32_t word121; 3838 uint32_t reserved1[3]; 3839 uint32_t word125; 3840#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3841#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3842#define lpfc_cntl_attr_pci_vendor_id_WORD word125 3843#define lpfc_cntl_attr_pci_device_id_SHIFT 16 3844#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3845#define lpfc_cntl_attr_pci_device_id_WORD word125 3846 uint32_t word126; 3847#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3848#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3849#define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3850#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3851#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3852#define lpfc_cntl_attr_pci_subsys_id_WORD word126 3853 uint32_t word127; 3854#define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3855#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3856#define lpfc_cntl_attr_pci_bus_num_WORD word127 3857#define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3858#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3859#define lpfc_cntl_attr_pci_dev_num_WORD word127 3860#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3861#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3862#define lpfc_cntl_attr_pci_fnc_num_WORD word127 3863#define lpfc_cntl_attr_inf_type_SHIFT 24 3864#define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3865#define lpfc_cntl_attr_inf_type_WORD word127 3866 uint32_t unique_id[2]; 3867 uint32_t word130; 3868#define lpfc_cntl_attr_num_netfil_SHIFT 0 3869#define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3870#define lpfc_cntl_attr_num_netfil_WORD word130 3871 uint32_t reserved2[4]; 3872}; 3873 3874struct lpfc_mbx_get_cntl_attributes { 3875 union lpfc_sli4_cfg_shdr cfg_shdr; 3876 struct lpfc_controller_attribute cntl_attr; 3877}; 3878 3879struct lpfc_mbx_get_port_name { 3880 struct mbox_header header; 3881 union { 3882 struct { 3883 uint32_t word4; 3884#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3885#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3886#define lpfc_mbx_get_port_name_lnk_type_WORD word4 3887 } request; 3888 struct { 3889 uint32_t word4; 3890#define lpfc_mbx_get_port_name_name0_SHIFT 0 3891#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3892#define lpfc_mbx_get_port_name_name0_WORD word4 3893#define lpfc_mbx_get_port_name_name1_SHIFT 8 3894#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3895#define lpfc_mbx_get_port_name_name1_WORD word4 3896#define lpfc_mbx_get_port_name_name2_SHIFT 16 3897#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3898#define lpfc_mbx_get_port_name_name2_WORD word4 3899#define lpfc_mbx_get_port_name_name3_SHIFT 24 3900#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3901#define lpfc_mbx_get_port_name_name3_WORD word4 3902#define LPFC_LINK_NUMBER_0 0 3903#define LPFC_LINK_NUMBER_1 1 3904#define LPFC_LINK_NUMBER_2 2 3905#define LPFC_LINK_NUMBER_3 3 3906 } response; 3907 } u; 3908}; 3909 3910/* Mailbox Completion Queue Error Messages */ 3911#define MB_CQE_STATUS_SUCCESS 0x0 3912#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3913#define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3914#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3915#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3916#define MB_CQE_STATUS_DMA_FAILED 0x5 3917 3918 3919#define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3920struct lpfc_mbx_wr_object { 3921 struct mbox_header header; 3922 union { 3923 struct { 3924 uint32_t word4; 3925#define lpfc_wr_object_eof_SHIFT 31 3926#define lpfc_wr_object_eof_MASK 0x00000001 3927#define lpfc_wr_object_eof_WORD word4 3928#define lpfc_wr_object_eas_SHIFT 29 3929#define lpfc_wr_object_eas_MASK 0x00000001 3930#define lpfc_wr_object_eas_WORD word4 3931#define lpfc_wr_object_write_length_SHIFT 0 3932#define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3933#define lpfc_wr_object_write_length_WORD word4 3934 uint32_t write_offset; 3935 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 3936 uint32_t bde_count; 3937 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3938 } request; 3939 struct { 3940 uint32_t actual_write_length; 3941 uint32_t word5; 3942#define lpfc_wr_object_change_status_SHIFT 0 3943#define lpfc_wr_object_change_status_MASK 0x000000FF 3944#define lpfc_wr_object_change_status_WORD word5 3945#define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3946#define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3947#define LPFC_CHANGE_STATUS_FW_RESET 0x02 3948#define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3949#define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3950#define lpfc_wr_object_csf_SHIFT 8 3951#define lpfc_wr_object_csf_MASK 0x00000001 3952#define lpfc_wr_object_csf_WORD word5 3953 } response; 3954 } u; 3955}; 3956 3957/* mailbox queue entry structure */ 3958struct lpfc_mqe { 3959 uint32_t word0; 3960#define lpfc_mqe_status_SHIFT 16 3961#define lpfc_mqe_status_MASK 0x0000FFFF 3962#define lpfc_mqe_status_WORD word0 3963#define lpfc_mqe_command_SHIFT 8 3964#define lpfc_mqe_command_MASK 0x000000FF 3965#define lpfc_mqe_command_WORD word0 3966 union { 3967 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3968 /* sli4 mailbox commands */ 3969 struct lpfc_mbx_sli4_config sli4_config; 3970 struct lpfc_mbx_init_vfi init_vfi; 3971 struct lpfc_mbx_reg_vfi reg_vfi; 3972 struct lpfc_mbx_reg_vfi unreg_vfi; 3973 struct lpfc_mbx_init_vpi init_vpi; 3974 struct lpfc_mbx_resume_rpi resume_rpi; 3975 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3976 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3977 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3978 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3979 struct lpfc_mbx_reg_fcfi reg_fcfi; 3980 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3981 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3982 struct lpfc_mbx_mq_create mq_create; 3983 struct lpfc_mbx_mq_create_ext mq_create_ext; 3984 struct lpfc_mbx_read_object read_object; 3985 struct lpfc_mbx_eq_create eq_create; 3986 struct lpfc_mbx_modify_eq_delay eq_delay; 3987 struct lpfc_mbx_cq_create cq_create; 3988 struct lpfc_mbx_cq_create_set cq_create_set; 3989 struct lpfc_mbx_wq_create wq_create; 3990 struct lpfc_mbx_rq_create rq_create; 3991 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3992 struct lpfc_mbx_mq_destroy mq_destroy; 3993 struct lpfc_mbx_eq_destroy eq_destroy; 3994 struct lpfc_mbx_cq_destroy cq_destroy; 3995 struct lpfc_mbx_wq_destroy wq_destroy; 3996 struct lpfc_mbx_rq_destroy rq_destroy; 3997 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3998 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3999 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 4000 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 4001 struct lpfc_mbx_nembed_cmd nembed_cmd; 4002 struct lpfc_mbx_read_rev read_rev; 4003 struct lpfc_mbx_read_vpi read_vpi; 4004 struct lpfc_mbx_read_config rd_config; 4005 struct lpfc_mbx_request_features req_ftrs; 4006 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 4007 struct lpfc_mbx_query_fw_config query_fw_cfg; 4008 struct lpfc_mbx_set_beacon_config beacon_config; 4009 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 4010 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf; 4011 struct lpfc_mbx_set_link_diag_state link_diag_state; 4012 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 4013 struct lpfc_mbx_run_link_diag_test link_diag_test; 4014 struct lpfc_mbx_get_func_cfg get_func_cfg; 4015 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 4016 struct lpfc_mbx_wr_object wr_object; 4017 struct lpfc_mbx_get_port_name get_port_name; 4018 struct lpfc_mbx_set_feature set_feature; 4019 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 4020 struct lpfc_mbx_set_host_data set_host_data; 4021 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 4022 struct lpfc_mbx_nop nop; 4023 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 4024 } un; 4025}; 4026 4027struct lpfc_mcqe { 4028 uint32_t word0; 4029#define lpfc_mcqe_status_SHIFT 0 4030#define lpfc_mcqe_status_MASK 0x0000FFFF 4031#define lpfc_mcqe_status_WORD word0 4032#define lpfc_mcqe_ext_status_SHIFT 16 4033#define lpfc_mcqe_ext_status_MASK 0x0000FFFF 4034#define lpfc_mcqe_ext_status_WORD word0 4035 uint32_t mcqe_tag0; 4036 uint32_t mcqe_tag1; 4037 uint32_t trailer; 4038#define lpfc_trailer_valid_SHIFT 31 4039#define lpfc_trailer_valid_MASK 0x00000001 4040#define lpfc_trailer_valid_WORD trailer 4041#define lpfc_trailer_async_SHIFT 30 4042#define lpfc_trailer_async_MASK 0x00000001 4043#define lpfc_trailer_async_WORD trailer 4044#define lpfc_trailer_hpi_SHIFT 29 4045#define lpfc_trailer_hpi_MASK 0x00000001 4046#define lpfc_trailer_hpi_WORD trailer 4047#define lpfc_trailer_completed_SHIFT 28 4048#define lpfc_trailer_completed_MASK 0x00000001 4049#define lpfc_trailer_completed_WORD trailer 4050#define lpfc_trailer_consumed_SHIFT 27 4051#define lpfc_trailer_consumed_MASK 0x00000001 4052#define lpfc_trailer_consumed_WORD trailer 4053#define lpfc_trailer_type_SHIFT 16 4054#define lpfc_trailer_type_MASK 0x000000FF 4055#define lpfc_trailer_type_WORD trailer 4056#define lpfc_trailer_code_SHIFT 8 4057#define lpfc_trailer_code_MASK 0x000000FF 4058#define lpfc_trailer_code_WORD trailer 4059#define LPFC_TRAILER_CODE_LINK 0x1 4060#define LPFC_TRAILER_CODE_FCOE 0x2 4061#define LPFC_TRAILER_CODE_DCBX 0x3 4062#define LPFC_TRAILER_CODE_GRP5 0x5 4063#define LPFC_TRAILER_CODE_FC 0x10 4064#define LPFC_TRAILER_CODE_SLI 0x11 4065#define LPFC_TRAILER_CODE_CMSTAT 0x13 4066}; 4067 4068struct lpfc_acqe_link { 4069 uint32_t word0; 4070#define lpfc_acqe_link_speed_SHIFT 24 4071#define lpfc_acqe_link_speed_MASK 0x000000FF 4072#define lpfc_acqe_link_speed_WORD word0 4073#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4074#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4075#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4076#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4077#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4078#define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4079#define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4080#define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4081#define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4082#define lpfc_acqe_link_duplex_SHIFT 16 4083#define lpfc_acqe_link_duplex_MASK 0x000000FF 4084#define lpfc_acqe_link_duplex_WORD word0 4085#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4086#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4087#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4088#define lpfc_acqe_link_status_SHIFT 8 4089#define lpfc_acqe_link_status_MASK 0x000000FF 4090#define lpfc_acqe_link_status_WORD word0 4091#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4092#define LPFC_ASYNC_LINK_STATUS_UP 0x1 4093#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4094#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4095#define lpfc_acqe_link_type_SHIFT 6 4096#define lpfc_acqe_link_type_MASK 0x00000003 4097#define lpfc_acqe_link_type_WORD word0 4098#define lpfc_acqe_link_number_SHIFT 0 4099#define lpfc_acqe_link_number_MASK 0x0000003F 4100#define lpfc_acqe_link_number_WORD word0 4101 uint32_t word1; 4102#define lpfc_acqe_link_fault_SHIFT 0 4103#define lpfc_acqe_link_fault_MASK 0x000000FF 4104#define lpfc_acqe_link_fault_WORD word1 4105#define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4106#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4107#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4108#define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4109#define lpfc_acqe_logical_link_speed_SHIFT 16 4110#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4111#define lpfc_acqe_logical_link_speed_WORD word1 4112 uint32_t event_tag; 4113 uint32_t trailer; 4114#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4115#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4116}; 4117 4118struct lpfc_acqe_fip { 4119 uint32_t index; 4120 uint32_t word1; 4121#define lpfc_acqe_fip_fcf_count_SHIFT 0 4122#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4123#define lpfc_acqe_fip_fcf_count_WORD word1 4124#define lpfc_acqe_fip_event_type_SHIFT 16 4125#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4126#define lpfc_acqe_fip_event_type_WORD word1 4127 uint32_t event_tag; 4128 uint32_t trailer; 4129#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4130#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4131#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4132#define LPFC_FIP_EVENT_TYPE_CVL 0x4 4133#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4134}; 4135 4136struct lpfc_acqe_dcbx { 4137 uint32_t tlv_ttl; 4138 uint32_t reserved; 4139 uint32_t event_tag; 4140 uint32_t trailer; 4141}; 4142 4143struct lpfc_acqe_grp5 { 4144 uint32_t word0; 4145#define lpfc_acqe_grp5_type_SHIFT 6 4146#define lpfc_acqe_grp5_type_MASK 0x00000003 4147#define lpfc_acqe_grp5_type_WORD word0 4148#define lpfc_acqe_grp5_number_SHIFT 0 4149#define lpfc_acqe_grp5_number_MASK 0x0000003F 4150#define lpfc_acqe_grp5_number_WORD word0 4151 uint32_t word1; 4152#define lpfc_acqe_grp5_llink_spd_SHIFT 16 4153#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4154#define lpfc_acqe_grp5_llink_spd_WORD word1 4155 uint32_t event_tag; 4156 uint32_t trailer; 4157}; 4158 4159extern const char *const trunk_errmsg[]; 4160 4161struct lpfc_acqe_fc_la { 4162 uint32_t word0; 4163#define lpfc_acqe_fc_la_speed_SHIFT 24 4164#define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4165#define lpfc_acqe_fc_la_speed_WORD word0 4166#define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4167#define LPFC_FC_LA_SPEED_1G 0x1 4168#define LPFC_FC_LA_SPEED_2G 0x2 4169#define LPFC_FC_LA_SPEED_4G 0x4 4170#define LPFC_FC_LA_SPEED_8G 0x8 4171#define LPFC_FC_LA_SPEED_10G 0xA 4172#define LPFC_FC_LA_SPEED_16G 0x10 4173#define LPFC_FC_LA_SPEED_32G 0x20 4174#define LPFC_FC_LA_SPEED_64G 0x21 4175#define LPFC_FC_LA_SPEED_128G 0x22 4176#define LPFC_FC_LA_SPEED_256G 0x23 4177#define lpfc_acqe_fc_la_topology_SHIFT 16 4178#define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4179#define lpfc_acqe_fc_la_topology_WORD word0 4180#define LPFC_FC_LA_TOP_UNKOWN 0x0 4181#define LPFC_FC_LA_TOP_P2P 0x1 4182#define LPFC_FC_LA_TOP_FCAL 0x2 4183#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4184#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4185#define lpfc_acqe_fc_la_att_type_SHIFT 8 4186#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4187#define lpfc_acqe_fc_la_att_type_WORD word0 4188#define LPFC_FC_LA_TYPE_LINK_UP 0x1 4189#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4190#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4191#define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4192#define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4193#define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4194#define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4195#define lpfc_acqe_fc_la_port_type_SHIFT 6 4196#define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4197#define lpfc_acqe_fc_la_port_type_WORD word0 4198#define LPFC_LINK_TYPE_ETHERNET 0x0 4199#define LPFC_LINK_TYPE_FC 0x1 4200#define lpfc_acqe_fc_la_port_number_SHIFT 0 4201#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4202#define lpfc_acqe_fc_la_port_number_WORD word0 4203 4204/* Attention Type is 0x07 (Trunking Event) word0 */ 4205#define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4206#define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4207#define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4208#define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4209#define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4210#define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4211#define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4212#define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4213#define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4214#define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4215#define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4216#define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4217#define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4218#define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4219#define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4220#define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4221#define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4222#define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4223#define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4224#define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4225#define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4226#define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4227#define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4228#define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4229 uint32_t word1; 4230#define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4231#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4232#define lpfc_acqe_fc_la_llink_spd_WORD word1 4233#define lpfc_acqe_fc_la_fault_SHIFT 0 4234#define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4235#define lpfc_acqe_fc_la_fault_WORD word1 4236#define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4237#define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4238#define lpfc_acqe_fc_la_trunk_fault_WORD word1 4239#define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4240#define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4241#define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4242#define LPFC_FC_LA_FAULT_NONE 0x0 4243#define LPFC_FC_LA_FAULT_LOCAL 0x1 4244#define LPFC_FC_LA_FAULT_REMOTE 0x2 4245 uint32_t event_tag; 4246 uint32_t trailer; 4247#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4248#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4249}; 4250 4251struct lpfc_acqe_misconfigured_event { 4252 struct { 4253 uint32_t word0; 4254#define lpfc_sli_misconfigured_port0_state_SHIFT 0 4255#define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4256#define lpfc_sli_misconfigured_port0_state_WORD word0 4257#define lpfc_sli_misconfigured_port1_state_SHIFT 8 4258#define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4259#define lpfc_sli_misconfigured_port1_state_WORD word0 4260#define lpfc_sli_misconfigured_port2_state_SHIFT 16 4261#define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4262#define lpfc_sli_misconfigured_port2_state_WORD word0 4263#define lpfc_sli_misconfigured_port3_state_SHIFT 24 4264#define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4265#define lpfc_sli_misconfigured_port3_state_WORD word0 4266 uint32_t word1; 4267#define lpfc_sli_misconfigured_port0_op_SHIFT 0 4268#define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4269#define lpfc_sli_misconfigured_port0_op_WORD word1 4270#define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4271#define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4272#define lpfc_sli_misconfigured_port0_severity_WORD word1 4273#define lpfc_sli_misconfigured_port1_op_SHIFT 8 4274#define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4275#define lpfc_sli_misconfigured_port1_op_WORD word1 4276#define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4277#define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4278#define lpfc_sli_misconfigured_port1_severity_WORD word1 4279#define lpfc_sli_misconfigured_port2_op_SHIFT 16 4280#define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4281#define lpfc_sli_misconfigured_port2_op_WORD word1 4282#define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4283#define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4284#define lpfc_sli_misconfigured_port2_severity_WORD word1 4285#define lpfc_sli_misconfigured_port3_op_SHIFT 24 4286#define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4287#define lpfc_sli_misconfigured_port3_op_WORD word1 4288#define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4289#define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4290#define lpfc_sli_misconfigured_port3_severity_WORD word1 4291 } theEvent; 4292#define LPFC_SLI_EVENT_STATUS_VALID 0x00 4293#define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4294#define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4295#define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4296#define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4297#define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4298}; 4299 4300struct lpfc_acqe_cgn_signal { 4301 u32 word0; 4302#define lpfc_warn_acqe_SHIFT 0 4303#define lpfc_warn_acqe_MASK 0x7FFFFFFF 4304#define lpfc_warn_acqe_WORD word0 4305#define lpfc_imm_acqe_SHIFT 31 4306#define lpfc_imm_acqe_MASK 0x1 4307#define lpfc_imm_acqe_WORD word0 4308 u32 alarm_cnt; 4309 u32 word2; 4310 u32 trailer; 4311}; 4312 4313struct lpfc_acqe_sli { 4314 uint32_t event_data1; 4315 uint32_t event_data2; 4316 uint32_t reserved; 4317 uint32_t trailer; 4318#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4319#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4320#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4321#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4322#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4323#define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4324#define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4325#define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE 4326#define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4327#define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4328#define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11 4329}; 4330 4331/* 4332 * Define the bootstrap mailbox (bmbx) region used to communicate 4333 * mailbox command between the host and port. The mailbox consists 4334 * of a payload area of 256 bytes and a completion queue of length 4335 * 16 bytes. 4336 */ 4337struct lpfc_bmbx_create { 4338 struct lpfc_mqe mqe; 4339 struct lpfc_mcqe mcqe; 4340}; 4341 4342#define SGL_ALIGN_SZ 64 4343#define SGL_PAGE_SIZE 4096 4344/* align SGL addr on a size boundary - adjust address up */ 4345#define NO_XRI 0xffff 4346 4347struct wqe_common { 4348 uint32_t word6; 4349#define wqe_xri_tag_SHIFT 0 4350#define wqe_xri_tag_MASK 0x0000FFFF 4351#define wqe_xri_tag_WORD word6 4352#define wqe_ctxt_tag_SHIFT 16 4353#define wqe_ctxt_tag_MASK 0x0000FFFF 4354#define wqe_ctxt_tag_WORD word6 4355 uint32_t word7; 4356#define wqe_dif_SHIFT 0 4357#define wqe_dif_MASK 0x00000003 4358#define wqe_dif_WORD word7 4359#define LPFC_WQE_DIF_PASSTHRU 1 4360#define LPFC_WQE_DIF_STRIP 2 4361#define LPFC_WQE_DIF_INSERT 3 4362#define wqe_ct_SHIFT 2 4363#define wqe_ct_MASK 0x00000003 4364#define wqe_ct_WORD word7 4365#define wqe_status_SHIFT 4 4366#define wqe_status_MASK 0x0000000f 4367#define wqe_status_WORD word7 4368#define wqe_cmnd_SHIFT 8 4369#define wqe_cmnd_MASK 0x000000ff 4370#define wqe_cmnd_WORD word7 4371#define wqe_class_SHIFT 16 4372#define wqe_class_MASK 0x00000007 4373#define wqe_class_WORD word7 4374#define wqe_ar_SHIFT 19 4375#define wqe_ar_MASK 0x00000001 4376#define wqe_ar_WORD word7 4377#define wqe_ag_SHIFT wqe_ar_SHIFT 4378#define wqe_ag_MASK wqe_ar_MASK 4379#define wqe_ag_WORD wqe_ar_WORD 4380#define wqe_pu_SHIFT 20 4381#define wqe_pu_MASK 0x00000003 4382#define wqe_pu_WORD word7 4383#define wqe_erp_SHIFT 22 4384#define wqe_erp_MASK 0x00000001 4385#define wqe_erp_WORD word7 4386#define wqe_conf_SHIFT wqe_erp_SHIFT 4387#define wqe_conf_MASK wqe_erp_MASK 4388#define wqe_conf_WORD wqe_erp_WORD 4389#define wqe_lnk_SHIFT 23 4390#define wqe_lnk_MASK 0x00000001 4391#define wqe_lnk_WORD word7 4392#define wqe_tmo_SHIFT 24 4393#define wqe_tmo_MASK 0x000000ff 4394#define wqe_tmo_WORD word7 4395 uint32_t abort_tag; /* word 8 in WQE */ 4396 uint32_t word9; 4397#define wqe_reqtag_SHIFT 0 4398#define wqe_reqtag_MASK 0x0000FFFF 4399#define wqe_reqtag_WORD word9 4400#define wqe_temp_rpi_SHIFT 16 4401#define wqe_temp_rpi_MASK 0x0000FFFF 4402#define wqe_temp_rpi_WORD word9 4403#define wqe_rcvoxid_SHIFT 16 4404#define wqe_rcvoxid_MASK 0x0000FFFF 4405#define wqe_rcvoxid_WORD word9 4406#define wqe_sof_SHIFT 24 4407#define wqe_sof_MASK 0x000000FF 4408#define wqe_sof_WORD word9 4409#define wqe_eof_SHIFT 16 4410#define wqe_eof_MASK 0x000000FF 4411#define wqe_eof_WORD word9 4412 uint32_t word10; 4413#define wqe_ebde_cnt_SHIFT 0 4414#define wqe_ebde_cnt_MASK 0x0000000f 4415#define wqe_ebde_cnt_WORD word10 4416#define wqe_xchg_SHIFT 4 4417#define wqe_xchg_MASK 0x00000001 4418#define wqe_xchg_WORD word10 4419#define LPFC_SCSI_XCHG 0x0 4420#define LPFC_NVME_XCHG 0x1 4421#define wqe_appid_SHIFT 5 4422#define wqe_appid_MASK 0x00000001 4423#define wqe_appid_WORD word10 4424#define wqe_oas_SHIFT 6 4425#define wqe_oas_MASK 0x00000001 4426#define wqe_oas_WORD word10 4427#define wqe_lenloc_SHIFT 7 4428#define wqe_lenloc_MASK 0x00000003 4429#define wqe_lenloc_WORD word10 4430#define LPFC_WQE_LENLOC_NONE 0 4431#define LPFC_WQE_LENLOC_WORD3 1 4432#define LPFC_WQE_LENLOC_WORD12 2 4433#define LPFC_WQE_LENLOC_WORD4 3 4434#define wqe_qosd_SHIFT 9 4435#define wqe_qosd_MASK 0x00000001 4436#define wqe_qosd_WORD word10 4437#define wqe_xbl_SHIFT 11 4438#define wqe_xbl_MASK 0x00000001 4439#define wqe_xbl_WORD word10 4440#define wqe_iod_SHIFT 13 4441#define wqe_iod_MASK 0x00000001 4442#define wqe_iod_WORD word10 4443#define LPFC_WQE_IOD_NONE 0 4444#define LPFC_WQE_IOD_WRITE 0 4445#define LPFC_WQE_IOD_READ 1 4446#define wqe_dbde_SHIFT 14 4447#define wqe_dbde_MASK 0x00000001 4448#define wqe_dbde_WORD word10 4449#define wqe_wqes_SHIFT 15 4450#define wqe_wqes_MASK 0x00000001 4451#define wqe_wqes_WORD word10 4452/* Note that this field overlaps above fields */ 4453#define wqe_wqid_SHIFT 1 4454#define wqe_wqid_MASK 0x00007fff 4455#define wqe_wqid_WORD word10 4456#define wqe_pri_SHIFT 16 4457#define wqe_pri_MASK 0x00000007 4458#define wqe_pri_WORD word10 4459#define wqe_pv_SHIFT 19 4460#define wqe_pv_MASK 0x00000001 4461#define wqe_pv_WORD word10 4462#define wqe_xc_SHIFT 21 4463#define wqe_xc_MASK 0x00000001 4464#define wqe_xc_WORD word10 4465#define wqe_sr_SHIFT 22 4466#define wqe_sr_MASK 0x00000001 4467#define wqe_sr_WORD word10 4468#define wqe_ccpe_SHIFT 23 4469#define wqe_ccpe_MASK 0x00000001 4470#define wqe_ccpe_WORD word10 4471#define wqe_ccp_SHIFT 24 4472#define wqe_ccp_MASK 0x000000ff 4473#define wqe_ccp_WORD word10 4474 uint32_t word11; 4475#define wqe_cmd_type_SHIFT 0 4476#define wqe_cmd_type_MASK 0x0000000f 4477#define wqe_cmd_type_WORD word11 4478#define wqe_els_id_SHIFT 4 4479#define wqe_els_id_MASK 0x00000007 4480#define wqe_els_id_WORD word11 4481#define wqe_irsp_SHIFT 4 4482#define wqe_irsp_MASK 0x00000001 4483#define wqe_irsp_WORD word11 4484#define wqe_pbde_SHIFT 5 4485#define wqe_pbde_MASK 0x00000001 4486#define wqe_pbde_WORD word11 4487#define wqe_sup_SHIFT 6 4488#define wqe_sup_MASK 0x00000001 4489#define wqe_sup_WORD word11 4490#define wqe_ffrq_SHIFT 6 4491#define wqe_ffrq_MASK 0x00000001 4492#define wqe_ffrq_WORD word11 4493#define wqe_wqec_SHIFT 7 4494#define wqe_wqec_MASK 0x00000001 4495#define wqe_wqec_WORD word11 4496#define wqe_irsplen_SHIFT 8 4497#define wqe_irsplen_MASK 0x0000000f 4498#define wqe_irsplen_WORD word11 4499#define wqe_cqid_SHIFT 16 4500#define wqe_cqid_MASK 0x0000ffff 4501#define wqe_cqid_WORD word11 4502#define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4503}; 4504 4505struct wqe_did { 4506 uint32_t word5; 4507#define wqe_els_did_SHIFT 0 4508#define wqe_els_did_MASK 0x00FFFFFF 4509#define wqe_els_did_WORD word5 4510#define wqe_xmit_bls_pt_SHIFT 28 4511#define wqe_xmit_bls_pt_MASK 0x00000003 4512#define wqe_xmit_bls_pt_WORD word5 4513#define wqe_xmit_bls_ar_SHIFT 30 4514#define wqe_xmit_bls_ar_MASK 0x00000001 4515#define wqe_xmit_bls_ar_WORD word5 4516#define wqe_xmit_bls_xo_SHIFT 31 4517#define wqe_xmit_bls_xo_MASK 0x00000001 4518#define wqe_xmit_bls_xo_WORD word5 4519}; 4520 4521struct lpfc_wqe_generic{ 4522 struct ulp_bde64 bde; 4523 uint32_t word3; 4524 uint32_t word4; 4525 uint32_t word5; 4526 struct wqe_common wqe_com; 4527 uint32_t payload[4]; 4528}; 4529 4530enum els_request64_wqe_word11 { 4531 LPFC_ELS_ID_DEFAULT, 4532 LPFC_ELS_ID_LOGO, 4533 LPFC_ELS_ID_FDISC, 4534 LPFC_ELS_ID_FLOGI, 4535 LPFC_ELS_ID_PLOGI, 4536}; 4537 4538struct els_request64_wqe { 4539 struct ulp_bde64 bde; 4540 uint32_t payload_len; 4541 uint32_t word4; 4542#define els_req64_sid_SHIFT 0 4543#define els_req64_sid_MASK 0x00FFFFFF 4544#define els_req64_sid_WORD word4 4545#define els_req64_sp_SHIFT 24 4546#define els_req64_sp_MASK 0x00000001 4547#define els_req64_sp_WORD word4 4548#define els_req64_vf_SHIFT 25 4549#define els_req64_vf_MASK 0x00000001 4550#define els_req64_vf_WORD word4 4551 struct wqe_did wqe_dest; 4552 struct wqe_common wqe_com; /* words 6-11 */ 4553 uint32_t word12; 4554#define els_req64_vfid_SHIFT 1 4555#define els_req64_vfid_MASK 0x00000FFF 4556#define els_req64_vfid_WORD word12 4557#define els_req64_pri_SHIFT 13 4558#define els_req64_pri_MASK 0x00000007 4559#define els_req64_pri_WORD word12 4560 uint32_t word13; 4561#define els_req64_hopcnt_SHIFT 24 4562#define els_req64_hopcnt_MASK 0x000000ff 4563#define els_req64_hopcnt_WORD word13 4564 uint32_t word14; 4565 uint32_t max_response_payload_len; 4566}; 4567 4568struct xmit_els_rsp64_wqe { 4569 struct ulp_bde64 bde; 4570 uint32_t response_payload_len; 4571 uint32_t word4; 4572#define els_rsp64_sid_SHIFT 0 4573#define els_rsp64_sid_MASK 0x00FFFFFF 4574#define els_rsp64_sid_WORD word4 4575#define els_rsp64_sp_SHIFT 24 4576#define els_rsp64_sp_MASK 0x00000001 4577#define els_rsp64_sp_WORD word4 4578 struct wqe_did wqe_dest; 4579 struct wqe_common wqe_com; /* words 6-11 */ 4580 uint32_t word12; 4581#define wqe_rsp_temp_rpi_SHIFT 0 4582#define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4583#define wqe_rsp_temp_rpi_WORD word12 4584 uint32_t rsvd_13_15[3]; 4585}; 4586 4587struct xmit_bls_rsp64_wqe { 4588 uint32_t payload0; 4589/* Payload0 for BA_ACC */ 4590#define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4591#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4592#define xmit_bls_rsp64_acc_seq_id_WORD payload0 4593#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4594#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4595#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4596/* Payload0 for BA_RJT */ 4597#define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4598#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4599#define xmit_bls_rsp64_rjt_vspec_WORD payload0 4600#define xmit_bls_rsp64_rjt_expc_SHIFT 8 4601#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4602#define xmit_bls_rsp64_rjt_expc_WORD payload0 4603#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4604#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4605#define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4606 uint32_t word1; 4607#define xmit_bls_rsp64_rxid_SHIFT 0 4608#define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4609#define xmit_bls_rsp64_rxid_WORD word1 4610#define xmit_bls_rsp64_oxid_SHIFT 16 4611#define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4612#define xmit_bls_rsp64_oxid_WORD word1 4613 uint32_t word2; 4614#define xmit_bls_rsp64_seqcnthi_SHIFT 0 4615#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4616#define xmit_bls_rsp64_seqcnthi_WORD word2 4617#define xmit_bls_rsp64_seqcntlo_SHIFT 16 4618#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4619#define xmit_bls_rsp64_seqcntlo_WORD word2 4620 uint32_t rsrvd3; 4621 uint32_t rsrvd4; 4622 struct wqe_did wqe_dest; 4623 struct wqe_common wqe_com; /* words 6-11 */ 4624 uint32_t word12; 4625#define xmit_bls_rsp64_temprpi_SHIFT 0 4626#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4627#define xmit_bls_rsp64_temprpi_WORD word12 4628 uint32_t rsvd_13_15[3]; 4629}; 4630 4631struct wqe_rctl_dfctl { 4632 uint32_t word5; 4633#define wqe_si_SHIFT 2 4634#define wqe_si_MASK 0x000000001 4635#define wqe_si_WORD word5 4636#define wqe_la_SHIFT 3 4637#define wqe_la_MASK 0x000000001 4638#define wqe_la_WORD word5 4639#define wqe_xo_SHIFT 6 4640#define wqe_xo_MASK 0x000000001 4641#define wqe_xo_WORD word5 4642#define wqe_ls_SHIFT 7 4643#define wqe_ls_MASK 0x000000001 4644#define wqe_ls_WORD word5 4645#define wqe_dfctl_SHIFT 8 4646#define wqe_dfctl_MASK 0x0000000ff 4647#define wqe_dfctl_WORD word5 4648#define wqe_type_SHIFT 16 4649#define wqe_type_MASK 0x0000000ff 4650#define wqe_type_WORD word5 4651#define wqe_rctl_SHIFT 24 4652#define wqe_rctl_MASK 0x0000000ff 4653#define wqe_rctl_WORD word5 4654}; 4655 4656struct xmit_seq64_wqe { 4657 struct ulp_bde64 bde; 4658 uint32_t rsvd3; 4659 uint32_t relative_offset; 4660 struct wqe_rctl_dfctl wge_ctl; 4661 struct wqe_common wqe_com; /* words 6-11 */ 4662 uint32_t xmit_len; 4663 uint32_t rsvd_12_15[3]; 4664}; 4665struct xmit_bcast64_wqe { 4666 struct ulp_bde64 bde; 4667 uint32_t seq_payload_len; 4668 uint32_t rsvd4; 4669 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4670 struct wqe_common wqe_com; /* words 6-11 */ 4671 uint32_t rsvd_12_15[4]; 4672}; 4673 4674struct gen_req64_wqe { 4675 struct ulp_bde64 bde; 4676 uint32_t request_payload_len; 4677 uint32_t relative_offset; 4678 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4679 struct wqe_common wqe_com; /* words 6-11 */ 4680 uint32_t rsvd_12_14[3]; 4681 uint32_t max_response_payload_len; 4682}; 4683 4684/* Define NVME PRLI request to fabric. NVME is a 4685 * fabric-only protocol. 4686 * Updated to red-lined v1.08 on Sept 16, 2016 4687 */ 4688struct lpfc_nvme_prli { 4689 uint32_t word1; 4690 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4691#define prli_acc_rsp_code_SHIFT 8 4692#define prli_acc_rsp_code_MASK 0x0000000f 4693#define prli_acc_rsp_code_WORD word1 4694#define prli_estabImagePair_SHIFT 13 4695#define prli_estabImagePair_MASK 0x00000001 4696#define prli_estabImagePair_WORD word1 4697#define prli_type_code_ext_SHIFT 16 4698#define prli_type_code_ext_MASK 0x000000ff 4699#define prli_type_code_ext_WORD word1 4700#define prli_type_code_SHIFT 24 4701#define prli_type_code_MASK 0x000000ff 4702#define prli_type_code_WORD word1 4703 uint32_t word_rsvd2; 4704 uint32_t word_rsvd3; 4705 4706 uint32_t word4; 4707#define prli_fba_SHIFT 0 4708#define prli_fba_MASK 0x00000001 4709#define prli_fba_WORD word4 4710#define prli_disc_SHIFT 3 4711#define prli_disc_MASK 0x00000001 4712#define prli_disc_WORD word4 4713#define prli_tgt_SHIFT 4 4714#define prli_tgt_MASK 0x00000001 4715#define prli_tgt_WORD word4 4716#define prli_init_SHIFT 5 4717#define prli_init_MASK 0x00000001 4718#define prli_init_WORD word4 4719#define prli_conf_SHIFT 7 4720#define prli_conf_MASK 0x00000001 4721#define prli_conf_WORD word4 4722#define prli_nsler_SHIFT 8 4723#define prli_nsler_MASK 0x00000001 4724#define prli_nsler_WORD word4 4725 uint32_t word5; 4726#define prli_fb_sz_SHIFT 0 4727#define prli_fb_sz_MASK 0x0000ffff 4728#define prli_fb_sz_WORD word5 4729#define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4730}; 4731 4732struct create_xri_wqe { 4733 uint32_t rsrvd[5]; /* words 0-4 */ 4734 struct wqe_did wqe_dest; /* word 5 */ 4735 struct wqe_common wqe_com; /* words 6-11 */ 4736 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4737}; 4738 4739#define INHIBIT_ABORT 1 4740#define T_REQUEST_TAG 3 4741#define T_XRI_TAG 1 4742 4743struct cmf_sync_wqe { 4744 uint32_t rsrvd[3]; 4745 uint32_t word3; 4746#define cmf_sync_interval_SHIFT 0 4747#define cmf_sync_interval_MASK 0x00000ffff 4748#define cmf_sync_interval_WORD word3 4749#define cmf_sync_afpin_SHIFT 16 4750#define cmf_sync_afpin_MASK 0x000000001 4751#define cmf_sync_afpin_WORD word3 4752#define cmf_sync_asig_SHIFT 17 4753#define cmf_sync_asig_MASK 0x000000001 4754#define cmf_sync_asig_WORD word3 4755#define cmf_sync_op_SHIFT 20 4756#define cmf_sync_op_MASK 0x00000000f 4757#define cmf_sync_op_WORD word3 4758#define cmf_sync_ver_SHIFT 24 4759#define cmf_sync_ver_MASK 0x0000000ff 4760#define cmf_sync_ver_WORD word3 4761#define LPFC_CMF_SYNC_VER 1 4762 uint32_t event_tag; 4763 uint32_t word5; 4764#define cmf_sync_wsigmax_SHIFT 0 4765#define cmf_sync_wsigmax_MASK 0x00000ffff 4766#define cmf_sync_wsigmax_WORD word5 4767#define cmf_sync_wsigcnt_SHIFT 16 4768#define cmf_sync_wsigcnt_MASK 0x00000ffff 4769#define cmf_sync_wsigcnt_WORD word5 4770 uint32_t word6; 4771 uint32_t word7; 4772#define cmf_sync_cmnd_SHIFT 8 4773#define cmf_sync_cmnd_MASK 0x0000000ff 4774#define cmf_sync_cmnd_WORD word7 4775 uint32_t word8; 4776 uint32_t word9; 4777#define cmf_sync_reqtag_SHIFT 0 4778#define cmf_sync_reqtag_MASK 0x00000ffff 4779#define cmf_sync_reqtag_WORD word9 4780#define cmf_sync_wfpinmax_SHIFT 16 4781#define cmf_sync_wfpinmax_MASK 0x0000000ff 4782#define cmf_sync_wfpinmax_WORD word9 4783#define cmf_sync_wfpincnt_SHIFT 24 4784#define cmf_sync_wfpincnt_MASK 0x0000000ff 4785#define cmf_sync_wfpincnt_WORD word9 4786 uint32_t word10; 4787#define cmf_sync_qosd_SHIFT 9 4788#define cmf_sync_qosd_MASK 0x00000001 4789#define cmf_sync_qosd_WORD word10 4790 uint32_t word11; 4791#define cmf_sync_cmd_type_SHIFT 0 4792#define cmf_sync_cmd_type_MASK 0x0000000f 4793#define cmf_sync_cmd_type_WORD word11 4794#define cmf_sync_wqec_SHIFT 7 4795#define cmf_sync_wqec_MASK 0x00000001 4796#define cmf_sync_wqec_WORD word11 4797#define cmf_sync_cqid_SHIFT 16 4798#define cmf_sync_cqid_MASK 0x0000ffff 4799#define cmf_sync_cqid_WORD word11 4800 uint32_t read_bytes; 4801 uint32_t word13; 4802 uint32_t word14; 4803 uint32_t word15; 4804}; 4805 4806struct abort_cmd_wqe { 4807 uint32_t rsrvd[3]; 4808 uint32_t word3; 4809#define abort_cmd_ia_SHIFT 0 4810#define abort_cmd_ia_MASK 0x000000001 4811#define abort_cmd_ia_WORD word3 4812#define abort_cmd_criteria_SHIFT 8 4813#define abort_cmd_criteria_MASK 0x0000000ff 4814#define abort_cmd_criteria_WORD word3 4815 uint32_t rsrvd4; 4816 uint32_t rsrvd5; 4817 struct wqe_common wqe_com; /* words 6-11 */ 4818 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4819}; 4820 4821struct fcp_iwrite64_wqe { 4822 struct ulp_bde64 bde; 4823 uint32_t word3; 4824#define cmd_buff_len_SHIFT 16 4825#define cmd_buff_len_MASK 0x00000ffff 4826#define cmd_buff_len_WORD word3 4827#define payload_offset_len_SHIFT 0 4828#define payload_offset_len_MASK 0x0000ffff 4829#define payload_offset_len_WORD word3 4830 uint32_t total_xfer_len; 4831 uint32_t initial_xfer_len; 4832 struct wqe_common wqe_com; /* words 6-11 */ 4833 uint32_t rsrvd12; 4834 struct ulp_bde64 ph_bde; /* words 13-15 */ 4835}; 4836 4837struct fcp_iread64_wqe { 4838 struct ulp_bde64 bde; 4839 uint32_t word3; 4840#define cmd_buff_len_SHIFT 16 4841#define cmd_buff_len_MASK 0x00000ffff 4842#define cmd_buff_len_WORD word3 4843#define payload_offset_len_SHIFT 0 4844#define payload_offset_len_MASK 0x0000ffff 4845#define payload_offset_len_WORD word3 4846 uint32_t total_xfer_len; /* word 4 */ 4847 uint32_t rsrvd5; /* word 5 */ 4848 struct wqe_common wqe_com; /* words 6-11 */ 4849 uint32_t rsrvd12; 4850 struct ulp_bde64 ph_bde; /* words 13-15 */ 4851}; 4852 4853struct fcp_icmnd64_wqe { 4854 struct ulp_bde64 bde; /* words 0-2 */ 4855 uint32_t word3; 4856#define cmd_buff_len_SHIFT 16 4857#define cmd_buff_len_MASK 0x00000ffff 4858#define cmd_buff_len_WORD word3 4859#define payload_offset_len_SHIFT 0 4860#define payload_offset_len_MASK 0x0000ffff 4861#define payload_offset_len_WORD word3 4862 uint32_t rsrvd4; /* word 4 */ 4863 uint32_t rsrvd5; /* word 5 */ 4864 struct wqe_common wqe_com; /* words 6-11 */ 4865 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4866}; 4867 4868struct fcp_trsp64_wqe { 4869 struct ulp_bde64 bde; 4870 uint32_t response_len; 4871 uint32_t rsvd_4_5[2]; 4872 struct wqe_common wqe_com; /* words 6-11 */ 4873 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4874}; 4875 4876struct fcp_tsend64_wqe { 4877 struct ulp_bde64 bde; 4878 uint32_t payload_offset_len; 4879 uint32_t relative_offset; 4880 uint32_t reserved; 4881 struct wqe_common wqe_com; /* words 6-11 */ 4882 uint32_t fcp_data_len; /* word 12 */ 4883 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4884}; 4885 4886struct fcp_treceive64_wqe { 4887 struct ulp_bde64 bde; 4888 uint32_t payload_offset_len; 4889 uint32_t relative_offset; 4890 uint32_t reserved; 4891 struct wqe_common wqe_com; /* words 6-11 */ 4892 uint32_t fcp_data_len; /* word 12 */ 4893 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4894}; 4895#define TXRDY_PAYLOAD_LEN 12 4896 4897#define CMD_SEND_FRAME 0xE1 4898 4899struct send_frame_wqe { 4900 struct ulp_bde64 bde; /* words 0-2 */ 4901 uint32_t frame_len; /* word 3 */ 4902 uint32_t fc_hdr_wd0; /* word 4 */ 4903 uint32_t fc_hdr_wd1; /* word 5 */ 4904 struct wqe_common wqe_com; /* words 6-11 */ 4905 uint32_t fc_hdr_wd2; /* word 12 */ 4906 uint32_t fc_hdr_wd3; /* word 13 */ 4907 uint32_t fc_hdr_wd4; /* word 14 */ 4908 uint32_t fc_hdr_wd5; /* word 15 */ 4909}; 4910 4911#define ELS_RDF_REG_TAG_CNT 4 4912struct lpfc_els_rdf_reg_desc { 4913 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4914 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4915 /* tags in reg_desc */ 4916}; 4917 4918struct lpfc_els_rdf_req { 4919 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4920 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4921}; 4922 4923struct lpfc_els_rdf_rsp { 4924 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4925 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4926}; 4927 4928union lpfc_wqe { 4929 uint32_t words[16]; 4930 struct lpfc_wqe_generic generic; 4931 struct fcp_icmnd64_wqe fcp_icmd; 4932 struct fcp_iread64_wqe fcp_iread; 4933 struct fcp_iwrite64_wqe fcp_iwrite; 4934 struct abort_cmd_wqe abort_cmd; 4935 struct cmf_sync_wqe cmf_sync; 4936 struct create_xri_wqe create_xri; 4937 struct xmit_bcast64_wqe xmit_bcast64; 4938 struct xmit_seq64_wqe xmit_sequence; 4939 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4940 struct xmit_els_rsp64_wqe xmit_els_rsp; 4941 struct els_request64_wqe els_req; 4942 struct gen_req64_wqe gen_req; 4943 struct fcp_trsp64_wqe fcp_trsp; 4944 struct fcp_tsend64_wqe fcp_tsend; 4945 struct fcp_treceive64_wqe fcp_treceive; 4946 struct send_frame_wqe send_frame; 4947}; 4948 4949union lpfc_wqe128 { 4950 uint32_t words[32]; 4951 struct lpfc_wqe_generic generic; 4952 struct fcp_icmnd64_wqe fcp_icmd; 4953 struct fcp_iread64_wqe fcp_iread; 4954 struct fcp_iwrite64_wqe fcp_iwrite; 4955 struct abort_cmd_wqe abort_cmd; 4956 struct cmf_sync_wqe cmf_sync; 4957 struct create_xri_wqe create_xri; 4958 struct xmit_bcast64_wqe xmit_bcast64; 4959 struct xmit_seq64_wqe xmit_sequence; 4960 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4961 struct xmit_els_rsp64_wqe xmit_els_rsp; 4962 struct els_request64_wqe els_req; 4963 struct gen_req64_wqe gen_req; 4964 struct fcp_trsp64_wqe fcp_trsp; 4965 struct fcp_tsend64_wqe fcp_tsend; 4966 struct fcp_treceive64_wqe fcp_treceive; 4967 struct send_frame_wqe send_frame; 4968}; 4969 4970#define MAGIC_NUMBER_G6 0xFEAA0003 4971#define MAGIC_NUMBER_G7 0xFEAA0005 4972#define MAGIC_NUMBER_G7P 0xFEAA0020 4973 4974struct lpfc_grp_hdr { 4975 uint32_t size; 4976 uint32_t magic_number; 4977 uint32_t word2; 4978#define lpfc_grp_hdr_file_type_SHIFT 24 4979#define lpfc_grp_hdr_file_type_MASK 0x000000FF 4980#define lpfc_grp_hdr_file_type_WORD word2 4981#define lpfc_grp_hdr_id_SHIFT 16 4982#define lpfc_grp_hdr_id_MASK 0x000000FF 4983#define lpfc_grp_hdr_id_WORD word2 4984 uint8_t rev_name[128]; 4985 uint8_t date[12]; 4986 uint8_t revision[32]; 4987}; 4988 4989/* Defines for WQE command type */ 4990#define FCP_COMMAND 0x0 4991#define NVME_READ_CMD 0x0 4992#define FCP_COMMAND_DATA_OUT 0x1 4993#define NVME_WRITE_CMD 0x1 4994#define COMMAND_DATA_IN 0x0 4995#define COMMAND_DATA_OUT 0x1 4996#define FCP_COMMAND_TRECEIVE 0x2 4997#define FCP_COMMAND_TRSP 0x3 4998#define FCP_COMMAND_TSEND 0x7 4999#define OTHER_COMMAND 0x8 5000#define CMF_SYNC_COMMAND 0xA 5001#define ELS_COMMAND_NON_FIP 0xC 5002#define ELS_COMMAND_FIP 0xD 5003 5004#define LPFC_NVME_EMBED_CMD 0x0 5005#define LPFC_NVME_EMBED_WRITE 0x1 5006#define LPFC_NVME_EMBED_READ 0x2 5007 5008/* WQE Commands */ 5009#define CMD_ABORT_XRI_WQE 0x0F 5010#define CMD_XMIT_SEQUENCE64_WQE 0x82 5011#define CMD_XMIT_BCAST64_WQE 0x84 5012#define CMD_ELS_REQUEST64_WQE 0x8A 5013#define CMD_XMIT_ELS_RSP64_WQE 0x95 5014#define CMD_XMIT_BLS_RSP64_WQE 0x97 5015#define CMD_FCP_IWRITE64_WQE 0x98 5016#define CMD_FCP_IREAD64_WQE 0x9A 5017#define CMD_FCP_ICMND64_WQE 0x9C 5018#define CMD_FCP_TSEND64_WQE 0x9F 5019#define CMD_FCP_TRECEIVE64_WQE 0xA1 5020#define CMD_FCP_TRSP64_WQE 0xA3 5021#define CMD_GEN_REQUEST64_WQE 0xC2 5022#define CMD_CMF_SYNC_WQE 0xE8 5023 5024#define CMD_WQE_MASK 0xff 5025 5026 5027#define LPFC_FW_DUMP 1 5028#define LPFC_FW_RESET 2 5029#define LPFC_DV_RESET 3 5030 5031/* On some kernels, enum fc_ls_tlv_dtag does not have 5032 * these 2 enums defined, on other kernels it does. 5033 * To get aound this we need to add these 2 defines here. 5034 */ 5035#ifndef ELS_DTAG_LNK_FAULT_CAP 5036#define ELS_DTAG_LNK_FAULT_CAP 0x0001000D 5037#endif 5038#ifndef ELS_DTAG_CG_SIGNAL_CAP 5039#define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F 5040#endif 5041 5042/* 5043 * Initializer useful for decoding FPIN string table. 5044 */ 5045#define FC_FPIN_CONGN_SEVERITY_INIT { \ 5046 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \ 5047 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \ 5048} 5049 5050/* EDC supports two descriptors. When allocated, it is the 5051 * size of this structure plus each supported descriptor. 5052 */ 5053struct lpfc_els_edc_req { 5054 struct fc_els_edc edc; /* hdr up to descriptors */ 5055 struct fc_diag_cg_sig_desc cgn_desc; /* 1st descriptor */ 5056}; 5057 5058/* Minimum structure defines for the EDC response. 5059 * Balance is in buffer. 5060 */ 5061struct lpfc_els_edc_rsp { 5062 struct fc_els_edc_resp edc_rsp; /* hdr up to descriptors */ 5063 struct fc_diag_cg_sig_desc cgn_desc; /* 1st descriptor */ 5064}; 5065 5066/* Used for logging FPIN messages */ 5067#define LPFC_FPIN_WWPN_LINE_SZ 128 5068#define LPFC_FPIN_WWPN_LINE_CNT 6 5069#define LPFC_FPIN_WWPN_NUM_LINE 6