cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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megaraid_mbox.h (7845B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *
      4 *			Linux MegaRAID device driver
      5 *
      6 * Copyright (c) 2003-2004  LSI Logic Corporation.
      7 *
      8 * FILE		: megaraid_mbox.h
      9 */
     10
     11#ifndef _MEGARAID_H_
     12#define _MEGARAID_H_
     13
     14
     15#include "mega_common.h"
     16#include "mbox_defs.h"
     17#include "megaraid_ioctl.h"
     18
     19
     20#define MEGARAID_VERSION	"2.20.5.1"
     21#define MEGARAID_EXT_VERSION	"(Release Date: Thu Nov 16 15:32:35 EST 2006)"
     22
     23
     24/*
     25 * Define some PCI values here until they are put in the kernel
     26 */
     27#define PCI_DEVICE_ID_PERC4_DI_DISCOVERY		0x000E
     28#define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY		0x0123
     29
     30#define PCI_DEVICE_ID_PERC4_SC				0x1960
     31#define PCI_SUBSYS_ID_PERC4_SC				0x0520
     32
     33#define PCI_DEVICE_ID_PERC4_DC				0x1960
     34#define PCI_SUBSYS_ID_PERC4_DC				0x0518
     35
     36#define PCI_DEVICE_ID_VERDE				0x0407
     37
     38#define PCI_DEVICE_ID_PERC4_DI_EVERGLADES		0x000F
     39#define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES		0x014A
     40
     41#define PCI_DEVICE_ID_PERC4E_SI_BIGBEND			0x0013
     42#define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND			0x016c
     43
     44#define PCI_DEVICE_ID_PERC4E_DI_KOBUK			0x0013
     45#define PCI_SUBSYS_ID_PERC4E_DI_KOBUK			0x016d
     46
     47#define PCI_DEVICE_ID_PERC4E_DI_CORVETTE		0x0013
     48#define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE		0x016e
     49
     50#define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION		0x0013
     51#define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION		0x016f
     52
     53#define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE		0x0013
     54#define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE		0x0170
     55
     56#define PCI_DEVICE_ID_DOBSON				0x0408
     57
     58#define PCI_DEVICE_ID_MEGARAID_SCSI_320_0		0x1960
     59#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0		0xA520
     60
     61#define PCI_DEVICE_ID_MEGARAID_SCSI_320_1		0x1960
     62#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1		0x0520
     63
     64#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2		0x1960
     65#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2		0x0518
     66
     67#define PCI_DEVICE_ID_MEGARAID_I4_133_RAID		0x1960
     68#define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID		0x0522
     69
     70#define PCI_DEVICE_ID_MEGARAID_SATA_150_4		0x1960
     71#define PCI_SUBSYS_ID_MEGARAID_SATA_150_4		0x4523
     72
     73#define PCI_DEVICE_ID_MEGARAID_SATA_150_6		0x1960
     74#define PCI_SUBSYS_ID_MEGARAID_SATA_150_6		0x0523
     75
     76#define PCI_DEVICE_ID_LINDSAY				0x0409
     77
     78#define PCI_DEVICE_ID_INTEL_RAID_SRCS16			0x1960
     79#define PCI_SUBSYS_ID_INTEL_RAID_SRCS16			0x0523
     80
     81#define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK	0x1960
     82#define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK	0x0520
     83
     84#define PCI_SUBSYS_ID_PERC3_QC				0x0471
     85#define PCI_SUBSYS_ID_PERC3_DC				0x0493
     86#define PCI_SUBSYS_ID_PERC3_SC				0x0475
     87#define PCI_SUBSYS_ID_CERC_ATA100_4CH			0x0511
     88
     89
     90#define MBOX_MAX_SCSI_CMDS	128	// number of cmds reserved for kernel
     91#define MBOX_MAX_USER_CMDS	32	// number of cmds for applications
     92#define MBOX_DEF_CMD_PER_LUN	64	// default commands per lun
     93#define MBOX_DEFAULT_SG_SIZE	26	// default sg size supported by all fw
     94#define MBOX_MAX_SG_SIZE	32	// maximum scatter-gather list size
     95#define MBOX_MAX_SECTORS	128	// maximum sectors per IO
     96#define MBOX_TIMEOUT		30	// timeout value for internal cmds
     97#define MBOX_BUSY_WAIT		10	// max usec to wait for busy mailbox
     98#define MBOX_RESET_WAIT		180	// wait these many seconds in reset
     99#define MBOX_RESET_EXT_WAIT	120	// extended wait reset
    100#define MBOX_SYNC_WAIT_CNT	0xFFFF	// wait loop index for synchronous mode
    101
    102#define MBOX_SYNC_DELAY_200	200	// 200 micro-seconds
    103
    104/*
    105 * maximum transfer that can happen through the firmware commands issued
    106 * internnaly from the driver.
    107 */
    108#define MBOX_IBUF_SIZE		4096
    109
    110
    111/**
    112 * mbox_ccb_t - command control block specific to mailbox based controllers
    113 * @raw_mbox		: raw mailbox pointer
    114 * @mbox		: mailbox
    115 * @mbox64		: extended mailbox
    116 * @mbox_dma_h		: mailbox dma address
    117 * @sgl64		: 64-bit scatter-gather list
    118 * @sgl32		: 32-bit scatter-gather list
    119 * @sgl_dma_h		: dma handle for the scatter-gather list
    120 * @pthru		: passthru structure
    121 * @pthru_dma_h		: dma handle for the passthru structure
    122 * @epthru		: extended passthru structure
    123 * @epthru_dma_h	: dma handle for extended passthru structure
    124 * @buf_dma_h		: dma handle for buffers w/o sg list
    125 *
    126 * command control block specific to the mailbox based controllers
    127 */
    128typedef struct {
    129	uint8_t			*raw_mbox;
    130	mbox_t			*mbox;
    131	mbox64_t		*mbox64;
    132	dma_addr_t		mbox_dma_h;
    133	mbox_sgl64		*sgl64;
    134	mbox_sgl32		*sgl32;
    135	dma_addr_t		sgl_dma_h;
    136	mraid_passthru_t	*pthru;
    137	dma_addr_t		pthru_dma_h;
    138	mraid_epassthru_t	*epthru;
    139	dma_addr_t		epthru_dma_h;
    140	dma_addr_t		buf_dma_h;
    141} mbox_ccb_t;
    142
    143
    144/**
    145 * mraid_device_t - adapter soft state structure for mailbox controllers
    146 * @una_mbox64			: 64-bit mbox - unaligned
    147 * @una_mbox64_dma		: mbox dma addr - unaligned
    148 * @mbox			: 32-bit mbox - aligned
    149 * @mbox64			: 64-bit mbox - aligned
    150 * @mbox_dma			: mbox dma addr - aligned
    151 * @mailbox_lock		: exclusion lock for the mailbox
    152 * @baseport			: base port of hba memory
    153 * @baseaddr			: mapped addr of hba memory
    154 * @mbox_pool			: pool of mailboxes
    155 * @mbox_pool_handle		: handle for the mailbox pool memory
    156 * @epthru_pool			: a pool for extended passthru commands
    157 * @epthru_pool_handle		: handle to the pool above
    158 * @sg_pool			: pool of scatter-gather lists for this driver
    159 * @sg_pool_handle		: handle to the pool above
    160 * @ccb_list			: list of our command control blocks
    161 * @uccb_list			: list of cmd control blocks for mgmt module
    162 * @umbox64			: array of mailbox for user commands (cmm)
    163 * @pdrv_state			: array for state of each physical drive.
    164 * @last_disp			: flag used to show device scanning
    165 * @hw_error			: set if FW not responding
    166 * @fast_load			: If set, skip physical device scanning
    167 * @channel_class		: channel class, RAID or SCSI
    168 * @sysfs_mtx			: mutex to serialize access to sysfs res.
    169 * @sysfs_uioc			: management packet to issue FW calls from sysfs
    170 * @sysfs_mbox64		: mailbox packet to issue FW calls from sysfs
    171 * @sysfs_buffer		: data buffer for FW commands issued from sysfs
    172 * @sysfs_buffer_dma		: DMA buffer for FW commands issued from sysfs
    173 * @sysfs_wait_q		: wait queue for sysfs operations
    174 * @random_del_supported	: set if the random deletion is supported
    175 * @curr_ldmap			: current LDID map
    176 *
    177 * Initialization structure for mailbox controllers: memory based and IO based
    178 * All the fields in this structure are LLD specific and may be discovered at
    179 * init() or start() time.
    180 *
    181 * NOTE: The fields of this structures are placed to minimize cache misses
    182 */
    183#define MAX_LD_EXTENDED64	64
    184typedef struct {
    185	mbox64_t			*una_mbox64;
    186	dma_addr_t			una_mbox64_dma;
    187	mbox_t				*mbox;
    188	mbox64_t			*mbox64;
    189	dma_addr_t			mbox_dma;
    190	spinlock_t			mailbox_lock;
    191	unsigned long			baseport;
    192	void __iomem *			baseaddr;
    193	struct mraid_pci_blk		mbox_pool[MBOX_MAX_SCSI_CMDS];
    194	struct dma_pool			*mbox_pool_handle;
    195	struct mraid_pci_blk		epthru_pool[MBOX_MAX_SCSI_CMDS];
    196	struct dma_pool			*epthru_pool_handle;
    197	struct mraid_pci_blk		sg_pool[MBOX_MAX_SCSI_CMDS];
    198	struct dma_pool			*sg_pool_handle;
    199	mbox_ccb_t			ccb_list[MBOX_MAX_SCSI_CMDS];
    200	mbox_ccb_t			uccb_list[MBOX_MAX_USER_CMDS];
    201	mbox64_t			umbox64[MBOX_MAX_USER_CMDS];
    202
    203	uint8_t				pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
    204	uint32_t			last_disp;
    205	int				hw_error;
    206	int				fast_load;
    207	uint8_t				channel_class;
    208	struct mutex			sysfs_mtx;
    209	uioc_t				*sysfs_uioc;
    210	mbox64_t			*sysfs_mbox64;
    211	caddr_t				sysfs_buffer;
    212	dma_addr_t			sysfs_buffer_dma;
    213	wait_queue_head_t		sysfs_wait_q;
    214	int				random_del_supported;
    215	uint16_t			curr_ldmap[MAX_LD_EXTENDED64];
    216} mraid_device_t;
    217
    218// route to raid device from adapter
    219#define ADAP2RAIDDEV(adp)	((mraid_device_t *)((adp)->raid_device))
    220
    221#define MAILBOX_LOCK(rdev)	(&(rdev)->mailbox_lock)
    222
    223// Find out if this channel is a RAID or SCSI
    224#define IS_RAID_CH(rdev, ch)	(((rdev)->channel_class >> (ch)) & 0x01)
    225
    226
    227#define RDINDOOR(rdev)		readl((rdev)->baseaddr + 0x20)
    228#define RDOUTDOOR(rdev)		readl((rdev)->baseaddr + 0x2C)
    229#define WRINDOOR(rdev, value)	writel(value, (rdev)->baseaddr + 0x20)
    230#define WROUTDOOR(rdev, value)	writel(value, (rdev)->baseaddr + 0x2C)
    231
    232#endif // _MEGARAID_H_