cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mv_64xx.h (4330B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Marvell 88SE64xx hardware specific head file
      4 *
      5 * Copyright 2007 Red Hat, Inc.
      6 * Copyright 2008 Marvell. <kewei@marvell.com>
      7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
      8*/
      9
     10#ifndef _MVS64XX_REG_H_
     11#define _MVS64XX_REG_H_
     12
     13#include <linux/types.h>
     14
     15#define MAX_LINK_RATE		SAS_LINK_RATE_3_0_GBPS
     16
     17/* enhanced mode registers (BAR4) */
     18enum hw_registers {
     19	MVS_GBL_CTL		= 0x04,  /* global control */
     20	MVS_GBL_INT_STAT	= 0x08,  /* global irq status */
     21	MVS_GBL_PI		= 0x0C,  /* ports implemented bitmask */
     22
     23	MVS_PHY_CTL		= 0x40,  /* SOC PHY Control */
     24	MVS_PORTS_IMP		= 0x9C,  /* SOC Port Implemented */
     25
     26	MVS_GBL_PORT_TYPE	= 0xa0,  /* port type */
     27
     28	MVS_CTL			= 0x100, /* SAS/SATA port configuration */
     29	MVS_PCS			= 0x104, /* SAS/SATA port control/status */
     30	MVS_CMD_LIST_LO		= 0x108, /* cmd list addr */
     31	MVS_CMD_LIST_HI		= 0x10C,
     32	MVS_RX_FIS_LO		= 0x110, /* RX FIS list addr */
     33	MVS_RX_FIS_HI		= 0x114,
     34
     35	MVS_TX_CFG		= 0x120, /* TX configuration */
     36	MVS_TX_LO		= 0x124, /* TX (delivery) ring addr */
     37	MVS_TX_HI		= 0x128,
     38
     39	MVS_TX_PROD_IDX		= 0x12C, /* TX producer pointer */
     40	MVS_TX_CONS_IDX		= 0x130, /* TX consumer pointer (RO) */
     41	MVS_RX_CFG		= 0x134, /* RX configuration */
     42	MVS_RX_LO		= 0x138, /* RX (completion) ring addr */
     43	MVS_RX_HI		= 0x13C,
     44	MVS_RX_CONS_IDX		= 0x140, /* RX consumer pointer (RO) */
     45
     46	MVS_INT_COAL		= 0x148, /* Int coalescing config */
     47	MVS_INT_COAL_TMOUT	= 0x14C, /* Int coalescing timeout */
     48	MVS_INT_STAT		= 0x150, /* Central int status */
     49	MVS_INT_MASK		= 0x154, /* Central int enable */
     50	MVS_INT_STAT_SRS_0	= 0x158, /* SATA register set status */
     51	MVS_INT_MASK_SRS_0	= 0x15C,
     52
     53					 /* ports 1-3 follow after this */
     54	MVS_P0_INT_STAT		= 0x160, /* port0 interrupt status */
     55	MVS_P0_INT_MASK		= 0x164, /* port0 interrupt mask */
     56					 /* ports 5-7 follow after this */
     57	MVS_P4_INT_STAT		= 0x200, /* Port4 interrupt status */
     58	MVS_P4_INT_MASK		= 0x204, /* Port4 interrupt enable mask */
     59
     60					 /* ports 1-3 follow after this */
     61	MVS_P0_SER_CTLSTAT	= 0x180, /* port0 serial control/status */
     62					 /* ports 5-7 follow after this */
     63	MVS_P4_SER_CTLSTAT	= 0x220, /* port4 serial control/status */
     64
     65	MVS_CMD_ADDR		= 0x1B8, /* Command register port (addr) */
     66	MVS_CMD_DATA		= 0x1BC, /* Command register port (data) */
     67
     68					 /* ports 1-3 follow after this */
     69	MVS_P0_CFG_ADDR		= 0x1C0, /* port0 phy register address */
     70	MVS_P0_CFG_DATA		= 0x1C4, /* port0 phy register data */
     71					 /* ports 5-7 follow after this */
     72	MVS_P4_CFG_ADDR		= 0x230, /* Port4 config address */
     73	MVS_P4_CFG_DATA		= 0x234, /* Port4 config data */
     74
     75					 /* ports 1-3 follow after this */
     76	MVS_P0_VSR_ADDR		= 0x1E0, /* port0 VSR address */
     77	MVS_P0_VSR_DATA		= 0x1E4, /* port0 VSR data */
     78					 /* ports 5-7 follow after this */
     79	MVS_P4_VSR_ADDR		= 0x250, /* port4 VSR addr */
     80	MVS_P4_VSR_DATA		= 0x254, /* port4 VSR data */
     81};
     82
     83enum pci_cfg_registers {
     84	PCR_PHY_CTL		= 0x40,
     85	PCR_PHY_CTL2		= 0x90,
     86	PCR_DEV_CTRL		= 0xE8,
     87	PCR_LINK_STAT		= 0xF2,
     88};
     89
     90/*  SAS/SATA Vendor Specific Port Registers */
     91enum sas_sata_vsp_regs {
     92	VSR_PHY_STAT		= 0x00, /* Phy Status */
     93	VSR_PHY_MODE1		= 0x01, /* phy tx */
     94	VSR_PHY_MODE2		= 0x02, /* tx scc */
     95	VSR_PHY_MODE3		= 0x03, /* pll */
     96	VSR_PHY_MODE4		= 0x04, /* VCO */
     97	VSR_PHY_MODE5		= 0x05, /* Rx */
     98	VSR_PHY_MODE6		= 0x06, /* CDR */
     99	VSR_PHY_MODE7		= 0x07, /* Impedance */
    100	VSR_PHY_MODE8		= 0x08, /* Voltage */
    101	VSR_PHY_MODE9		= 0x09, /* Test */
    102	VSR_PHY_MODE10		= 0x0A, /* Power */
    103	VSR_PHY_MODE11		= 0x0B, /* Phy Mode */
    104	VSR_PHY_VS0		= 0x0C, /* Vednor Specific 0 */
    105	VSR_PHY_VS1		= 0x0D, /* Vednor Specific 1 */
    106};
    107
    108enum chip_register_bits {
    109	PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
    110	PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
    111	PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
    112	PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
    113			(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
    114};
    115
    116#define MAX_SG_ENTRY		64
    117
    118struct mvs_prd {
    119	__le64			addr;		/* 64-bit buffer address */
    120	__le32			reserved;
    121	__le32			len;		/* 16-bit length */
    122};
    123
    124#define SPI_CTRL_REG				0xc0
    125#define SPI_CTRL_VENDOR_ENABLE		(1U<<29)
    126#define SPI_CTRL_SPIRDY         		(1U<<22)
    127#define SPI_CTRL_SPISTART			(1U<<20)
    128
    129#define SPI_CMD_REG		0xc4
    130#define SPI_DATA_REG		0xc8
    131
    132#define SPI_CTRL_REG_64XX		0x10
    133#define SPI_CMD_REG_64XX		0x14
    134#define SPI_DATA_REG_64XX		0x18
    135
    136#endif