cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pm8001_chips.h (2926B)

      1/*
      2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
      3 *
      4 * Copyright (c) 2008-2009 USI Co., Ltd.
      5 * All rights reserved.
      6 *
      7 * Redistribution and use in source and binary forms, with or without
      8 * modification, are permitted provided that the following conditions
      9 * are met:
     10 * 1. Redistributions of source code must retain the above copyright
     11 *    notice, this list of conditions, and the following disclaimer,
     12 *    without modification.
     13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
     14 *    substantially similar to the "NO WARRANTY" disclaimer below
     15 *    ("Disclaimer") and any redistribution must be conditioned upon
     16 *    including a substantially similar Disclaimer requirement for further
     17 *    binary redistribution.
     18 * 3. Neither the names of the above-listed copyright holders nor the names
     19 *    of any contributors may be used to endorse or promote products derived
     20 *    from this software without specific prior written permission.
     21 *
     22 * Alternatively, this software may be distributed under the terms of the
     23 * GNU General Public License ("GPL") version 2 as published by the Free
     24 * Software Foundation.
     25 *
     26 * NO WARRANTY
     27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
     30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37 * POSSIBILITY OF SUCH DAMAGES.
     38 *
     39 */
     40
     41#ifndef _PM8001_CHIPS_H_
     42#define _PM8001_CHIPS_H_
     43
     44static inline u32 pm8001_read_32(void *virt_addr)
     45{
     46	return *((u32 *)virt_addr);
     47}
     48
     49static inline void pm8001_write_32(void *addr, u32 offset, __le32 val)
     50{
     51	*((__le32 *)(addr + offset)) = val;
     52}
     53
     54static inline u32 pm8001_cr32(struct pm8001_hba_info *pm8001_ha, u32 bar,
     55		u32 offset)
     56{
     57	return readl(pm8001_ha->io_mem[bar].memvirtaddr + offset);
     58}
     59
     60static inline void pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar,
     61		u32 addr, u32 val)
     62{
     63	writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
     64}
     65static inline u32 pm8001_mr32(void __iomem *addr, u32 offset)
     66{
     67	return readl(addr + offset);
     68}
     69static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val)
     70{
     71	writel(val, addr + offset);
     72}
     73static inline u32 get_pci_bar_index(u32 pcibar)
     74{
     75		switch (pcibar) {
     76		case 0x18:
     77		case 0x1C:
     78			return 1;
     79		case 0x20:
     80			return 2;
     81		case 0x24:
     82			return 3;
     83		default:
     84			return 0;
     85	}
     86}
     87
     88#endif  /* _PM8001_CHIPS_H_ */
     89