cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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smartpqi_sis.h (1561B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 *    driver for Microchip PQI-based storage controllers
      4 *    Copyright (c) 2019-2021 Microchip Technology Inc. and its subsidiaries
      5 *    Copyright (c) 2016-2018 Microsemi Corporation
      6 *    Copyright (c) 2016 PMC-Sierra, Inc.
      7 *
      8 *    Questions/Comments/Bugfixes to storagedev@microchip.com
      9 *
     10 */
     11
     12#if !defined(_SMARTPQI_SIS_H)
     13#define _SMARTPQI_SIS_H
     14
     15void sis_verify_structures(void);
     16int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info);
     17int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info);
     18bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info);
     19bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info);
     20int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info);
     21int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info);
     22int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info);
     23void sis_enable_msix(struct pqi_ctrl_info *ctrl_info);
     24void sis_enable_intx(struct pqi_ctrl_info *ctrl_info);
     25void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info,
     26	enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason);
     27int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info);
     28int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info);
     29void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value);
     30u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info);
     31void sis_soft_reset(struct pqi_ctrl_info *ctrl_info);
     32u32 sis_get_product_id(struct pqi_ctrl_info *ctrl_info);
     33int sis_wait_for_fw_triage_completion(struct pqi_ctrl_info *ctrl_info);
     34
     35#endif	/* _SMARTPQI_SIS_H */