cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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vnic_cq.c (2655B)

      1/*
      2 * Copyright 2014 Cisco Systems, Inc.  All rights reserved.
      3 *
      4 * This program is free software; you may redistribute it and/or modify
      5 * it under the terms of the GNU General Public License as published by
      6 * the Free Software Foundation; version 2 of the License.
      7 *
      8 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
      9 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     10 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     11 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     12 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     13 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     14 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     15 * SOFTWARE.
     16 */
     17
     18#include <linux/errno.h>
     19#include <linux/types.h>
     20#include <linux/pci.h>
     21#include "vnic_dev.h"
     22#include "vnic_cq.h"
     23
     24void svnic_cq_free(struct vnic_cq *cq)
     25{
     26	svnic_dev_free_desc_ring(cq->vdev, &cq->ring);
     27
     28	cq->ctrl = NULL;
     29}
     30
     31int svnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq,
     32	unsigned int index, unsigned int desc_count, unsigned int desc_size)
     33{
     34	cq->index = index;
     35	cq->vdev = vdev;
     36
     37	cq->ctrl = svnic_dev_get_res(vdev, RES_TYPE_CQ, index);
     38	if (!cq->ctrl) {
     39		pr_err("Failed to hook CQ[%d] resource\n", index);
     40
     41		return -EINVAL;
     42	}
     43
     44	return svnic_dev_alloc_desc_ring(vdev, &cq->ring, desc_count, desc_size);
     45}
     46
     47void svnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
     48	unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
     49	unsigned int cq_tail_color, unsigned int interrupt_enable,
     50	unsigned int cq_entry_enable, unsigned int cq_message_enable,
     51	unsigned int interrupt_offset, u64 cq_message_addr)
     52{
     53	u64 paddr;
     54
     55	paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;
     56	writeq(paddr, &cq->ctrl->ring_base);
     57	iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size);
     58	iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable);
     59	iowrite32(color_enable, &cq->ctrl->color_enable);
     60	iowrite32(cq_head, &cq->ctrl->cq_head);
     61	iowrite32(cq_tail, &cq->ctrl->cq_tail);
     62	iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color);
     63	iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable);
     64	iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable);
     65	iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable);
     66	iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset);
     67	writeq(cq_message_addr, &cq->ctrl->cq_message_addr);
     68}
     69
     70void svnic_cq_clean(struct vnic_cq *cq)
     71{
     72	cq->to_clean = 0;
     73	cq->last_color = 0;
     74
     75	iowrite32(0, &cq->ctrl->cq_head);
     76	iowrite32(0, &cq->ctrl->cq_tail);
     77	iowrite32(1, &cq->ctrl->cq_tail_color);
     78
     79	svnic_dev_clear_desc_ring(&cq->ring);
     80}