cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Kconfig (2309B)


      1# SPDX-License-Identifier: GPL-2.0-only
      2menuconfig FSL_DPAA
      3	bool "QorIQ DPAA1 framework support"
      4	depends on ((FSL_SOC_BOOKE || ARCH_LAYERSCAPE) && ARCH_DMA_ADDR_T_64BIT)
      5	select GENERIC_ALLOCATOR
      6	help
      7	  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
      8	  hardware components on specific QorIQ multicore processors.
      9	  This architecture provides the infrastructure to support simplified
     10	  sharing of networking interfaces and accelerators by multiple CPUs.
     11	  The major h/w blocks composing DPAA are BMan and QMan.
     12
     13	  The Buffer Manager (BMan) is a hardware buffer pool management block
     14	  that allows software and accelerators on the datapath to acquire and
     15	  release buffers in order to build frames.
     16
     17	  The Queue Manager (QMan) is a hardware queue management block
     18	  that allows software and accelerators on the datapath to enqueue and
     19	  dequeue frames in order to communicate.
     20
     21if FSL_DPAA
     22
     23config FSL_DPAA_CHECKING
     24	bool "Additional driver checking"
     25	help
     26	  Compiles in additional checks, to sanity-check the drivers and
     27	  any use of the exported API. Not recommended for performance.
     28
     29config FSL_BMAN_TEST
     30	tristate "BMan self-tests"
     31	help
     32	  Compile the BMan self-test code. These tests will
     33	  exercise the BMan APIs to confirm functionality
     34	  of both the software drivers and hardware device.
     35
     36config FSL_BMAN_TEST_API
     37	bool "High-level API self-test"
     38	depends on FSL_BMAN_TEST
     39	default y
     40	help
     41	  This requires the presence of cpu-affine portals, and performs
     42	  high-level API testing with them (whichever portal(s) are affine
     43	  to the cpu(s) the test executes on).
     44
     45config FSL_QMAN_TEST
     46	tristate "QMan self-tests"
     47	help
     48	  Compile self-test code for QMan.
     49
     50config FSL_QMAN_TEST_API
     51	bool "QMan high-level self-test"
     52	depends on FSL_QMAN_TEST
     53	default y
     54	help
     55	  This requires the presence of cpu-affine portals, and performs
     56	  high-level API testing with them (whichever portal(s) are affine to
     57	  the cpu(s) the test executes on).
     58
     59config FSL_QMAN_TEST_STASH
     60	bool "QMan 'hot potato' data-stashing self-test"
     61	depends on FSL_QMAN_TEST
     62	default y
     63	help
     64	  This performs a "hot potato" style test enqueuing/dequeuing a frame
     65	  across a series of FQs scheduled to different portals (and cpus), with
     66	  DQRR, data and context stashing always on.
     67
     68endif # FSL_DPAA