cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bman_priv.h (3255B)


      1/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
      2 *
      3 * Redistribution and use in source and binary forms, with or without
      4 * modification, are permitted provided that the following conditions are met:
      5 *     * Redistributions of source code must retain the above copyright
      6 *	 notice, this list of conditions and the following disclaimer.
      7 *     * Redistributions in binary form must reproduce the above copyright
      8 *	 notice, this list of conditions and the following disclaimer in the
      9 *	 documentation and/or other materials provided with the distribution.
     10 *     * Neither the name of Freescale Semiconductor nor the
     11 *	 names of its contributors may be used to endorse or promote products
     12 *	 derived from this software without specific prior written permission.
     13 *
     14 * ALTERNATIVELY, this software may be distributed under the terms of the
     15 * GNU General Public License ("GPL") as published by the Free Software
     16 * Foundation, either version 2 of that License or (at your option) any
     17 * later version.
     18 *
     19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
     20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
     23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     29 */
     30
     31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
     32
     33#include "dpaa_sys.h"
     34
     35#include <soc/fsl/bman.h>
     36
     37/* Portal processing (interrupt) sources */
     38#define BM_PIRQ_RCRI	0x00000002	/* RCR Ring (below threshold) */
     39
     40/* Revision info (for errata and feature handling) */
     41#define BMAN_REV10 0x0100
     42#define BMAN_REV20 0x0200
     43#define BMAN_REV21 0x0201
     44extern u16 bman_ip_rev;	/* 0 if uninitialised, otherwise BMAN_REVx */
     45
     46extern struct gen_pool *bm_bpalloc;
     47
     48struct bm_portal_config {
     49	/* Portal addresses */
     50	void  *addr_virt_ce;
     51	void __iomem *addr_virt_ci;
     52	/* Allow these to be joined in lists */
     53	struct list_head list;
     54	struct device *dev;
     55	/* User-visible portal configuration settings */
     56	/* portal is affined to this cpu */
     57	int cpu;
     58	/* portal interrupt line */
     59	int irq;
     60};
     61
     62struct bman_portal *bman_create_affine_portal(
     63			const struct bm_portal_config *config);
     64/*
     65 * The below bman_p_***() variant might be called in a situation that the cpu
     66 * which the portal affine to is not online yet.
     67 * @bman_portal specifies which portal the API will use.
     68 */
     69int bman_p_irqsource_add(struct bman_portal *p, u32 bits);
     70
     71/*
     72 * Used by all portal interrupt registers except 'inhibit'
     73 * This mask contains all the "irqsource" bits visible to API users
     74 */
     75#define BM_PIRQ_VISIBLE	BM_PIRQ_RCRI
     76
     77const struct bm_portal_config *
     78bman_get_bm_portal_config(const struct bman_portal *portal);
     79
     80int bman_requires_cleanup(void);
     81void bman_done_cleanup(void);
     82
     83int bm_shutdown_pool(u32 bpid);