cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt8173-pm-domains.h (3619B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2
      3#ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
      4#define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
      5
      6#include "mtk-pm-domains.h"
      7#include <dt-bindings/power/mt8173-power.h>
      8
      9/*
     10 * MT8173 power domain support
     11 */
     12
     13static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
     14	[MT8173_POWER_DOMAIN_VDEC] = {
     15		.name = "vdec",
     16		.sta_mask = PWR_STATUS_VDEC,
     17		.ctl_offs = SPM_VDE_PWR_CON,
     18		.pwr_sta_offs = SPM_PWR_STATUS,
     19		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     20		.sram_pdn_bits = GENMASK(11, 8),
     21		.sram_pdn_ack_bits = GENMASK(12, 12),
     22	},
     23	[MT8173_POWER_DOMAIN_VENC] = {
     24		.name = "venc",
     25		.sta_mask = PWR_STATUS_VENC,
     26		.ctl_offs = SPM_VEN_PWR_CON,
     27		.pwr_sta_offs = SPM_PWR_STATUS,
     28		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     29		.sram_pdn_bits = GENMASK(11, 8),
     30		.sram_pdn_ack_bits = GENMASK(15, 12),
     31	},
     32	[MT8173_POWER_DOMAIN_ISP] = {
     33		.name = "isp",
     34		.sta_mask = PWR_STATUS_ISP,
     35		.ctl_offs = SPM_ISP_PWR_CON,
     36		.pwr_sta_offs = SPM_PWR_STATUS,
     37		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     38		.sram_pdn_bits = GENMASK(11, 8),
     39		.sram_pdn_ack_bits = GENMASK(13, 12),
     40	},
     41	[MT8173_POWER_DOMAIN_MM] = {
     42		.name = "mm",
     43		.sta_mask = PWR_STATUS_DISP,
     44		.ctl_offs = SPM_DIS_PWR_CON,
     45		.pwr_sta_offs = SPM_PWR_STATUS,
     46		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     47		.sram_pdn_bits = GENMASK(11, 8),
     48		.sram_pdn_ack_bits = GENMASK(12, 12),
     49		.bp_infracfg = {
     50			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
     51					       MT8173_TOP_AXI_PROT_EN_MM_M1),
     52		},
     53	},
     54	[MT8173_POWER_DOMAIN_VENC_LT] = {
     55		.name = "venc_lt",
     56		.sta_mask = PWR_STATUS_VENC_LT,
     57		.ctl_offs = SPM_VEN2_PWR_CON,
     58		.pwr_sta_offs = SPM_PWR_STATUS,
     59		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     60		.sram_pdn_bits = GENMASK(11, 8),
     61		.sram_pdn_ack_bits = GENMASK(15, 12),
     62	},
     63	[MT8173_POWER_DOMAIN_AUDIO] = {
     64		.name = "audio",
     65		.sta_mask = PWR_STATUS_AUDIO,
     66		.ctl_offs = SPM_AUDIO_PWR_CON,
     67		.pwr_sta_offs = SPM_PWR_STATUS,
     68		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     69		.sram_pdn_bits = GENMASK(11, 8),
     70		.sram_pdn_ack_bits = GENMASK(15, 12),
     71	},
     72	[MT8173_POWER_DOMAIN_USB] = {
     73		.name = "usb",
     74		.sta_mask = PWR_STATUS_USB,
     75		.ctl_offs = SPM_USB_PWR_CON,
     76		.pwr_sta_offs = SPM_PWR_STATUS,
     77		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     78		.sram_pdn_bits = GENMASK(11, 8),
     79		.sram_pdn_ack_bits = GENMASK(15, 12),
     80		.caps = MTK_SCPD_ACTIVE_WAKEUP,
     81	},
     82	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
     83		.name = "mfg_async",
     84		.sta_mask = PWR_STATUS_MFG_ASYNC,
     85		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
     86		.pwr_sta_offs = SPM_PWR_STATUS,
     87		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     88		.sram_pdn_bits = GENMASK(11, 8),
     89		.sram_pdn_ack_bits = 0,
     90		.caps = MTK_SCPD_DOMAIN_SUPPLY,
     91	},
     92	[MT8173_POWER_DOMAIN_MFG_2D] = {
     93		.name = "mfg_2d",
     94		.sta_mask = PWR_STATUS_MFG_2D,
     95		.ctl_offs = SPM_MFG_2D_PWR_CON,
     96		.pwr_sta_offs = SPM_PWR_STATUS,
     97		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
     98		.sram_pdn_bits = GENMASK(11, 8),
     99		.sram_pdn_ack_bits = GENMASK(13, 12),
    100	},
    101	[MT8173_POWER_DOMAIN_MFG] = {
    102		.name = "mfg",
    103		.sta_mask = PWR_STATUS_MFG,
    104		.ctl_offs = SPM_MFG_PWR_CON,
    105		.pwr_sta_offs = SPM_PWR_STATUS,
    106		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
    107		.sram_pdn_bits = GENMASK(13, 8),
    108		.sram_pdn_ack_bits = GENMASK(21, 16),
    109		.bp_infracfg = {
    110			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
    111					       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
    112					       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
    113					       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
    114		},
    115	},
    116};
    117
    118static const struct scpsys_soc_data mt8173_scpsys_data = {
    119	.domains_data = scpsys_domain_data_mt8173,
    120	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
    121};
    122
    123#endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */