mt8183-pm-domains.h (8110B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 4#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 5 6#include "mtk-pm-domains.h" 7#include <dt-bindings/power/mt8183-power.h> 8 9/* 10 * MT8183 power domain support 11 */ 12 13static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 14 [MT8183_POWER_DOMAIN_AUDIO] = { 15 .name = "audio", 16 .sta_mask = PWR_STATUS_AUDIO, 17 .ctl_offs = 0x0314, 18 .pwr_sta_offs = 0x0180, 19 .pwr_sta2nd_offs = 0x0184, 20 .sram_pdn_bits = GENMASK(11, 8), 21 .sram_pdn_ack_bits = GENMASK(15, 12), 22 }, 23 [MT8183_POWER_DOMAIN_CONN] = { 24 .name = "conn", 25 .sta_mask = PWR_STATUS_CONN, 26 .ctl_offs = 0x032c, 27 .pwr_sta_offs = 0x0180, 28 .pwr_sta2nd_offs = 0x0184, 29 .sram_pdn_bits = 0, 30 .sram_pdn_ack_bits = 0, 31 .bp_infracfg = { 32 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, 33 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 34 }, 35 }, 36 [MT8183_POWER_DOMAIN_MFG_ASYNC] = { 37 .name = "mfg_async", 38 .sta_mask = PWR_STATUS_MFG_ASYNC, 39 .ctl_offs = 0x0334, 40 .pwr_sta_offs = 0x0180, 41 .pwr_sta2nd_offs = 0x0184, 42 .sram_pdn_bits = 0, 43 .sram_pdn_ack_bits = 0, 44 }, 45 [MT8183_POWER_DOMAIN_MFG] = { 46 .name = "mfg", 47 .sta_mask = PWR_STATUS_MFG, 48 .ctl_offs = 0x0338, 49 .pwr_sta_offs = 0x0180, 50 .pwr_sta2nd_offs = 0x0184, 51 .sram_pdn_bits = GENMASK(8, 8), 52 .sram_pdn_ack_bits = GENMASK(12, 12), 53 .caps = MTK_SCPD_DOMAIN_SUPPLY, 54 }, 55 [MT8183_POWER_DOMAIN_MFG_CORE0] = { 56 .name = "mfg_core0", 57 .sta_mask = BIT(7), 58 .ctl_offs = 0x034c, 59 .pwr_sta_offs = 0x0180, 60 .pwr_sta2nd_offs = 0x0184, 61 .sram_pdn_bits = GENMASK(8, 8), 62 .sram_pdn_ack_bits = GENMASK(12, 12), 63 }, 64 [MT8183_POWER_DOMAIN_MFG_CORE1] = { 65 .name = "mfg_core1", 66 .sta_mask = BIT(20), 67 .ctl_offs = 0x0310, 68 .pwr_sta_offs = 0x0180, 69 .pwr_sta2nd_offs = 0x0184, 70 .sram_pdn_bits = GENMASK(8, 8), 71 .sram_pdn_ack_bits = GENMASK(12, 12), 72 }, 73 [MT8183_POWER_DOMAIN_MFG_2D] = { 74 .name = "mfg_2d", 75 .sta_mask = PWR_STATUS_MFG_2D, 76 .ctl_offs = 0x0348, 77 .pwr_sta_offs = 0x0180, 78 .pwr_sta2nd_offs = 0x0184, 79 .sram_pdn_bits = GENMASK(8, 8), 80 .sram_pdn_ack_bits = GENMASK(12, 12), 81 .bp_infracfg = { 82 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, 83 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 84 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, 85 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 86 }, 87 }, 88 [MT8183_POWER_DOMAIN_DISP] = { 89 .name = "disp", 90 .sta_mask = PWR_STATUS_DISP, 91 .ctl_offs = 0x030c, 92 .pwr_sta_offs = 0x0180, 93 .pwr_sta2nd_offs = 0x0184, 94 .sram_pdn_bits = GENMASK(8, 8), 95 .sram_pdn_ack_bits = GENMASK(12, 12), 96 .bp_infracfg = { 97 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, 98 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 99 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, 100 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 101 }, 102 .bp_smi = { 103 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, 104 MT8183_SMI_COMMON_CLAMP_EN_SET, 105 MT8183_SMI_COMMON_CLAMP_EN_CLR, 106 MT8183_SMI_COMMON_CLAMP_EN), 107 }, 108 }, 109 [MT8183_POWER_DOMAIN_CAM] = { 110 .name = "cam", 111 .sta_mask = BIT(25), 112 .ctl_offs = 0x0344, 113 .pwr_sta_offs = 0x0180, 114 .pwr_sta2nd_offs = 0x0184, 115 .sram_pdn_bits = GENMASK(9, 8), 116 .sram_pdn_ack_bits = GENMASK(13, 12), 117 .bp_infracfg = { 118 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, 119 MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), 120 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, 121 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 122 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, 123 MT8183_TOP_AXI_PROT_EN_MM_SET, 124 MT8183_TOP_AXI_PROT_EN_MM_CLR, 125 MT8183_TOP_AXI_PROT_EN_MM_STA1), 126 }, 127 .bp_smi = { 128 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, 129 MT8183_SMI_COMMON_CLAMP_EN_SET, 130 MT8183_SMI_COMMON_CLAMP_EN_CLR, 131 MT8183_SMI_COMMON_CLAMP_EN), 132 }, 133 }, 134 [MT8183_POWER_DOMAIN_ISP] = { 135 .name = "isp", 136 .sta_mask = PWR_STATUS_ISP, 137 .ctl_offs = 0x0308, 138 .pwr_sta_offs = 0x0180, 139 .pwr_sta2nd_offs = 0x0184, 140 .sram_pdn_bits = GENMASK(9, 8), 141 .sram_pdn_ack_bits = GENMASK(13, 12), 142 .bp_infracfg = { 143 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, 144 MT8183_TOP_AXI_PROT_EN_MM_SET, 145 MT8183_TOP_AXI_PROT_EN_MM_CLR, 146 MT8183_TOP_AXI_PROT_EN_MM_STA1), 147 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, 148 MT8183_TOP_AXI_PROT_EN_MM_SET, 149 MT8183_TOP_AXI_PROT_EN_MM_CLR, 150 MT8183_TOP_AXI_PROT_EN_MM_STA1), 151 }, 152 .bp_smi = { 153 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, 154 MT8183_SMI_COMMON_CLAMP_EN_SET, 155 MT8183_SMI_COMMON_CLAMP_EN_CLR, 156 MT8183_SMI_COMMON_CLAMP_EN), 157 }, 158 }, 159 [MT8183_POWER_DOMAIN_VDEC] = { 160 .name = "vdec", 161 .sta_mask = BIT(31), 162 .ctl_offs = 0x0300, 163 .pwr_sta_offs = 0x0180, 164 .pwr_sta2nd_offs = 0x0184, 165 .sram_pdn_bits = GENMASK(8, 8), 166 .sram_pdn_ack_bits = GENMASK(12, 12), 167 .bp_smi = { 168 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, 169 MT8183_SMI_COMMON_CLAMP_EN_SET, 170 MT8183_SMI_COMMON_CLAMP_EN_CLR, 171 MT8183_SMI_COMMON_CLAMP_EN), 172 }, 173 }, 174 [MT8183_POWER_DOMAIN_VENC] = { 175 .name = "venc", 176 .sta_mask = PWR_STATUS_VENC, 177 .ctl_offs = 0x0304, 178 .pwr_sta_offs = 0x0180, 179 .pwr_sta2nd_offs = 0x0184, 180 .sram_pdn_bits = GENMASK(11, 8), 181 .sram_pdn_ack_bits = GENMASK(15, 12), 182 .bp_smi = { 183 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, 184 MT8183_SMI_COMMON_CLAMP_EN_SET, 185 MT8183_SMI_COMMON_CLAMP_EN_CLR, 186 MT8183_SMI_COMMON_CLAMP_EN), 187 }, 188 }, 189 [MT8183_POWER_DOMAIN_VPU_TOP] = { 190 .name = "vpu_top", 191 .sta_mask = BIT(26), 192 .ctl_offs = 0x0324, 193 .pwr_sta_offs = 0x0180, 194 .pwr_sta2nd_offs = 0x0184, 195 .sram_pdn_bits = GENMASK(8, 8), 196 .sram_pdn_ack_bits = GENMASK(12, 12), 197 .bp_infracfg = { 198 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, 199 MT8183_TOP_AXI_PROT_EN_MM_SET, 200 MT8183_TOP_AXI_PROT_EN_MM_CLR, 201 MT8183_TOP_AXI_PROT_EN_MM_STA1), 202 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, 203 MT8183_TOP_AXI_PROT_EN_SET, 204 MT8183_TOP_AXI_PROT_EN_CLR, 205 MT8183_TOP_AXI_PROT_EN_STA1), 206 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, 207 MT8183_TOP_AXI_PROT_EN_MM_SET, 208 MT8183_TOP_AXI_PROT_EN_MM_CLR, 209 MT8183_TOP_AXI_PROT_EN_MM_STA1), 210 }, 211 .bp_smi = { 212 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, 213 MT8183_SMI_COMMON_CLAMP_EN_SET, 214 MT8183_SMI_COMMON_CLAMP_EN_CLR, 215 MT8183_SMI_COMMON_CLAMP_EN), 216 }, 217 }, 218 [MT8183_POWER_DOMAIN_VPU_CORE0] = { 219 .name = "vpu_core0", 220 .sta_mask = BIT(27), 221 .ctl_offs = 0x33c, 222 .pwr_sta_offs = 0x0180, 223 .pwr_sta2nd_offs = 0x0184, 224 .sram_pdn_bits = GENMASK(11, 8), 225 .sram_pdn_ack_bits = GENMASK(13, 12), 226 .bp_infracfg = { 227 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, 228 MT8183_TOP_AXI_PROT_EN_MCU_SET, 229 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 230 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 231 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, 232 MT8183_TOP_AXI_PROT_EN_MCU_SET, 233 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 234 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 235 }, 236 .caps = MTK_SCPD_SRAM_ISO, 237 }, 238 [MT8183_POWER_DOMAIN_VPU_CORE1] = { 239 .name = "vpu_core1", 240 .sta_mask = BIT(28), 241 .ctl_offs = 0x0340, 242 .pwr_sta_offs = 0x0180, 243 .pwr_sta2nd_offs = 0x0184, 244 .sram_pdn_bits = GENMASK(11, 8), 245 .sram_pdn_ack_bits = GENMASK(13, 12), 246 .bp_infracfg = { 247 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, 248 MT8183_TOP_AXI_PROT_EN_MCU_SET, 249 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 250 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 251 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, 252 MT8183_TOP_AXI_PROT_EN_MCU_SET, 253 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 254 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 255 }, 256 .caps = MTK_SCPD_SRAM_ISO, 257 }, 258}; 259 260static const struct scpsys_soc_data mt8183_scpsys_data = { 261 .domains_data = scpsys_domain_data_mt8183, 262 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), 263}; 264 265#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */