cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a779f0-sysc.c (1758B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Renesas R-Car S4-8 System Controller
      4 *
      5 * Copyright (C) 2021 Renesas Electronics Corp.
      6 */
      7
      8#include <linux/bits.h>
      9#include <linux/clk/renesas.h>
     10#include <linux/delay.h>
     11#include <linux/err.h>
     12#include <linux/io.h>
     13#include <linux/iopoll.h>
     14#include <linux/kernel.h>
     15#include <linux/mm.h>
     16#include <linux/of_address.h>
     17#include <linux/pm_domain.h>
     18#include <linux/slab.h>
     19#include <linux/spinlock.h>
     20#include <linux/types.h>
     21
     22#include <dt-bindings/power/r8a779f0-sysc.h>
     23
     24#include "rcar-gen4-sysc.h"
     25
     26static struct rcar_gen4_sysc_area r8a779f0_areas[] __initdata = {
     27	{ "always-on",	R8A779F0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
     28	{ "a3e0",	R8A779F0_PD_A3E0, R8A779F0_PD_ALWAYS_ON, PD_SCU },
     29	{ "a3e1",	R8A779F0_PD_A3E1, R8A779F0_PD_ALWAYS_ON, PD_SCU },
     30	{ "a2e0d0",	R8A779F0_PD_A2E0D0, R8A779F0_PD_A3E0, PD_SCU },
     31	{ "a2e0d1",	R8A779F0_PD_A2E0D1, R8A779F0_PD_A3E0, PD_SCU },
     32	{ "a2e1d0",	R8A779F0_PD_A2E1D0, R8A779F0_PD_A3E1, PD_SCU },
     33	{ "a2e1d1",	R8A779F0_PD_A2E1D1, R8A779F0_PD_A3E1, PD_SCU },
     34	{ "a1e0d0c0",	R8A779F0_PD_A1E0D0C0, R8A779F0_PD_A2E0D0, PD_CPU_NOCR },
     35	{ "a1e0d0c1",	R8A779F0_PD_A1E0D0C1, R8A779F0_PD_A2E0D0, PD_CPU_NOCR },
     36	{ "a1e0d1c0",	R8A779F0_PD_A1E0D1C0, R8A779F0_PD_A2E0D1, PD_CPU_NOCR },
     37	{ "a1e0d1c1",	R8A779F0_PD_A1E0D1C1, R8A779F0_PD_A2E0D1, PD_CPU_NOCR },
     38	{ "a1e1d0c0",	R8A779F0_PD_A1E1D0C0, R8A779F0_PD_A2E1D0, PD_CPU_NOCR },
     39	{ "a1e1d0c1",	R8A779F0_PD_A1E1D0C1, R8A779F0_PD_A2E1D0, PD_CPU_NOCR },
     40	{ "a1e1d1c0",	R8A779F0_PD_A1E1D1C0, R8A779F0_PD_A2E1D1, PD_CPU_NOCR },
     41	{ "a1e1d1c1",	R8A779F0_PD_A1E1D1C1, R8A779F0_PD_A2E1D1, PD_CPU_NOCR },
     42};
     43
     44const struct rcar_gen4_sysc_info r8a779f0_sysc_info __initconst = {
     45	.areas = r8a779f0_areas,
     46	.num_areas = ARRAY_SIZE(r8a779f0_areas),
     47};