cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a779g0-sysc.c (2479B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Renesas R-Car V4H System Controller
      4 *
      5 * Copyright (C) 2022 Renesas Electronics Corp.
      6 */
      7
      8#include <linux/bits.h>
      9#include <linux/clk/renesas.h>
     10#include <linux/delay.h>
     11#include <linux/err.h>
     12#include <linux/io.h>
     13#include <linux/iopoll.h>
     14#include <linux/kernel.h>
     15#include <linux/mm.h>
     16#include <linux/of_address.h>
     17#include <linux/pm_domain.h>
     18#include <linux/slab.h>
     19#include <linux/spinlock.h>
     20#include <linux/types.h>
     21
     22#include <dt-bindings/power/r8a779g0-sysc.h>
     23
     24#include "rcar-gen4-sysc.h"
     25
     26static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
     27	{ "always-on",	R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
     28	{ "a3e0",	R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
     29	{ "a2e0d0",	R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
     30	{ "a2e0d1",	R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
     31	{ "a1e0d0c0",	R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
     32	{ "a1e0d0c1",	R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
     33	{ "a1e0d1c0",	R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
     34	{ "a1e0d1c1",	R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
     35	{ "a33dga",	R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
     36	{ "a23dgb",	R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
     37	{ "a3vip0",	R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
     38	{ "a3vip1",	R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
     39	{ "a3vip2",	R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
     40	{ "a3isp0",	R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
     41	{ "a3isp1",	R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
     42	{ "a3ir",	R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
     43	{ "a2cn0",	R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
     44	{ "a1cnn0",	R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
     45	{ "a1dsp0",	R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
     46	{ "a1dsp1",	R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
     47	{ "a1dsp2",	R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
     48	{ "a1dsp3",	R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
     49	{ "a2imp01",	R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
     50	{ "a2imp23",	R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
     51	{ "a2psc",	R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
     52	{ "a2dma",	R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
     53	{ "a2cv0",	R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
     54	{ "a2cv1",	R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
     55	{ "a2cv2",	R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
     56	{ "a2cv3",	R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
     57};
     58
     59const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
     60	.areas = r8a779g0_areas,
     61	.num_areas = ARRAY_SIZE(r8a779g0_areas),
     62};