cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spi-fsl-spi.h (1886B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Freescale SPI controller driver.
      4 *
      5 * Maintainer: Kumar Gala
      6 *
      7 * Copyright (C) 2006 Polycom, Inc.
      8 * Copyright 2010 Freescale Semiconductor, Inc.
      9 *
     10 * CPM SPI and QE buffer descriptors mode support:
     11 * Copyright (c) 2009  MontaVista Software, Inc.
     12 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
     13 *
     14 * GRLIB support:
     15 * Copyright (c) 2012 Aeroflex Gaisler AB.
     16 * Author: Andreas Larsson <andreas@gaisler.com>
     17 */
     18
     19#ifndef __SPI_FSL_SPI_H__
     20#define __SPI_FSL_SPI_H__
     21
     22/* SPI Controller registers */
     23struct fsl_spi_reg {
     24	__be32 cap; /* TYPE_GRLIB specific */
     25	u8 res1[0x1C];
     26	__be32 mode;
     27	__be32 event;
     28	__be32 mask;
     29	__be32 command;
     30	__be32 transmit;
     31	__be32 receive;
     32	__be32 slvsel; /* TYPE_GRLIB specific */
     33};
     34
     35/* SPI Controller mode register definitions */
     36#define	SPMODE_LOOP		(1 << 30)
     37#define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
     38#define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
     39#define	SPMODE_DIV16		(1 << 27)
     40#define	SPMODE_REV		(1 << 26)
     41#define	SPMODE_MS		(1 << 25)
     42#define	SPMODE_ENABLE		(1 << 24)
     43#define	SPMODE_LEN(x)		((x) << 20)
     44#define	SPMODE_PM(x)		((x) << 16)
     45#define	SPMODE_OP		(1 << 14)
     46#define	SPMODE_CG(x)		((x) << 7)
     47
     48/* TYPE_GRLIB SPI Controller capability register definitions */
     49#define SPCAP_SSEN(x)		(((x) >> 16) & 0x1)
     50#define SPCAP_SSSZ(x)		(((x) >> 24) & 0xff)
     51#define SPCAP_MAXWLEN(x)	(((x) >> 20) & 0xf)
     52
     53/*
     54 * Default for SPI Mode:
     55 *	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
     56 */
     57#define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
     58			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
     59
     60/* SPIE register values */
     61#define	SPIE_NE		0x00000200	/* Not empty */
     62#define	SPIE_NF		0x00000100	/* Not full */
     63
     64/* SPIM register values */
     65#define	SPIM_NE		0x00000200	/* Not empty */
     66#define	SPIM_NF		0x00000100	/* Not full */
     67
     68#endif /* __SPI_FSL_SPI_H__ */