ade7854.c (14735B)
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * ADE7854/58/68/78 Polyphase Multifunction Energy Metering IC Driver 4 * 5 * Copyright 2010 Analog Devices Inc. 6 */ 7 8#include <linux/interrupt.h> 9#include <linux/irq.h> 10#include <linux/delay.h> 11#include <linux/mutex.h> 12#include <linux/device.h> 13#include <linux/kernel.h> 14#include <linux/slab.h> 15#include <linux/sysfs.h> 16#include <linux/list.h> 17#include <linux/module.h> 18 19#include <linux/iio/iio.h> 20#include <linux/iio/sysfs.h> 21#include "meter.h" 22#include "ade7854.h" 23 24static ssize_t ade7854_read_8bit(struct device *dev, 25 struct device_attribute *attr, 26 char *buf) 27{ 28 int ret; 29 u32 val = 0; 30 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 31 struct ade7854_state *st = iio_priv(indio_dev); 32 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 33 34 ret = st->read_reg(dev, this_attr->address, &val, 8); 35 if (ret < 0) 36 return ret; 37 38 return sprintf(buf, "%u\n", val); 39} 40 41static ssize_t ade7854_read_16bit(struct device *dev, 42 struct device_attribute *attr, 43 char *buf) 44{ 45 int ret; 46 u32 val = 0; 47 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 48 struct ade7854_state *st = iio_priv(indio_dev); 49 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 50 51 ret = st->read_reg(dev, this_attr->address, &val, 16); 52 if (ret < 0) 53 return ret; 54 55 return sprintf(buf, "%u\n", val); 56} 57 58static ssize_t ade7854_read_24bit(struct device *dev, 59 struct device_attribute *attr, 60 char *buf) 61{ 62 int ret; 63 u32 val; 64 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 65 struct ade7854_state *st = iio_priv(indio_dev); 66 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 67 68 ret = st->read_reg(dev, this_attr->address, &val, 24); 69 if (ret < 0) 70 return ret; 71 72 return sprintf(buf, "%u\n", val); 73} 74 75static ssize_t ade7854_read_32bit(struct device *dev, 76 struct device_attribute *attr, 77 char *buf) 78{ 79 int ret; 80 u32 val = 0; 81 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 82 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 83 struct ade7854_state *st = iio_priv(indio_dev); 84 85 ret = st->read_reg(dev, this_attr->address, &val, 32); 86 if (ret < 0) 87 return ret; 88 89 return sprintf(buf, "%u\n", val); 90} 91 92static ssize_t ade7854_write_8bit(struct device *dev, 93 struct device_attribute *attr, 94 const char *buf, 95 size_t len) 96{ 97 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 98 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 99 struct ade7854_state *st = iio_priv(indio_dev); 100 101 int ret; 102 u8 val; 103 104 ret = kstrtou8(buf, 10, &val); 105 if (ret) 106 goto error_ret; 107 ret = st->write_reg(dev, this_attr->address, val, 8); 108 109error_ret: 110 return ret ? ret : len; 111} 112 113static ssize_t ade7854_write_16bit(struct device *dev, 114 struct device_attribute *attr, 115 const char *buf, 116 size_t len) 117{ 118 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 119 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 120 struct ade7854_state *st = iio_priv(indio_dev); 121 122 int ret; 123 u16 val; 124 125 ret = kstrtou16(buf, 10, &val); 126 if (ret) 127 goto error_ret; 128 ret = st->write_reg(dev, this_attr->address, val, 16); 129 130error_ret: 131 return ret ? ret : len; 132} 133 134static ssize_t ade7854_write_24bit(struct device *dev, 135 struct device_attribute *attr, 136 const char *buf, 137 size_t len) 138{ 139 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 140 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 141 struct ade7854_state *st = iio_priv(indio_dev); 142 143 int ret; 144 u32 val; 145 146 ret = kstrtou32(buf, 10, &val); 147 if (ret) 148 goto error_ret; 149 ret = st->write_reg(dev, this_attr->address, val, 24); 150 151error_ret: 152 return ret ? ret : len; 153} 154 155static ssize_t ade7854_write_32bit(struct device *dev, 156 struct device_attribute *attr, 157 const char *buf, 158 size_t len) 159{ 160 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 161 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 162 struct ade7854_state *st = iio_priv(indio_dev); 163 164 int ret; 165 u32 val; 166 167 ret = kstrtou32(buf, 10, &val); 168 if (ret) 169 goto error_ret; 170 ret = st->write_reg(dev, this_attr->address, val, 32); 171 172error_ret: 173 return ret ? ret : len; 174} 175 176static int ade7854_reset(struct device *dev) 177{ 178 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 179 struct ade7854_state *st = iio_priv(indio_dev); 180 u32 val; 181 182 st->read_reg(dev, ADE7854_CONFIG, &val, 16); 183 val |= BIT(7); /* Software Chip Reset */ 184 185 return st->write_reg(dev, ADE7854_CONFIG, val, 16); 186} 187 188static IIO_DEV_ATTR_AIGAIN(0644, 189 ade7854_read_24bit, 190 ade7854_write_24bit, 191 ADE7854_AIGAIN); 192static IIO_DEV_ATTR_BIGAIN(0644, 193 ade7854_read_24bit, 194 ade7854_write_24bit, 195 ADE7854_BIGAIN); 196static IIO_DEV_ATTR_CIGAIN(0644, 197 ade7854_read_24bit, 198 ade7854_write_24bit, 199 ADE7854_CIGAIN); 200static IIO_DEV_ATTR_NIGAIN(0644, 201 ade7854_read_24bit, 202 ade7854_write_24bit, 203 ADE7854_NIGAIN); 204static IIO_DEV_ATTR_AVGAIN(0644, 205 ade7854_read_24bit, 206 ade7854_write_24bit, 207 ADE7854_AVGAIN); 208static IIO_DEV_ATTR_BVGAIN(0644, 209 ade7854_read_24bit, 210 ade7854_write_24bit, 211 ADE7854_BVGAIN); 212static IIO_DEV_ATTR_CVGAIN(0644, 213 ade7854_read_24bit, 214 ade7854_write_24bit, 215 ADE7854_CVGAIN); 216static IIO_DEV_ATTR_APPARENT_POWER_A_GAIN(0644, 217 ade7854_read_24bit, 218 ade7854_write_24bit, 219 ADE7854_AVAGAIN); 220static IIO_DEV_ATTR_APPARENT_POWER_B_GAIN(0644, 221 ade7854_read_24bit, 222 ade7854_write_24bit, 223 ADE7854_BVAGAIN); 224static IIO_DEV_ATTR_APPARENT_POWER_C_GAIN(0644, 225 ade7854_read_24bit, 226 ade7854_write_24bit, 227 ADE7854_CVAGAIN); 228static IIO_DEV_ATTR_ACTIVE_POWER_A_OFFSET(0644, 229 ade7854_read_24bit, 230 ade7854_write_24bit, 231 ADE7854_AWATTOS); 232static IIO_DEV_ATTR_ACTIVE_POWER_B_OFFSET(0644, 233 ade7854_read_24bit, 234 ade7854_write_24bit, 235 ADE7854_BWATTOS); 236static IIO_DEV_ATTR_ACTIVE_POWER_C_OFFSET(0644, 237 ade7854_read_24bit, 238 ade7854_write_24bit, 239 ADE7854_CWATTOS); 240static IIO_DEV_ATTR_REACTIVE_POWER_A_GAIN(0644, 241 ade7854_read_24bit, 242 ade7854_write_24bit, 243 ADE7854_AVARGAIN); 244static IIO_DEV_ATTR_REACTIVE_POWER_B_GAIN(0644, 245 ade7854_read_24bit, 246 ade7854_write_24bit, 247 ADE7854_BVARGAIN); 248static IIO_DEV_ATTR_REACTIVE_POWER_C_GAIN(0644, 249 ade7854_read_24bit, 250 ade7854_write_24bit, 251 ADE7854_CVARGAIN); 252static IIO_DEV_ATTR_REACTIVE_POWER_A_OFFSET(0644, 253 ade7854_read_24bit, 254 ade7854_write_24bit, 255 ADE7854_AVAROS); 256static IIO_DEV_ATTR_REACTIVE_POWER_B_OFFSET(0644, 257 ade7854_read_24bit, 258 ade7854_write_24bit, 259 ADE7854_BVAROS); 260static IIO_DEV_ATTR_REACTIVE_POWER_C_OFFSET(0644, 261 ade7854_read_24bit, 262 ade7854_write_24bit, 263 ADE7854_CVAROS); 264static IIO_DEV_ATTR_VPEAK(0644, 265 ade7854_read_32bit, 266 ade7854_write_32bit, 267 ADE7854_VPEAK); 268static IIO_DEV_ATTR_IPEAK(0644, 269 ade7854_read_32bit, 270 ade7854_write_32bit, 271 ADE7854_IPEAK); 272static IIO_DEV_ATTR_APHCAL(0644, 273 ade7854_read_16bit, 274 ade7854_write_16bit, 275 ADE7854_APHCAL); 276static IIO_DEV_ATTR_BPHCAL(0644, 277 ade7854_read_16bit, 278 ade7854_write_16bit, 279 ADE7854_BPHCAL); 280static IIO_DEV_ATTR_CPHCAL(0644, 281 ade7854_read_16bit, 282 ade7854_write_16bit, 283 ADE7854_CPHCAL); 284static IIO_DEV_ATTR_CF1DEN(0644, 285 ade7854_read_16bit, 286 ade7854_write_16bit, 287 ADE7854_CF1DEN); 288static IIO_DEV_ATTR_CF2DEN(0644, 289 ade7854_read_16bit, 290 ade7854_write_16bit, 291 ADE7854_CF2DEN); 292static IIO_DEV_ATTR_CF3DEN(0644, 293 ade7854_read_16bit, 294 ade7854_write_16bit, 295 ADE7854_CF3DEN); 296static IIO_DEV_ATTR_LINECYC(0644, 297 ade7854_read_16bit, 298 ade7854_write_16bit, 299 ADE7854_LINECYC); 300static IIO_DEV_ATTR_SAGCYC(0644, 301 ade7854_read_8bit, 302 ade7854_write_8bit, 303 ADE7854_SAGCYC); 304static IIO_DEV_ATTR_CFCYC(0644, 305 ade7854_read_8bit, 306 ade7854_write_8bit, 307 ADE7854_CFCYC); 308static IIO_DEV_ATTR_PEAKCYC(0644, 309 ade7854_read_8bit, 310 ade7854_write_8bit, 311 ADE7854_PEAKCYC); 312static IIO_DEV_ATTR_CHKSUM(ade7854_read_24bit, 313 ADE7854_CHECKSUM); 314static IIO_DEV_ATTR_ANGLE0(ade7854_read_24bit, 315 ADE7854_ANGLE0); 316static IIO_DEV_ATTR_ANGLE1(ade7854_read_24bit, 317 ADE7854_ANGLE1); 318static IIO_DEV_ATTR_ANGLE2(ade7854_read_24bit, 319 ADE7854_ANGLE2); 320static IIO_DEV_ATTR_AIRMS(0444, 321 ade7854_read_24bit, 322 NULL, 323 ADE7854_AIRMS); 324static IIO_DEV_ATTR_BIRMS(0444, 325 ade7854_read_24bit, 326 NULL, 327 ADE7854_BIRMS); 328static IIO_DEV_ATTR_CIRMS(0444, 329 ade7854_read_24bit, 330 NULL, 331 ADE7854_CIRMS); 332static IIO_DEV_ATTR_NIRMS(0444, 333 ade7854_read_24bit, 334 NULL, 335 ADE7854_NIRMS); 336static IIO_DEV_ATTR_AVRMS(0444, 337 ade7854_read_24bit, 338 NULL, 339 ADE7854_AVRMS); 340static IIO_DEV_ATTR_BVRMS(0444, 341 ade7854_read_24bit, 342 NULL, 343 ADE7854_BVRMS); 344static IIO_DEV_ATTR_CVRMS(0444, 345 ade7854_read_24bit, 346 NULL, 347 ADE7854_CVRMS); 348static IIO_DEV_ATTR_AIRMSOS(0444, 349 ade7854_read_16bit, 350 ade7854_write_16bit, 351 ADE7854_AIRMSOS); 352static IIO_DEV_ATTR_BIRMSOS(0444, 353 ade7854_read_16bit, 354 ade7854_write_16bit, 355 ADE7854_BIRMSOS); 356static IIO_DEV_ATTR_CIRMSOS(0444, 357 ade7854_read_16bit, 358 ade7854_write_16bit, 359 ADE7854_CIRMSOS); 360static IIO_DEV_ATTR_AVRMSOS(0444, 361 ade7854_read_16bit, 362 ade7854_write_16bit, 363 ADE7854_AVRMSOS); 364static IIO_DEV_ATTR_BVRMSOS(0444, 365 ade7854_read_16bit, 366 ade7854_write_16bit, 367 ADE7854_BVRMSOS); 368static IIO_DEV_ATTR_CVRMSOS(0444, 369 ade7854_read_16bit, 370 ade7854_write_16bit, 371 ADE7854_CVRMSOS); 372static IIO_DEV_ATTR_VOLT_A(ade7854_read_24bit, 373 ADE7854_VAWV); 374static IIO_DEV_ATTR_VOLT_B(ade7854_read_24bit, 375 ADE7854_VBWV); 376static IIO_DEV_ATTR_VOLT_C(ade7854_read_24bit, 377 ADE7854_VCWV); 378static IIO_DEV_ATTR_CURRENT_A(ade7854_read_24bit, 379 ADE7854_IAWV); 380static IIO_DEV_ATTR_CURRENT_B(ade7854_read_24bit, 381 ADE7854_IBWV); 382static IIO_DEV_ATTR_CURRENT_C(ade7854_read_24bit, 383 ADE7854_ICWV); 384static IIO_DEV_ATTR_AWATTHR(ade7854_read_32bit, 385 ADE7854_AWATTHR); 386static IIO_DEV_ATTR_BWATTHR(ade7854_read_32bit, 387 ADE7854_BWATTHR); 388static IIO_DEV_ATTR_CWATTHR(ade7854_read_32bit, 389 ADE7854_CWATTHR); 390static IIO_DEV_ATTR_AFWATTHR(ade7854_read_32bit, 391 ADE7854_AFWATTHR); 392static IIO_DEV_ATTR_BFWATTHR(ade7854_read_32bit, 393 ADE7854_BFWATTHR); 394static IIO_DEV_ATTR_CFWATTHR(ade7854_read_32bit, 395 ADE7854_CFWATTHR); 396static IIO_DEV_ATTR_AVARHR(ade7854_read_32bit, 397 ADE7854_AVARHR); 398static IIO_DEV_ATTR_BVARHR(ade7854_read_32bit, 399 ADE7854_BVARHR); 400static IIO_DEV_ATTR_CVARHR(ade7854_read_32bit, 401 ADE7854_CVARHR); 402static IIO_DEV_ATTR_AVAHR(ade7854_read_32bit, 403 ADE7854_AVAHR); 404static IIO_DEV_ATTR_BVAHR(ade7854_read_32bit, 405 ADE7854_BVAHR); 406static IIO_DEV_ATTR_CVAHR(ade7854_read_32bit, 407 ADE7854_CVAHR); 408 409static int ade7854_set_irq(struct device *dev, bool enable) 410{ 411 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 412 struct ade7854_state *st = iio_priv(indio_dev); 413 414 int ret; 415 u32 irqen; 416 417 ret = st->read_reg(dev, ADE7854_MASK0, &irqen, 32); 418 if (ret < 0) 419 return ret; 420 421 if (enable) 422 irqen |= BIT(17); /* 1: interrupt enabled when all periodical 423 * (at 8 kHz rate) DSP computations finish. 424 */ 425 else 426 irqen &= ~BIT(17); 427 428 return st->write_reg(dev, ADE7854_MASK0, irqen, 32); 429} 430 431static int ade7854_initial_setup(struct iio_dev *indio_dev) 432{ 433 int ret; 434 struct device *dev = &indio_dev->dev; 435 436 /* Disable IRQ */ 437 ret = ade7854_set_irq(dev, false); 438 if (ret) { 439 dev_err(dev, "disable irq failed"); 440 goto err_ret; 441 } 442 443 ade7854_reset(dev); 444 usleep_range(ADE7854_STARTUP_DELAY, ADE7854_STARTUP_DELAY + 100); 445 446err_ret: 447 return ret; 448} 449 450static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("8000"); 451 452static IIO_CONST_ATTR(name, "ade7854"); 453 454static struct attribute *ade7854_attributes[] = { 455 &iio_dev_attr_aigain.dev_attr.attr, 456 &iio_dev_attr_bigain.dev_attr.attr, 457 &iio_dev_attr_cigain.dev_attr.attr, 458 &iio_dev_attr_nigain.dev_attr.attr, 459 &iio_dev_attr_avgain.dev_attr.attr, 460 &iio_dev_attr_bvgain.dev_attr.attr, 461 &iio_dev_attr_cvgain.dev_attr.attr, 462 &iio_dev_attr_linecyc.dev_attr.attr, 463 &iio_dev_attr_sagcyc.dev_attr.attr, 464 &iio_dev_attr_cfcyc.dev_attr.attr, 465 &iio_dev_attr_peakcyc.dev_attr.attr, 466 &iio_dev_attr_chksum.dev_attr.attr, 467 &iio_dev_attr_apparent_power_a_gain.dev_attr.attr, 468 &iio_dev_attr_apparent_power_b_gain.dev_attr.attr, 469 &iio_dev_attr_apparent_power_c_gain.dev_attr.attr, 470 &iio_dev_attr_active_power_a_offset.dev_attr.attr, 471 &iio_dev_attr_active_power_b_offset.dev_attr.attr, 472 &iio_dev_attr_active_power_c_offset.dev_attr.attr, 473 &iio_dev_attr_reactive_power_a_gain.dev_attr.attr, 474 &iio_dev_attr_reactive_power_b_gain.dev_attr.attr, 475 &iio_dev_attr_reactive_power_c_gain.dev_attr.attr, 476 &iio_dev_attr_reactive_power_a_offset.dev_attr.attr, 477 &iio_dev_attr_reactive_power_b_offset.dev_attr.attr, 478 &iio_dev_attr_reactive_power_c_offset.dev_attr.attr, 479 &iio_dev_attr_awatthr.dev_attr.attr, 480 &iio_dev_attr_bwatthr.dev_attr.attr, 481 &iio_dev_attr_cwatthr.dev_attr.attr, 482 &iio_dev_attr_afwatthr.dev_attr.attr, 483 &iio_dev_attr_bfwatthr.dev_attr.attr, 484 &iio_dev_attr_cfwatthr.dev_attr.attr, 485 &iio_dev_attr_avarhr.dev_attr.attr, 486 &iio_dev_attr_bvarhr.dev_attr.attr, 487 &iio_dev_attr_cvarhr.dev_attr.attr, 488 &iio_dev_attr_angle0.dev_attr.attr, 489 &iio_dev_attr_angle1.dev_attr.attr, 490 &iio_dev_attr_angle2.dev_attr.attr, 491 &iio_dev_attr_avahr.dev_attr.attr, 492 &iio_dev_attr_bvahr.dev_attr.attr, 493 &iio_dev_attr_cvahr.dev_attr.attr, 494 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 495 &iio_const_attr_name.dev_attr.attr, 496 &iio_dev_attr_vpeak.dev_attr.attr, 497 &iio_dev_attr_ipeak.dev_attr.attr, 498 &iio_dev_attr_aphcal.dev_attr.attr, 499 &iio_dev_attr_bphcal.dev_attr.attr, 500 &iio_dev_attr_cphcal.dev_attr.attr, 501 &iio_dev_attr_cf1den.dev_attr.attr, 502 &iio_dev_attr_cf2den.dev_attr.attr, 503 &iio_dev_attr_cf3den.dev_attr.attr, 504 &iio_dev_attr_airms.dev_attr.attr, 505 &iio_dev_attr_birms.dev_attr.attr, 506 &iio_dev_attr_cirms.dev_attr.attr, 507 &iio_dev_attr_nirms.dev_attr.attr, 508 &iio_dev_attr_avrms.dev_attr.attr, 509 &iio_dev_attr_bvrms.dev_attr.attr, 510 &iio_dev_attr_cvrms.dev_attr.attr, 511 &iio_dev_attr_airmsos.dev_attr.attr, 512 &iio_dev_attr_birmsos.dev_attr.attr, 513 &iio_dev_attr_cirmsos.dev_attr.attr, 514 &iio_dev_attr_avrmsos.dev_attr.attr, 515 &iio_dev_attr_bvrmsos.dev_attr.attr, 516 &iio_dev_attr_cvrmsos.dev_attr.attr, 517 &iio_dev_attr_volt_a.dev_attr.attr, 518 &iio_dev_attr_volt_b.dev_attr.attr, 519 &iio_dev_attr_volt_c.dev_attr.attr, 520 &iio_dev_attr_current_a.dev_attr.attr, 521 &iio_dev_attr_current_b.dev_attr.attr, 522 &iio_dev_attr_current_c.dev_attr.attr, 523 NULL, 524}; 525 526static const struct attribute_group ade7854_attribute_group = { 527 .attrs = ade7854_attributes, 528}; 529 530static const struct iio_info ade7854_info = { 531 .attrs = &ade7854_attribute_group, 532}; 533 534int ade7854_probe(struct iio_dev *indio_dev, struct device *dev) 535{ 536 int ret; 537 struct ade7854_state *st = iio_priv(indio_dev); 538 /* setup the industrialio driver allocated elements */ 539 mutex_init(&st->buf_lock); 540 541 indio_dev->dev.parent = dev; 542 indio_dev->info = &ade7854_info; 543 indio_dev->modes = INDIO_DIRECT_MODE; 544 545 ret = devm_iio_device_register(dev, indio_dev); 546 if (ret) 547 return ret; 548 549 /* Get the device into a sane initial state */ 550 return ade7854_initial_setup(indio_dev); 551} 552EXPORT_SYMBOL(ade7854_probe); 553 554MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); 555MODULE_DESCRIPTION("Analog Devices ADE7854/58/68/78 Polyphase Energy Meter"); 556MODULE_LICENSE("GPL v2");