Hal8188EPwrSeq.c (2305B)
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4#include "../include/Hal8188EPwrSeq.h" 5#include "../include/rtl8188e_hal.h" 6 7struct wl_pwr_cfg rtl8188E_power_on_flow[] = { 8 { 0x0006, PWR_CMD_POLLING, BIT(1), BIT(1) }, 9 { 0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0 }, /* reset BB */ 10 { 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */ 11 { 0x0005, PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN (control by DRV)*/ 12 { 0x0005, PWR_CMD_WRITE, BIT(4) | BIT(3), 0 }, /* disable WL suspend*/ 13 { 0x0005, PWR_CMD_WRITE, BIT(0), BIT(0) }, 14 { 0x0005, PWR_CMD_POLLING, BIT(0), 0 }, 15 { 0x0023, PWR_CMD_WRITE, BIT(4), 0 }, 16 { 0xFFFF, PWR_CMD_END, 0, 0 }, 17}; 18 19struct wl_pwr_cfg rtl8188E_card_disable_flow[] = { 20 { 0x001F, PWR_CMD_WRITE, 0xFF, 0 }, /* turn off RF */ 21 { 0x0023, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* LDO Sleep mode */ 22 { 0x0005, PWR_CMD_WRITE, BIT(1), BIT(1) }, /* turn off MAC by HW state machine */ 23 { 0x0005, PWR_CMD_POLLING, BIT(1), 0 }, 24 { 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */ 25 { 0x0005, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /* enable WL suspend */ 26 { 0x0007, PWR_CMD_WRITE, 0xFF, 0 }, /* enable bandgap mbias in suspend */ 27 { 0x0041, PWR_CMD_WRITE, BIT(4), 0 }, /* Clear SIC_EN register */ 28 { 0xfe10, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* Set USB suspend enable local register */ 29 { 0xFFFF, PWR_CMD_END, 0, 0 }, 30}; 31 32/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ 33struct wl_pwr_cfg rtl8188E_enter_lps_flow[] = { 34 { 0x0522, PWR_CMD_WRITE, 0xFF, 0x7F },/* Tx Pause */ 35 { 0x05F8, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ 36 { 0x05F9, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ 37 { 0x05FA, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ 38 { 0x05FB, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ 39 { 0x0002, PWR_CMD_WRITE, BIT(0), 0 }, /* CCK and OFDM are disabled, clocks are gated */ 40 { 0x0002, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US }, 41 { 0x0100, PWR_CMD_WRITE, 0xFF, 0x3F }, /* Reset MAC TRX */ 42 { 0x0101, PWR_CMD_WRITE, BIT(1), 0 }, /* check if removed later */ 43 { 0x0553, PWR_CMD_WRITE, BIT(5), BIT(5) }, /* Respond TxOK to scheduler */ 44 { 0xFFFF, PWR_CMD_END, 0, 0 }, 45};