cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

r819xU_cmdpkt.h (4562B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef R819XUSB_CMDPKT_H
      3#define R819XUSB_CMDPKT_H
      4/* Different command packet have dedicated message length and definition. */
      5#define		CMPK_RX_TX_FB_SIZE		sizeof(struct cmd_pkt_tx_feedback)	/* 20 */
      6#define		CMPK_BOTH_QUERY_CONFIG_SIZE	sizeof(struct cmd_pkt_set_configuration)	/* 16 */
      7#define		CMPK_RX_TX_STS_SIZE		sizeof(cmpk_tx_status_t)
      8#define		CMPK_TX_RAHIS_SIZE		sizeof(cmpk_tx_rahis_t)
      9
     10/* 2008/05/08 amy For USB constant. */
     11#define ISR_TX_BCN_OK		BIT(27)		/* Transmit Beacon OK */
     12#define ISR_TX_BCN_ERR		BIT(26)		/* Transmit Beacon Error */
     13#define ISR_BCN_TIMER_INTR	BIT(13)		/* Beacon Timer Interrupt */
     14
     15/* Define element ID of command packet. */
     16
     17/*------------------------------Define structure----------------------------*/
     18/* Define different command packet structure. */
     19/* 1. RX side: TX feedback packet. */
     20struct cmd_pkt_tx_feedback {
     21	/* DWORD 0 */
     22	u8	element_id;			/* Command packet type. */
     23	u8	length;				/* Command packet length. */
     24	/* Change tx feedback info field. */
     25	/*------TX Feedback Info Field */
     26	u8	TID:4;
     27	u8	fail_reason:3;
     28	u8	tok:1;				/* Transmit ok. */
     29	u8	reserve1:4;
     30	u8	pkt_type:2;
     31	u8	bandwidth:1;
     32	u8	qos_pkt:1;
     33
     34	/* DWORD 1 */
     35	u8	reserve2;
     36	/*------TX Feedback Info Field */
     37	u8	retry_cnt;
     38	u16	pkt_id;
     39
     40	/* DWORD 3 */
     41	u16	seq_num;
     42	u8	s_rate;				/* Start rate. */
     43	u8	f_rate;				/* Final rate. */
     44
     45	/* DWORD 4 */
     46	u8	s_rts_rate;
     47	u8	f_rts_rate;
     48	u16	pkt_length;
     49
     50	/* DWORD 5 */
     51	u16	reserve3;
     52	u16	duration;
     53};
     54
     55/* 2. RX side: Interrupt status packet. It includes Beacon State,
     56 * Beacon Timer Interrupt and other useful information in MAC ISR Reg.
     57 */
     58struct cmd_pkt_interrupt_status {
     59	u8	element_id;			/* Command packet type. */
     60	u8	length;				/* Command packet length. */
     61	u16	reserve;
     62	u32	interrupt_status;		/* Interrupt Status. */
     63};
     64
     65/* 3. TX side: Set configuration packet. */
     66struct cmd_pkt_set_configuration {
     67	u8	element_id;			/* Command packet type. */
     68	u8	length;				/* Command packet length. */
     69	u16	reserve1;
     70	/* Configuration info. */
     71	u8	cfg_reserve1:3;
     72	u8	cfg_size:2;
     73	u8	cfg_type:2;
     74	u8	cfg_action:1;
     75	u8	cfg_reserve2;
     76	u8	cfg_page:4;
     77	u8	cfg_reserve3:4;
     78	u8	cfg_offset;
     79	u32	value;
     80	u32	mask;
     81};
     82
     83/* 4. Both side : TX/RX query configuration packet. The query structure is the
     84 *    same as set configuration.
     85 */
     86#define		cmpk_query_cfg	cmd_pkt_set_configuration
     87
     88/* 5. Multi packet feedback status. */
     89typedef struct tag_tx_stats_feedback {
     90	/* For endian transfer --> Driver will not the same as
     91	 *  firmware structure.
     92	 */
     93	/* DW 0 */
     94	u16	reserve1;
     95	u8	length;				/* Command packet length */
     96	u8	element_id;			/* Command packet type */
     97
     98	/* DW 1 */
     99	u16	txfail;				/* Tx fail count */
    100	u16	txok;				/* Tx ok count */
    101
    102	/* DW 2 */
    103	u16	txmcok;				/* Tx multicast */
    104	u16	txretry;			/* Tx retry count */
    105
    106	/* DW 3 */
    107	u16	txucok;				/* Tx unicast */
    108	u16	txbcok;				/* Tx broadcast */
    109
    110	/* DW 4 */
    111	u16	txbcfail;
    112	u16	txmcfail;
    113
    114	/* DW 5 */
    115	u16	reserve2;
    116	u16	txucfail;
    117
    118	/* DW 6-8 */
    119	u32	txmclength;
    120	u32	txbclength;
    121	u32	txuclength;
    122
    123	/* DW 9 */
    124	u16	reserve3_23;
    125	u8	reserve3_1;
    126	u8	rate;
    127} __packed cmpk_tx_status_t;
    128
    129/* 6. Debug feedback message. */
    130/* Define RX debug message  */
    131typedef struct tag_rx_debug_message_feedback {
    132	/* For endian transfer --> for driver */
    133	/* DW 0 */
    134	u16	reserve1;
    135	u8	length;				/* Command packet length */
    136	u8	element_id;			/* Command packet type */
    137
    138	/* DW 1-?? */
    139	/* Variable debug message. */
    140
    141} cmpk_rx_dbginfo_t;
    142
    143/* Define transmit rate history. For big endian format. */
    144typedef struct tag_tx_rate_history {
    145	/* For endian transfer --> for driver */
    146	/* DW 0 */
    147	u8	element_id;			/* Command packet type */
    148	u8	length;				/* Command packet length */
    149	u16	reserved1;
    150
    151	/* DW 1-2	CCK rate counter */
    152	u16	cck[4];
    153
    154	/* DW 3-6 */
    155	u16	ofdm[8];
    156
    157	/* DW 7-14	BW=0 SG=0
    158	 * DW 15-22	BW=1 SG=0
    159	 * DW 23-30	BW=0 SG=1
    160	 * DW 31-38	BW=1 SG=1
    161	 */
    162	u16	ht_mcs[4][16];
    163
    164} __packed cmpk_tx_rahis_t;
    165
    166typedef enum tag_command_packet_directories {
    167	RX_TX_FEEDBACK			= 0,
    168	RX_INTERRUPT_STATUS		= 1,
    169	TX_SET_CONFIG			= 2,
    170	BOTH_QUERY_CONFIG		= 3,
    171	RX_TX_STATUS			= 4,
    172	RX_DBGINFO_FEEDBACK		= 5,
    173	RX_TX_PER_PKT_FEEDBACK		= 6,
    174	RX_TX_RATE_HISTORY		= 7,
    175	RX_CMD_ELE_MAX
    176} cmpk_element_e;
    177
    178typedef enum _rt_status {
    179	RT_STATUS_SUCCESS,
    180	RT_STATUS_FAILURE,
    181	RT_STATUS_PENDING,
    182	RT_STATUS_RESOURCE
    183} rt_status, *prt_status;
    184
    185u32 cmpk_message_handle_rx(struct net_device *dev,
    186			   struct ieee80211_rx_stats *pstats);
    187rt_status SendTxCommandPacket(struct net_device *dev,
    188			      void *pData, u32 DataLen);
    189
    190#endif