cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rtl8712_spec.h (4120B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/******************************************************************************
      3 *
      4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
      5 *
      6 * Modifications for inclusion into the Linux staging tree are
      7 * Copyright(c) 2010 Larry Finger. All rights reserved.
      8 *
      9 * Contact information:
     10 * WLAN FAE <wlanfae@realtek.com>
     11 * Larry Finger <Larry.Finger@lwfinger.net>
     12 *
     13 ******************************************************************************/
     14#ifndef __RTL8712_SPEC_H__
     15#define __RTL8712_SPEC_H__
     16
     17#define RTL8712_IOBASE_TXPKT		0x10200000	/*IOBASE_TXPKT*/
     18#define RTL8712_IOBASE_RXPKT		0x10210000	/*IOBASE_RXPKT*/
     19#define RTL8712_IOBASE_RXCMD		0x10220000	/*IOBASE_RXCMD*/
     20#define RTL8712_IOBASE_TXSTATUS		0x10230000	/*IOBASE_TXSTATUS*/
     21#define RTL8712_IOBASE_RXSTATUS		0x10240000	/*IOBASE_RXSTATUS*/
     22#define RTL8712_IOBASE_IOREG		0x10250000	/*IOBASE_IOREG ADDR*/
     23#define RTL8712_IOBASE_SCHEDULER	0x10260000	/*IOBASE_SCHEDULE*/
     24
     25#define RTL8712_IOBASE_TRXDMA		0x10270000	/*IOBASE_TRXDMA*/
     26#define RTL8712_IOBASE_TXLLT		0x10280000	/*IOBASE_TXLLT*/
     27#define RTL8712_IOBASE_WMAC		0x10290000	/*IOBASE_WMAC*/
     28#define RTL8712_IOBASE_FW2HW		0x102A0000	/*IOBASE_FW2HW*/
     29#define RTL8712_IOBASE_ACCESS_PHYREG	0x102B0000	/*IOBASE_ACCESS_PHYREG*/
     30
     31#define RTL8712_IOBASE_FF	0x10300000 /*IOBASE_FIFO 0x1031000~0x103AFFFF*/
     32
     33/*IOREG Offset for 8712*/
     34#define RTL8712_SYSCFG_		RTL8712_IOBASE_IOREG
     35#define RTL8712_CMDCTRL_	(RTL8712_IOBASE_IOREG + 0x40)
     36#define RTL8712_MACIDSETTING_	(RTL8712_IOBASE_IOREG + 0x50)
     37#define RTL8712_TIMECTRL_	(RTL8712_IOBASE_IOREG + 0x80)
     38#define RTL8712_FIFOCTRL_	(RTL8712_IOBASE_IOREG + 0xA0)
     39#define RTL8712_RATECTRL_	(RTL8712_IOBASE_IOREG + 0x160)
     40#define RTL8712_EDCASETTING_	(RTL8712_IOBASE_IOREG + 0x1D0)
     41#define RTL8712_WMAC_		(RTL8712_IOBASE_IOREG + 0x200)
     42#define RTL8712_SECURITY_	(RTL8712_IOBASE_IOREG + 0x240)
     43#define RTL8712_POWERSAVE_	(RTL8712_IOBASE_IOREG + 0x260)
     44#define RTL8712_GP_		(RTL8712_IOBASE_IOREG + 0x2E0)
     45#define RTL8712_INTERRUPT_	(RTL8712_IOBASE_IOREG + 0x300)
     46#define RTL8712_DEBUGCTRL_	(RTL8712_IOBASE_IOREG + 0x310)
     47#define RTL8712_OFFLOAD_	(RTL8712_IOBASE_IOREG + 0x2D0)
     48
     49/*FIFO for 8712*/
     50#define RTL8712_DMA_BCNQ	(RTL8712_IOBASE_FF + 0x10000)
     51#define RTL8712_DMA_MGTQ	(RTL8712_IOBASE_FF + 0x20000)
     52#define RTL8712_DMA_BMCQ	(RTL8712_IOBASE_FF + 0x30000)
     53#define RTL8712_DMA_VOQ		(RTL8712_IOBASE_FF + 0x40000)
     54#define RTL8712_DMA_VIQ		(RTL8712_IOBASE_FF + 0x50000)
     55#define RTL8712_DMA_BEQ		(RTL8712_IOBASE_FF + 0x60000)
     56#define RTL8712_DMA_BKQ		(RTL8712_IOBASE_FF + 0x70000)
     57#define RTL8712_DMA_RX0FF	(RTL8712_IOBASE_FF + 0x80000)
     58#define RTL8712_DMA_H2CCMD	(RTL8712_IOBASE_FF + 0x90000)
     59#define RTL8712_DMA_C2HCMD	(RTL8712_IOBASE_FF + 0xA0000)
     60
     61/*------------------------------*/
     62
     63/*BIT 16 15*/
     64#define	DID_SDIO_LOCAL			0	/* 0 0*/
     65#define	DID_WLAN_IOREG			1	/* 0 1*/
     66#define	DID_WLAN_FIFO			3	/* 1 1*/
     67#define   DID_UNDEFINE				(-1)
     68
     69#define CMD_ADDR_MAPPING_SHIFT		2	/*SDIO CMD ADDR MAPPING,
     70						 *shift 2 bit for match
     71						 * offset[14:2]
     72						 */
     73
     74/*Offset for SDIO LOCAL*/
     75#define	OFFSET_SDIO_LOCAL				0x0FFF
     76
     77/*Offset for WLAN IOREG*/
     78#define OFFSET_WLAN_IOREG				0x0FFF
     79
     80/*Offset for WLAN FIFO*/
     81#define	OFFSET_TX_BCNQ				0x0300
     82#define	OFFSET_TX_HIQ					0x0310
     83#define	OFFSET_TX_CMDQ				0x0320
     84#define	OFFSET_TX_MGTQ				0x0330
     85#define	OFFSET_TX_HCCAQ				0x0340
     86#define	OFFSET_TX_VOQ					0x0350
     87#define	OFFSET_TX_VIQ					0x0360
     88#define	OFFSET_TX_BEQ					0x0370
     89#define	OFFSET_TX_BKQ					0x0380
     90#define	OFFSET_RX_RX0FFQ				0x0390
     91#define	OFFSET_RX_C2HFFQ				0x03A0
     92
     93#define	BK_QID_01	1
     94#define	BK_QID_02	2
     95#define	BE_QID_01	0
     96#define	BE_QID_02	3
     97#define	VI_QID_01	4
     98#define	VI_QID_02	5
     99#define	VO_QID_01	6
    100#define	VO_QID_02	7
    101#define	HCCA_QID_01	8
    102#define	HCCA_QID_02	9
    103#define	HCCA_QID_03	10
    104#define	HCCA_QID_04	11
    105#define	HCCA_QID_05	12
    106#define	HCCA_QID_06	13
    107#define	HCCA_QID_07	14
    108#define	HCCA_QID_08	15
    109#define	HI_QID		17
    110#define	CMD_QID	19
    111#define	MGT_QID	18
    112#define	BCN_QID	16
    113
    114#include "rtl8712_regdef.h"
    115
    116#include "rtl8712_bitdef.h"
    117
    118#include "basic_types.h"
    119
    120#endif /* __RTL8712_SPEC_H__ */
    121