cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rtl871x_pwrctrl.h (3154B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/******************************************************************************
      3 *
      4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
      5 *
      6 * Modifications for inclusion into the Linux staging tree are
      7 * Copyright(c) 2010 Larry Finger. All rights reserved.
      8 *
      9 * Contact information:
     10 * WLAN FAE <wlanfae@realtek.com>
     11 * Larry Finger <Larry.Finger@lwfinger.net>
     12 *
     13 ******************************************************************************/
     14#ifndef __RTL871X_PWRCTRL_H_
     15#define __RTL871X_PWRCTRL_H_
     16
     17#include "osdep_service.h"
     18#include "drv_types.h"
     19
     20#define CMD_ALIVE	BIT(2)
     21
     22enum Power_Mgnt {
     23	PS_MODE_ACTIVE	= 0,
     24	PS_MODE_MIN,
     25	PS_MODE_MAX,
     26	PS_MODE_DTIM,
     27	PS_MODE_VOIP,
     28	PS_MODE_UAPSD_WMM,
     29	PS_MODE_UAPSD,
     30	PS_MODE_IBSS,
     31	PS_MODE_WWLAN,
     32	PM_Radio_Off,
     33	PM_Card_Disable,
     34	PS_MODE_NUM
     35};
     36
     37/*
     38 * BIT[2:0] = HW state
     39 * BIT[3] = Protocol PS state, 0: register active state,
     40 *				1: register sleep state
     41 * BIT[4] = sub-state
     42 */
     43
     44#define		PS_DPS				BIT(0)
     45#define		PS_LCLK				(PS_DPS)
     46#define	PS_RF_OFF			BIT(1)
     47#define	PS_ALL_ON			BIT(2)
     48#define	PS_ST_ACTIVE		BIT(3)
     49#define	PS_LP				BIT(4)	/* low performance */
     50
     51#define	PS_STATE_MASK		(0x0F)
     52#define	PS_STATE_HW_MASK	(0x07)
     53#define		PS_SEQ_MASK		(0xc0)
     54
     55#define	PS_STATE(x)			(PS_STATE_MASK & (x))
     56#define	PS_STATE_HW(x)	(PS_STATE_HW_MASK & (x))
     57#define	PS_SEQ(x)			(PS_SEQ_MASK & (x))
     58
     59#define	PS_STATE_S0		(PS_DPS)
     60#define		PS_STATE_S1		(PS_LCLK)
     61#define	PS_STATE_S2		(PS_RF_OFF)
     62#define		PS_STATE_S3		(PS_ALL_ON)
     63#define	PS_STATE_S4		((PS_ST_ACTIVE) | (PS_ALL_ON))
     64
     65#define		PS_IS_RF_ON(x)		((x) & (PS_ALL_ON))
     66#define		PS_IS_ACTIVE(x)		((x) & (PS_ST_ACTIVE))
     67#define		CLR_PS_STATE(x)	((x) = ((x) & (0xF0)))
     68
     69struct reportpwrstate_parm {
     70	unsigned char mode;
     71	unsigned char state; /* the CPWM value */
     72	unsigned short rsvd;
     73};
     74
     75struct	pwrctrl_priv {
     76	struct mutex mutex_lock;
     77	/*volatile*/ u8 rpwm; /* requested power state for fw */
     78	/* fw current power state. updated when 1. read from HCPWM or
     79	 * 2. driver lowers power level
     80	 */
     81	/*volatile*/ u8 cpwm;
     82	/*volatile*/ u8 tog; /* toggling */
     83	/*volatile*/ u8 cpwm_tog; /* toggling */
     84	/*volatile*/ u8 tgt_rpwm; /* wanted power state */
     85	uint pwr_mode;
     86	uint smart_ps;
     87	uint alives;
     88	uint ImrContent;	/* used to store original imr. */
     89	uint bSleep; /* sleep -> active is different from active -> sleep. */
     90
     91	struct work_struct SetPSModeWorkItem;
     92	struct work_struct rpwm_workitem;
     93	struct timer_list rpwm_check_timer;
     94	u8	rpwm_retry;
     95	uint	bSetPSModeWorkItemInProgress;
     96
     97	spinlock_t pnp_pwr_mgnt_lock;
     98	s32	pnp_current_pwr_state;
     99	u8	pnp_bstop_trx;
    100	u8	pnp_wwirp_pending;
    101};
    102
    103void r8712_init_pwrctrl_priv(struct _adapter *adapter);
    104int r8712_register_cmd_alive(struct _adapter *padapter);
    105void r8712_unregister_cmd_alive(struct _adapter *padapter);
    106void r8712_cpwm_int_hdl(struct _adapter *padapter,
    107			struct reportpwrstate_parm *preportpwrstate);
    108void r8712_set_ps_mode(struct _adapter *padapter, uint ps_mode,
    109			uint smart_ps);
    110void r8712_set_rpwm(struct _adapter *padapter, u8 val8);
    111void r8712_flush_rwctrl_works(struct _adapter *padapter);
    112
    113#endif  /* __RTL871X_PWRCTRL_H_ */