cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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channel.c (3728B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
      4 * All rights reserved.
      5 *
      6 */
      7
      8#include "baseband.h"
      9#include "channel.h"
     10#include "device.h"
     11#include "rf.h"
     12
     13static struct ieee80211_rate vnt_rates_bg[] = {
     14	{ .bitrate = 10,  .hw_value = RATE_1M },
     15	{ .bitrate = 20,  .hw_value = RATE_2M },
     16	{ .bitrate = 55,  .hw_value = RATE_5M },
     17	{ .bitrate = 110, .hw_value = RATE_11M },
     18	{ .bitrate = 60,  .hw_value = RATE_6M },
     19	{ .bitrate = 90,  .hw_value = RATE_9M },
     20	{ .bitrate = 120, .hw_value = RATE_12M },
     21	{ .bitrate = 180, .hw_value = RATE_18M },
     22	{ .bitrate = 240, .hw_value = RATE_24M },
     23	{ .bitrate = 360, .hw_value = RATE_36M },
     24	{ .bitrate = 480, .hw_value = RATE_48M },
     25	{ .bitrate = 540, .hw_value = RATE_54M },
     26};
     27
     28static struct ieee80211_channel vnt_channels_2ghz[] = {
     29	{ .center_freq = 2412, .hw_value = 1 },
     30	{ .center_freq = 2417, .hw_value = 2 },
     31	{ .center_freq = 2422, .hw_value = 3 },
     32	{ .center_freq = 2427, .hw_value = 4 },
     33	{ .center_freq = 2432, .hw_value = 5 },
     34	{ .center_freq = 2437, .hw_value = 6 },
     35	{ .center_freq = 2442, .hw_value = 7 },
     36	{ .center_freq = 2447, .hw_value = 8 },
     37	{ .center_freq = 2452, .hw_value = 9 },
     38	{ .center_freq = 2457, .hw_value = 10 },
     39	{ .center_freq = 2462, .hw_value = 11 },
     40	{ .center_freq = 2467, .hw_value = 12 },
     41	{ .center_freq = 2472, .hw_value = 13 },
     42	{ .center_freq = 2484, .hw_value = 14 }
     43};
     44
     45static struct ieee80211_supported_band vnt_supported_2ghz_band = {
     46	.channels = vnt_channels_2ghz,
     47	.n_channels = ARRAY_SIZE(vnt_channels_2ghz),
     48	.bitrates = vnt_rates_bg,
     49	.n_bitrates = ARRAY_SIZE(vnt_rates_bg),
     50};
     51
     52static void vnt_init_band(struct vnt_private *priv,
     53			  struct ieee80211_supported_band *supported_band,
     54			  enum nl80211_band band)
     55{
     56	int i;
     57
     58	for (i = 0; i < supported_band->n_channels; i++) {
     59		supported_band->channels[i].max_power = 0x3f;
     60		supported_band->channels[i].flags =
     61			IEEE80211_CHAN_NO_HT40;
     62	}
     63
     64	priv->hw->wiphy->bands[band] = supported_band;
     65}
     66
     67void vnt_init_bands(struct vnt_private *priv)
     68{
     69	vnt_init_band(priv, &vnt_supported_2ghz_band, NL80211_BAND_2GHZ);
     70}
     71
     72/**
     73 * set_channel() - Set NIC media channel
     74 *
     75 * @priv: The adapter to be set
     76 * @ch: Channel to be set
     77 *
     78 * Return Value: true if succeeded; false if failed.
     79 *
     80 */
     81bool set_channel(struct vnt_private *priv, struct ieee80211_channel *ch)
     82{
     83	bool ret = true;
     84
     85	if (priv->byCurrentCh == ch->hw_value)
     86		return ret;
     87
     88	/* Set VGA to max sensitivity */
     89	if (priv->bUpdateBBVGA &&
     90	    priv->byBBVGACurrent != priv->abyBBVGA[0]) {
     91		priv->byBBVGACurrent = priv->abyBBVGA[0];
     92
     93		bb_set_vga_gain_offset(priv, priv->byBBVGACurrent);
     94	}
     95
     96	/* clear NAV */
     97	MACvRegBitsOn(priv->port_offset, MAC_REG_MACCR, MACCR_CLRNAV);
     98
     99	/* TX_PE will reserve 3 us for MAX2829 A mode only,
    100	 * it is for better TX throughput
    101	 */
    102
    103	priv->byCurrentCh = ch->hw_value;
    104	ret &= RFbSelectChannel(priv, priv->byRFType,
    105				ch->hw_value);
    106
    107	/* Init Synthesizer Table */
    108	if (priv->bEnablePSMode)
    109		rf_write_wake_prog_syn(priv, priv->byRFType, ch->hw_value);
    110
    111	bb_software_reset(priv);
    112
    113	if (priv->local_id > REV_ID_VT3253_B1) {
    114		unsigned long flags;
    115
    116		spin_lock_irqsave(&priv->lock, flags);
    117
    118		/* set HW default power register */
    119		MACvSelectPage1(priv->port_offset);
    120		RFbSetPower(priv, RATE_1M, priv->byCurrentCh);
    121		iowrite8(priv->byCurPwr, priv->port_offset + MAC_REG_PWRCCK);
    122		RFbSetPower(priv, RATE_6M, priv->byCurrentCh);
    123		iowrite8(priv->byCurPwr, priv->port_offset + MAC_REG_PWROFDM);
    124		MACvSelectPage0(priv->port_offset);
    125
    126		spin_unlock_irqrestore(&priv->lock, flags);
    127	}
    128
    129	if (priv->byBBType == BB_TYPE_11B)
    130		RFbSetPower(priv, RATE_1M, priv->byCurrentCh);
    131	else
    132		RFbSetPower(priv, RATE_6M, priv->byCurrentCh);
    133
    134	return ret;
    135}