cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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desc.h (6116B)


      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
      4 * All rights reserved.
      5 *
      6 * Purpose:The header file of descriptor
      7 *
      8 * Revision History:
      9 *
     10 * Author: Tevin Chen
     11 *
     12 * Date: May 21, 1996
     13 *
     14 */
     15
     16#ifndef __DESC_H__
     17#define __DESC_H__
     18
     19#include <linux/types.h>
     20#include <linux/mm.h>
     21#include "linux/ieee80211.h"
     22
     23#define B_OWNED_BY_CHIP     1
     24#define B_OWNED_BY_HOST     0
     25
     26/* Bits in the RSR register */
     27#define RSR_ADDRBROAD       0x80
     28#define RSR_ADDRMULTI       0x40
     29#define RSR_ADDRUNI         0x00
     30#define RSR_IVLDTYP         0x20
     31#define RSR_IVLDLEN         0x10        /* invalid len (> 2312 byte) */
     32#define RSR_BSSIDOK         0x08
     33#define RSR_CRCOK           0x04
     34#define RSR_BCNSSIDOK       0x02
     35#define RSR_ADDROK          0x01
     36
     37/* Bits in the new RSR register */
     38#define NEWRSR_DECRYPTOK    0x10
     39#define NEWRSR_CFPIND       0x08
     40#define NEWRSR_HWUTSF       0x04
     41#define NEWRSR_BCNHITAID    0x02
     42#define NEWRSR_BCNHITAID0   0x01
     43
     44/* Bits in the TSR0 register */
     45#define TSR0_PWRSTS1_2      0xC0
     46#define TSR0_PWRSTS7        0x20
     47#define TSR0_NCR            0x1F
     48
     49/* Bits in the TSR1 register */
     50#define TSR1_TERR           0x80
     51#define TSR1_PWRSTS4_6      0x70
     52#define TSR1_RETRYTMO       0x08
     53#define TSR1_TMO            0x04
     54#define TSR1_PWRSTS3        0x02
     55#define ACK_DATA            0x01
     56
     57/* Bits in the TCR register */
     58#define EDMSDU              0x04        /* end of sdu */
     59#define TCR_EDP             0x02        /* end of packet */
     60#define TCR_STP             0x01        /* start of packet */
     61
     62/* max transmit or receive buffer size */
     63#define CB_MAX_BUF_SIZE     2900U
     64					/* NOTE: must be multiple of 4 */
     65#define CB_MAX_TX_BUF_SIZE          CB_MAX_BUF_SIZE
     66#define CB_MAX_RX_BUF_SIZE_NORMAL   CB_MAX_BUF_SIZE
     67
     68#define CB_BEACON_BUF_SIZE  512U
     69
     70#define CB_MAX_RX_DESC      128
     71#define CB_MIN_RX_DESC      16
     72#define CB_MAX_TX_DESC      64
     73#define CB_MIN_TX_DESC      16
     74
     75#define CB_MAX_RECEIVED_PACKETS     16
     76				/*
     77				 * limit our receive routine to indicating
     78				 * this many at a time for 2 reasons:
     79				 * 1. driver flow control to protocol layer
     80				 * 2. limit the time used in ISR routine
     81				 */
     82
     83#define CB_EXTRA_RD_NUM     32
     84#define CB_RD_NUM           32
     85#define CB_TD_NUM           32
     86
     87/*
     88 * max number of physical segments in a single NDIS packet. Above this
     89 * threshold, the packet is copied into a single physically contiguous buffer
     90 */
     91#define CB_MAX_SEGMENT      4
     92
     93#define CB_MIN_MAP_REG_NUM  4
     94#define CB_MAX_MAP_REG_NUM  CB_MAX_TX_DESC
     95
     96#define CB_PROTOCOL_RESERVED_SECTION    16
     97
     98/*
     99 * if retrys excess 15 times , tx will abort, and if tx fifo underflow,
    100 * tx will fail, we should try to resend it
    101 */
    102#define CB_MAX_TX_ABORT_RETRY   3
    103
    104/* WMAC definition FIFO Control */
    105#define FIFOCTL_AUTO_FB_1   0x1000
    106#define FIFOCTL_AUTO_FB_0   0x0800
    107#define FIFOCTL_GRPACK      0x0400
    108#define FIFOCTL_11GA        0x0300
    109#define FIFOCTL_11GB        0x0200
    110#define FIFOCTL_11B         0x0100
    111#define FIFOCTL_11A         0x0000
    112#define FIFOCTL_RTS         0x0080
    113#define FIFOCTL_ISDMA0      0x0040
    114#define FIFOCTL_GENINT      0x0020
    115#define FIFOCTL_TMOEN       0x0010
    116#define FIFOCTL_LRETRY      0x0008
    117#define FIFOCTL_CRCDIS      0x0004
    118#define FIFOCTL_NEEDACK     0x0002
    119#define FIFOCTL_LHEAD       0x0001
    120
    121/* WMAC definition Frag Control */
    122#define FRAGCTL_AES         0x0300
    123#define FRAGCTL_TKIP        0x0200
    124#define FRAGCTL_LEGACY      0x0100
    125#define FRAGCTL_NONENCRYPT  0x0000
    126#define FRAGCTL_ENDFRAG     0x0003
    127#define FRAGCTL_MIDFRAG     0x0002
    128#define FRAGCTL_STAFRAG     0x0001
    129#define FRAGCTL_NONFRAG     0x0000
    130
    131#define TYPE_TXDMA0     0
    132#define TYPE_AC0DMA     1
    133#define TYPE_ATIMDMA    2
    134#define TYPE_SYNCDMA    3
    135#define TYPE_MAXTD      2
    136
    137#define TYPE_BEACONDMA  4
    138
    139#define TYPE_RXDMA0     0
    140#define TYPE_RXDMA1     1
    141#define TYPE_MAXRD      2
    142
    143/* TD_INFO flags control bit */
    144#define TD_FLAGS_NETIF_SKB      0x01    /* check if need release skb */
    145/* check if called from private skb (hostap) */
    146#define TD_FLAGS_PRIV_SKB       0x02
    147#define TD_FLAGS_PS_RETRY       0x04    /* check if PS STA frame re-transmit */
    148
    149/*
    150 * ref_sk_buff is used for mapping the skb structure between pre-built
    151 * driver-obj & running kernel. Since different kernel version (2.4x) may
    152 * change skb structure, i.e. pre-built driver-obj may link to older skb that
    153 * leads error.
    154 */
    155
    156struct vnt_rd_info {
    157	struct sk_buff *skb;
    158	dma_addr_t  skb_dma;
    159};
    160
    161struct vnt_rdes0 {
    162	volatile __le16 res_count;
    163#ifdef __BIG_ENDIAN
    164	union {
    165		volatile u16 f15_reserved;
    166		struct {
    167			volatile u8 f8_reserved1;
    168			volatile u8 owner:1;
    169			volatile u8 f7_reserved:7;
    170		} __packed;
    171	} __packed;
    172#else
    173	u16 f15_reserved:15;
    174	u16 owner:1;
    175#endif
    176} __packed;
    177
    178struct vnt_rdes1 {
    179	__le16 req_count;
    180	u16 reserved;
    181} __packed;
    182
    183/* Rx descriptor*/
    184struct vnt_rx_desc {
    185	volatile struct vnt_rdes0 rd0;
    186	volatile struct vnt_rdes1 rd1;
    187	volatile __le32 buff_addr;
    188	volatile __le32 next_desc;
    189	struct vnt_rx_desc *next __aligned(8);
    190	struct vnt_rd_info *rd_info __aligned(8);
    191} __packed;
    192
    193struct vnt_tdes0 {
    194	volatile u8 tsr0;
    195	volatile u8 tsr1;
    196#ifdef __BIG_ENDIAN
    197	union {
    198		volatile u16 f15_txtime;
    199		struct {
    200			volatile u8 f8_reserved;
    201			volatile u8 owner:1;
    202			volatile u8 f7_reserved:7;
    203		} __packed;
    204	} __packed;
    205#else
    206	volatile u16 f15_txtime:15;
    207	volatile u16 owner:1;
    208#endif
    209} __packed;
    210
    211struct vnt_tdes1 {
    212	volatile __le16 req_count;
    213	volatile u8 tcr;
    214	volatile u8 reserved;
    215} __packed;
    216
    217struct vnt_td_info {
    218	void *mic_hdr;
    219	struct sk_buff *skb;
    220	unsigned char *buf;
    221	dma_addr_t buf_dma;
    222	u16 req_count;
    223	u8 flags;
    224};
    225
    226/* transmit descriptor */
    227struct vnt_tx_desc {
    228	volatile struct vnt_tdes0 td0;
    229	volatile struct vnt_tdes1 td1;
    230	volatile __le32 buff_addr;
    231	volatile __le32 next_desc;
    232	struct vnt_tx_desc *next __aligned(8);
    233	struct vnt_td_info *td_info __aligned(8);
    234} __packed;
    235
    236/* Length, Service, and Signal fields of Phy for Tx */
    237struct vnt_phy_field {
    238	u8 signal;
    239	u8 service;
    240	__le16 len;
    241} __packed;
    242
    243union vnt_phy_field_swap {
    244	struct vnt_phy_field field_read;
    245	u16 swap[2];
    246	u32 field_write;
    247};
    248
    249#endif /* __DESC_H__ */