cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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desc.h (2523B)


      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
      4 * All rights reserved.
      5 *
      6 * Purpose:The header file of descriptor
      7 *
      8 * Revision History:
      9 *
     10 * Author: Tevin Chen
     11 *
     12 * Date: May 21, 1996
     13 *
     14 */
     15
     16#ifndef __DESC_H__
     17#define __DESC_H__
     18
     19#include <linux/bits.h>
     20#include <linux/types.h>
     21#include <linux/mm.h>
     22
     23/* max transmit or receive buffer size */
     24#define CB_MAX_BUF_SIZE     2900U       /* NOTE: must be multiple of 4 */
     25
     26#define MAX_TOTAL_SIZE_WITH_ALL_HEADERS CB_MAX_BUF_SIZE
     27
     28#define MAX_INTERRUPT_SIZE              32
     29
     30#define CB_MAX_RX_DESC      128         /* max # of descriptors */
     31#define CB_MIN_RX_DESC      16          /* min # of RX descriptors */
     32#define CB_MAX_TX_DESC      128         /* max # of descriptors */
     33#define CB_MIN_TX_DESC      16          /* min # of TX descriptors */
     34
     35/*
     36 * bits in the RSR register
     37 */
     38#define RSR_ADDRBROAD       BIT(7)
     39#define RSR_ADDRMULTI       BIT(6)
     40#define RSR_ADDRUNI         0x00
     41#define RSR_IVLDTYP         BIT(5)	/* invalid packet type */
     42#define RSR_IVLDLEN         BIT(4)	/* invalid len (> 2312 byte) */
     43#define RSR_BSSIDOK         BIT(3)
     44#define RSR_CRCOK           BIT(2)
     45#define RSR_BCNSSIDOK       BIT(1)
     46#define RSR_ADDROK          BIT(0)
     47
     48/*
     49 * bits in the new RSR register
     50 */
     51#define NEWRSR_DECRYPTOK    BIT(4)
     52#define NEWRSR_CFPIND       BIT(3)
     53#define NEWRSR_HWUTSF       BIT(2)
     54#define NEWRSR_BCNHITAID    BIT(1)
     55#define NEWRSR_BCNHITAID0   BIT(0)
     56
     57/*
     58 * bits in the TSR register
     59 */
     60#define TSR_RETRYTMO        BIT(3)
     61#define TSR_TMO             BIT(2)
     62#define TSR_ACKDATA         BIT(1)
     63#define TSR_VALID           BIT(0)
     64
     65#define FIFOCTL_AUTO_FB_1   0x1000
     66#define FIFOCTL_AUTO_FB_0   0x0800
     67#define FIFOCTL_GRPACK      0x0400
     68#define FIFOCTL_11GA        0x0300
     69#define FIFOCTL_11GB        0x0200
     70#define FIFOCTL_11B         0x0100
     71#define FIFOCTL_11A         0x0000
     72#define FIFOCTL_RTS         0x0080
     73#define FIFOCTL_ISDMA0      0x0040
     74#define FIFOCTL_GENINT      0x0020
     75#define FIFOCTL_TMOEN       0x0010
     76#define FIFOCTL_LRETRY      0x0008
     77#define FIFOCTL_CRCDIS      0x0004
     78#define FIFOCTL_NEEDACK     0x0002
     79#define FIFOCTL_LHEAD       0x0001
     80
     81/* WMAC definition Frag Control */
     82#define FRAGCTL_AES         0x0300
     83#define FRAGCTL_TKIP        0x0200
     84#define FRAGCTL_LEGACY      0x0100
     85#define FRAGCTL_NONENCRYPT  0x0000
     86#define FRAGCTL_ENDFRAG     0x0003
     87#define FRAGCTL_MIDFRAG     0x0002
     88#define FRAGCTL_STAFRAG     0x0001
     89#define FRAGCTL_NONFRAG     0x0000
     90
     91#endif /* __DESC_H__ */