cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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target_core_rd.h (1550B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef TARGET_CORE_RD_H
      3#define TARGET_CORE_RD_H
      4
      5#include <linux/module.h>
      6#include <linux/types.h>
      7#include <target/target_core_base.h>
      8
      9#define RD_HBA_VERSION		"v4.0"
     10#define RD_MCP_VERSION		"4.0"
     11
     12/* Largest piece of memory kmalloc can allocate */
     13#define RD_MAX_ALLOCATION_SIZE	65536
     14#define RD_DEVICE_QUEUE_DEPTH	32
     15#define RD_MAX_DEVICE_QUEUE_DEPTH 128
     16#define RD_BLOCKSIZE		512
     17
     18/* Used in target_core_init_configfs() for virtual LUN 0 access */
     19int __init rd_module_init(void);
     20void rd_module_exit(void);
     21
     22struct rd_dev_sg_table {
     23	u32		page_start_offset;
     24	u32		page_end_offset;
     25	u32		rd_sg_count;
     26	struct scatterlist *sg_table;
     27} ____cacheline_aligned;
     28
     29#define RDF_HAS_PAGE_COUNT	0x01
     30#define RDF_NULLIO		0x02
     31#define RDF_DUMMY		0x04
     32
     33struct rd_dev {
     34	struct se_device dev;
     35	u32		rd_flags;
     36	/* Unique Ramdisk Device ID in Ramdisk HBA */
     37	u32		rd_dev_id;
     38	/* Total page count for ramdisk device */
     39	u32		rd_page_count;
     40	/* Number of SG tables in sg_table_array */
     41	u32		sg_table_count;
     42	/* Number of SG tables in sg_prot_array */
     43	u32		sg_prot_count;
     44	/* Array of rd_dev_sg_table_t containing scatterlists */
     45	struct rd_dev_sg_table *sg_table_array;
     46	/* Array of rd_dev_sg_table containing protection scatterlists */
     47	struct rd_dev_sg_table *sg_prot_array;
     48	/* Ramdisk HBA device is connected to */
     49	struct rd_host *rd_host;
     50} ____cacheline_aligned;
     51
     52struct rd_host {
     53	u32		rd_host_dev_id_count;
     54	u32		rd_host_id;		/* Unique Ramdisk Host ID */
     55} ____cacheline_aligned;
     56
     57#endif /* TARGET_CORE_RD_H */