cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dz.h (5478B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * dz.h: Serial port driver for DECstations equipped
      4 *       with the DZ chipset.
      5 *
      6 * Copyright (C) 1998 Olivier A. D. Lebaillif 
      7 *             
      8 * Email: olivier.lebaillif@ifrsys.com
      9 *
     10 * Copyright (C) 2004, 2006  Maciej W. Rozycki
     11 */
     12#ifndef DZ_SERIAL_H
     13#define DZ_SERIAL_H
     14
     15/*
     16 * Definitions for the Control and Status Register.
     17 */
     18#define DZ_TRDY        0x8000                 /* Transmitter empty */
     19#define DZ_TIE         0x4000                 /* Transmitter Interrupt Enbl */
     20#define DZ_TLINE       0x0300                 /* Transmitter Line Number */
     21#define DZ_RDONE       0x0080                 /* Receiver data ready */
     22#define DZ_RIE         0x0040                 /* Receive Interrupt Enable */
     23#define DZ_MSE         0x0020                 /* Master Scan Enable */
     24#define DZ_CLR         0x0010                 /* Master reset */
     25#define DZ_MAINT       0x0008                 /* Loop Back Mode */
     26
     27/*
     28 * Definitions for the Receiver Buffer Register.
     29 */
     30#define DZ_RBUF_MASK   0x00FF                 /* Data Mask */
     31#define DZ_LINE_MASK   0x0300                 /* Line Mask */
     32#define DZ_DVAL        0x8000                 /* Valid Data indicator */
     33#define DZ_OERR        0x4000                 /* Overrun error indicator */
     34#define DZ_FERR        0x2000                 /* Frame error indicator */
     35#define DZ_PERR        0x1000                 /* Parity error indicator */
     36
     37#define DZ_BREAK       0x0800                 /* BREAK event software flag */
     38
     39#define LINE(x) ((x & DZ_LINE_MASK) >> 8)     /* Get the line number
     40                                                 from the input buffer */
     41#define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK))
     42
     43/*
     44 * Definitions for the Transmit Control Register.
     45 */
     46#define DZ_LINE_KEYBOARD 0x0001
     47#define DZ_LINE_MOUSE    0x0002
     48#define DZ_LINE_MODEM    0x0004
     49#define DZ_LINE_PRINTER  0x0008
     50
     51#define DZ_MODEM_RTS     0x0800               /* RTS for the modem line (2) */
     52#define DZ_MODEM_DTR     0x0400               /* DTR for the modem line (2) */
     53#define DZ_PRINT_RTS     0x0200               /* RTS for the prntr line (3) */
     54#define DZ_PRINT_DTR     0x0100               /* DTR for the prntr line (3) */
     55#define DZ_LNENB         0x000f               /* Transmitter Line Enable */
     56
     57/*
     58 * Definitions for the Modem Status Register.
     59 */
     60#define DZ_MODEM_RI      0x0800               /* RI for the modem line (2) */
     61#define DZ_MODEM_CD      0x0400               /* CD for the modem line (2) */
     62#define DZ_MODEM_DSR     0x0200               /* DSR for the modem line (2) */
     63#define DZ_MODEM_CTS     0x0100               /* CTS for the modem line (2) */
     64#define DZ_PRINT_RI      0x0008               /* RI for the printer line (3) */
     65#define DZ_PRINT_CD      0x0004               /* CD for the printer line (3) */
     66#define DZ_PRINT_DSR     0x0002               /* DSR for the prntr line (3) */
     67#define DZ_PRINT_CTS     0x0001               /* CTS for the prntr line (3) */
     68
     69/*
     70 * Definitions for the Transmit Data Register.
     71 */
     72#define DZ_BRK0          0x0100               /* Break assertion for line 0 */
     73#define DZ_BRK1          0x0200               /* Break assertion for line 1 */
     74#define DZ_BRK2          0x0400               /* Break assertion for line 2 */
     75#define DZ_BRK3          0x0800               /* Break assertion for line 3 */
     76
     77/*
     78 * Definitions for the Line Parameter Register.
     79 */
     80#define DZ_KEYBOARD      0x0000               /* line 0 = keyboard */
     81#define DZ_MOUSE         0x0001               /* line 1 = mouse */
     82#define DZ_MODEM         0x0002               /* line 2 = modem */
     83#define DZ_PRINTER       0x0003               /* line 3 = printer */
     84
     85#define DZ_CSIZE         0x0018               /* Number of bits per byte (mask) */
     86#define DZ_CS5           0x0000               /* 5 bits per byte */
     87#define DZ_CS6           0x0008               /* 6 bits per byte */
     88#define DZ_CS7           0x0010               /* 7 bits per byte */
     89#define DZ_CS8           0x0018               /* 8 bits per byte */
     90
     91#define DZ_CSTOPB        0x0020               /* 2 stop bits instead of one */ 
     92
     93#define DZ_PARENB        0x0040               /* Parity enable */
     94#define DZ_PARODD        0x0080               /* Odd parity instead of even */
     95
     96#define DZ_CBAUD         0x0E00               /* Baud Rate (mask) */
     97#define DZ_B50           0x0000
     98#define DZ_B75           0x0100
     99#define DZ_B110          0x0200
    100#define DZ_B134          0x0300
    101#define DZ_B150          0x0400
    102#define DZ_B300          0x0500
    103#define DZ_B600          0x0600
    104#define DZ_B1200         0x0700 
    105#define DZ_B1800         0x0800
    106#define DZ_B2000         0x0900
    107#define DZ_B2400         0x0A00
    108#define DZ_B3600         0x0B00
    109#define DZ_B4800         0x0C00
    110#define DZ_B7200         0x0D00
    111#define DZ_B9600         0x0E00
    112
    113#define DZ_RXENAB        0x1000               /* Receiver Enable */
    114
    115/*
    116 * Addresses for the DZ registers
    117 */
    118#define DZ_CSR       0x00            /* Control and Status Register */
    119#define DZ_RBUF      0x08            /* Receive Buffer */
    120#define DZ_LPR       0x08            /* Line Parameters Register */
    121#define DZ_TCR       0x10            /* Transmitter Control Register */
    122#define DZ_MSR       0x18            /* Modem Status Register */
    123#define DZ_TDR       0x18            /* Transmit Data Register */
    124
    125#define DZ_NB_PORT 4
    126
    127#define DZ_XMIT_SIZE   4096                 /* buffer size */
    128#define DZ_WAKEUP_CHARS   DZ_XMIT_SIZE/4
    129
    130#endif /* DZ_SERIAL_H */