cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap-serial.c (48339B)


      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Driver for OMAP-UART controller.
      4 * Based on drivers/serial/8250.c
      5 *
      6 * Copyright (C) 2010 Texas Instruments.
      7 *
      8 * Authors:
      9 *	Govindraj R	<govindraj.raja@ti.com>
     10 *	Thara Gopinath	<thara@ti.com>
     11 *
     12 * Note: This driver is made separate from 8250 driver as we cannot
     13 * over load 8250 driver with omap platform specific configuration for
     14 * features like DMA, it makes easier to implement features like DMA and
     15 * hardware flow control and software flow control configuration with
     16 * this driver as required for the omap-platform.
     17 */
     18
     19#include <linux/module.h>
     20#include <linux/init.h>
     21#include <linux/console.h>
     22#include <linux/serial_reg.h>
     23#include <linux/delay.h>
     24#include <linux/slab.h>
     25#include <linux/tty.h>
     26#include <linux/tty_flip.h>
     27#include <linux/platform_device.h>
     28#include <linux/io.h>
     29#include <linux/clk.h>
     30#include <linux/serial_core.h>
     31#include <linux/irq.h>
     32#include <linux/pm_runtime.h>
     33#include <linux/pm_wakeirq.h>
     34#include <linux/of.h>
     35#include <linux/of_irq.h>
     36#include <linux/gpio/consumer.h>
     37#include <linux/platform_data/serial-omap.h>
     38
     39#define OMAP_MAX_HSUART_PORTS	10
     40
     41#define UART_BUILD_REVISION(x, y)	(((x) << 8) | (y))
     42
     43#define OMAP_UART_REV_42 0x0402
     44#define OMAP_UART_REV_46 0x0406
     45#define OMAP_UART_REV_52 0x0502
     46#define OMAP_UART_REV_63 0x0603
     47
     48#define OMAP_UART_TX_WAKEUP_EN		BIT(7)
     49
     50/* Feature flags */
     51#define OMAP_UART_WER_HAS_TX_WAKEUP	BIT(0)
     52
     53#define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
     54#define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
     55
     56#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
     57
     58/* SCR register bitmasks */
     59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK		(1 << 7)
     60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK		(1 << 6)
     61#define OMAP_UART_SCR_TX_EMPTY			(1 << 3)
     62
     63/* FCR register bitmasks */
     64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK			(0x3 << 6)
     65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK			(0x3 << 4)
     66
     67/* MVR register bitmasks */
     68#define OMAP_UART_MVR_SCHEME_SHIFT	30
     69
     70#define OMAP_UART_LEGACY_MVR_MAJ_MASK	0xf0
     71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT	4
     72#define OMAP_UART_LEGACY_MVR_MIN_MASK	0x0f
     73
     74#define OMAP_UART_MVR_MAJ_MASK		0x700
     75#define OMAP_UART_MVR_MAJ_SHIFT		8
     76#define OMAP_UART_MVR_MIN_MASK		0x3f
     77
     78#define OMAP_UART_DMA_CH_FREE	-1
     79
     80#define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA
     81#define OMAP_MODE13X_SPEED	230400
     82
     83/* WER = 0x7F
     84 * Enable module level wakeup in WER reg
     85 */
     86#define OMAP_UART_WER_MOD_WKUP	0x7F
     87
     88/* Enable XON/XOFF flow control on output */
     89#define OMAP_UART_SW_TX		0x08
     90
     91/* Enable XON/XOFF flow control on input */
     92#define OMAP_UART_SW_RX		0x02
     93
     94#define OMAP_UART_SW_CLR	0xF0
     95
     96#define OMAP_UART_TCR_TRIG	0x0F
     97
     98struct uart_omap_dma {
     99	u8			uart_dma_tx;
    100	u8			uart_dma_rx;
    101	int			rx_dma_channel;
    102	int			tx_dma_channel;
    103	dma_addr_t		rx_buf_dma_phys;
    104	dma_addr_t		tx_buf_dma_phys;
    105	unsigned int		uart_base;
    106	/*
    107	 * Buffer for rx dma. It is not required for tx because the buffer
    108	 * comes from port structure.
    109	 */
    110	unsigned char		*rx_buf;
    111	unsigned int		prev_rx_dma_pos;
    112	int			tx_buf_size;
    113	int			tx_dma_used;
    114	int			rx_dma_used;
    115	spinlock_t		tx_lock;
    116	spinlock_t		rx_lock;
    117	/* timer to poll activity on rx dma */
    118	struct timer_list	rx_timer;
    119	unsigned int		rx_buf_size;
    120	unsigned int		rx_poll_rate;
    121	unsigned int		rx_timeout;
    122};
    123
    124struct uart_omap_port {
    125	struct uart_port	port;
    126	struct uart_omap_dma	uart_dma;
    127	struct device		*dev;
    128	int			wakeirq;
    129
    130	unsigned char		ier;
    131	unsigned char		lcr;
    132	unsigned char		mcr;
    133	unsigned char		fcr;
    134	unsigned char		efr;
    135	unsigned char		dll;
    136	unsigned char		dlh;
    137	unsigned char		mdr1;
    138	unsigned char		scr;
    139	unsigned char		wer;
    140
    141	int			use_dma;
    142	/*
    143	 * Some bits in registers are cleared on a read, so they must
    144	 * be saved whenever the register is read, but the bits will not
    145	 * be immediately processed.
    146	 */
    147	unsigned int		lsr_break_flag;
    148	unsigned char		msr_saved_flags;
    149	char			name[20];
    150	unsigned long		port_activity;
    151	int			context_loss_cnt;
    152	u32			errata;
    153	u32			features;
    154
    155	struct gpio_desc	*rts_gpiod;
    156
    157	struct pm_qos_request	pm_qos_request;
    158	u32			latency;
    159	u32			calc_latency;
    160	struct work_struct	qos_work;
    161	bool			is_suspending;
    162
    163	unsigned int		rs485_tx_filter_count;
    164};
    165
    166#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
    167
    168static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
    169
    170/* Forward declaration of functions */
    171static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
    172
    173static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
    174{
    175	offset <<= up->port.regshift;
    176	return readw(up->port.membase + offset);
    177}
    178
    179static inline void serial_out(struct uart_omap_port *up, int offset, int value)
    180{
    181	offset <<= up->port.regshift;
    182	writew(value, up->port.membase + offset);
    183}
    184
    185static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
    186{
    187	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
    188	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
    189		       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
    190	serial_out(up, UART_FCR, 0);
    191}
    192
    193#ifdef CONFIG_PM
    194static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
    195{
    196	struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
    197
    198	if (!pdata || !pdata->get_context_loss_count)
    199		return -EINVAL;
    200
    201	return pdata->get_context_loss_count(up->dev);
    202}
    203
    204/* REVISIT: Remove this when omap3 boots in device tree only mode */
    205static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
    206{
    207	struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
    208
    209	if (!pdata || !pdata->enable_wakeup)
    210		return;
    211
    212	pdata->enable_wakeup(up->dev, enable);
    213}
    214#endif /* CONFIG_PM */
    215
    216/*
    217 * Calculate the absolute difference between the desired and actual baud
    218 * rate for the given mode.
    219 */
    220static inline int calculate_baud_abs_diff(struct uart_port *port,
    221				unsigned int baud, unsigned int mode)
    222{
    223	unsigned int n = port->uartclk / (mode * baud);
    224	int abs_diff;
    225
    226	if (n == 0)
    227		n = 1;
    228
    229	abs_diff = baud - (port->uartclk / (mode * n));
    230	if (abs_diff < 0)
    231		abs_diff = -abs_diff;
    232
    233	return abs_diff;
    234}
    235
    236/*
    237 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
    238 * @port: uart port info
    239 * @baud: baudrate for which mode needs to be determined
    240 *
    241 * Returns true if baud rate is MODE16X and false if MODE13X
    242 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
    243 * and Error Rates" determines modes not for all common baud rates.
    244 * E.g. for 1000000 baud rate mode must be 16x, but according to that
    245 * table it's determined as 13x.
    246 */
    247static bool
    248serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
    249{
    250	int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
    251	int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
    252
    253	return (abs_diff_13 >= abs_diff_16);
    254}
    255
    256/*
    257 * serial_omap_get_divisor - calculate divisor value
    258 * @port: uart port info
    259 * @baud: baudrate for which divisor needs to be calculated.
    260 */
    261static unsigned int
    262serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
    263{
    264	unsigned int mode;
    265
    266	if (!serial_omap_baud_is_mode16(port, baud))
    267		mode = 13;
    268	else
    269		mode = 16;
    270	return port->uartclk/(mode * baud);
    271}
    272
    273static void serial_omap_enable_ms(struct uart_port *port)
    274{
    275	struct uart_omap_port *up = to_uart_omap_port(port);
    276
    277	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
    278
    279	up->ier |= UART_IER_MSI;
    280	serial_out(up, UART_IER, up->ier);
    281}
    282
    283static void serial_omap_stop_tx(struct uart_port *port)
    284{
    285	struct uart_omap_port *up = to_uart_omap_port(port);
    286	int res;
    287
    288	/* Handle RS-485 */
    289	if (port->rs485.flags & SER_RS485_ENABLED) {
    290		if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
    291			/* THR interrupt is fired when both TX FIFO and TX
    292			 * shift register are empty. This means there's nothing
    293			 * left to transmit now, so make sure the THR interrupt
    294			 * is fired when TX FIFO is below the trigger level,
    295			 * disable THR interrupts and toggle the RS-485 GPIO
    296			 * data direction pin if needed.
    297			 */
    298			up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
    299			serial_out(up, UART_OMAP_SCR, up->scr);
    300			res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
    301				1 : 0;
    302			if (up->rts_gpiod &&
    303			    gpiod_get_value(up->rts_gpiod) != res) {
    304				if (port->rs485.delay_rts_after_send > 0)
    305					mdelay(
    306					port->rs485.delay_rts_after_send);
    307				gpiod_set_value(up->rts_gpiod, res);
    308			}
    309		} else {
    310			/* We're asked to stop, but there's still stuff in the
    311			 * UART FIFO, so make sure the THR interrupt is fired
    312			 * when both TX FIFO and TX shift register are empty.
    313			 * The next THR interrupt (if no transmission is started
    314			 * in the meantime) will indicate the end of a
    315			 * transmission. Therefore we _don't_ disable THR
    316			 * interrupts in this situation.
    317			 */
    318			up->scr |= OMAP_UART_SCR_TX_EMPTY;
    319			serial_out(up, UART_OMAP_SCR, up->scr);
    320			return;
    321		}
    322	}
    323
    324	if (up->ier & UART_IER_THRI) {
    325		up->ier &= ~UART_IER_THRI;
    326		serial_out(up, UART_IER, up->ier);
    327	}
    328}
    329
    330static void serial_omap_stop_rx(struct uart_port *port)
    331{
    332	struct uart_omap_port *up = to_uart_omap_port(port);
    333
    334	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
    335	up->port.read_status_mask &= ~UART_LSR_DR;
    336	serial_out(up, UART_IER, up->ier);
    337}
    338
    339static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
    340{
    341	struct circ_buf *xmit = &up->port.state->xmit;
    342	int count;
    343
    344	if (up->port.x_char) {
    345		serial_out(up, UART_TX, up->port.x_char);
    346		up->port.icount.tx++;
    347		up->port.x_char = 0;
    348		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
    349		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
    350			up->rs485_tx_filter_count++;
    351
    352		return;
    353	}
    354	if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
    355		serial_omap_stop_tx(&up->port);
    356		return;
    357	}
    358	count = up->port.fifosize / 4;
    359	do {
    360		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
    361		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
    362		up->port.icount.tx++;
    363		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
    364		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
    365			up->rs485_tx_filter_count++;
    366
    367		if (uart_circ_empty(xmit))
    368			break;
    369	} while (--count > 0);
    370
    371	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
    372		uart_write_wakeup(&up->port);
    373
    374	if (uart_circ_empty(xmit))
    375		serial_omap_stop_tx(&up->port);
    376}
    377
    378static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
    379{
    380	if (!(up->ier & UART_IER_THRI)) {
    381		up->ier |= UART_IER_THRI;
    382		serial_out(up, UART_IER, up->ier);
    383	}
    384}
    385
    386static void serial_omap_start_tx(struct uart_port *port)
    387{
    388	struct uart_omap_port *up = to_uart_omap_port(port);
    389	int res;
    390
    391	/* Handle RS-485 */
    392	if (port->rs485.flags & SER_RS485_ENABLED) {
    393		/* Fire THR interrupts when FIFO is below trigger level */
    394		up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
    395		serial_out(up, UART_OMAP_SCR, up->scr);
    396
    397		/* if rts not already enabled */
    398		res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
    399		if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
    400			gpiod_set_value(up->rts_gpiod, res);
    401			if (port->rs485.delay_rts_before_send > 0)
    402				mdelay(port->rs485.delay_rts_before_send);
    403		}
    404	}
    405
    406	if ((port->rs485.flags & SER_RS485_ENABLED) &&
    407	    !(port->rs485.flags & SER_RS485_RX_DURING_TX))
    408		up->rs485_tx_filter_count = 0;
    409
    410	serial_omap_enable_ier_thri(up);
    411}
    412
    413static void serial_omap_throttle(struct uart_port *port)
    414{
    415	struct uart_omap_port *up = to_uart_omap_port(port);
    416	unsigned long flags;
    417
    418	spin_lock_irqsave(&up->port.lock, flags);
    419	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
    420	serial_out(up, UART_IER, up->ier);
    421	spin_unlock_irqrestore(&up->port.lock, flags);
    422}
    423
    424static void serial_omap_unthrottle(struct uart_port *port)
    425{
    426	struct uart_omap_port *up = to_uart_omap_port(port);
    427	unsigned long flags;
    428
    429	spin_lock_irqsave(&up->port.lock, flags);
    430	up->ier |= UART_IER_RLSI | UART_IER_RDI;
    431	serial_out(up, UART_IER, up->ier);
    432	spin_unlock_irqrestore(&up->port.lock, flags);
    433}
    434
    435static unsigned int check_modem_status(struct uart_omap_port *up)
    436{
    437	unsigned int status;
    438
    439	status = serial_in(up, UART_MSR);
    440	status |= up->msr_saved_flags;
    441	up->msr_saved_flags = 0;
    442	if ((status & UART_MSR_ANY_DELTA) == 0)
    443		return status;
    444
    445	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
    446	    up->port.state != NULL) {
    447		if (status & UART_MSR_TERI)
    448			up->port.icount.rng++;
    449		if (status & UART_MSR_DDSR)
    450			up->port.icount.dsr++;
    451		if (status & UART_MSR_DDCD)
    452			uart_handle_dcd_change
    453				(&up->port, status & UART_MSR_DCD);
    454		if (status & UART_MSR_DCTS)
    455			uart_handle_cts_change
    456				(&up->port, status & UART_MSR_CTS);
    457		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
    458	}
    459
    460	return status;
    461}
    462
    463static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
    464{
    465	unsigned int flag;
    466
    467	/*
    468	 * Read one data character out to avoid stalling the receiver according
    469	 * to the table 23-246 of the omap4 TRM.
    470	 */
    471	if (likely(lsr & UART_LSR_DR)) {
    472		serial_in(up, UART_RX);
    473		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
    474		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
    475		    up->rs485_tx_filter_count)
    476			up->rs485_tx_filter_count--;
    477	}
    478
    479	up->port.icount.rx++;
    480	flag = TTY_NORMAL;
    481
    482	if (lsr & UART_LSR_BI) {
    483		flag = TTY_BREAK;
    484		lsr &= ~(UART_LSR_FE | UART_LSR_PE);
    485		up->port.icount.brk++;
    486		/*
    487		 * We do the SysRQ and SAK checking
    488		 * here because otherwise the break
    489		 * may get masked by ignore_status_mask
    490		 * or read_status_mask.
    491		 */
    492		if (uart_handle_break(&up->port))
    493			return;
    494
    495	}
    496
    497	if (lsr & UART_LSR_PE) {
    498		flag = TTY_PARITY;
    499		up->port.icount.parity++;
    500	}
    501
    502	if (lsr & UART_LSR_FE) {
    503		flag = TTY_FRAME;
    504		up->port.icount.frame++;
    505	}
    506
    507	if (lsr & UART_LSR_OE)
    508		up->port.icount.overrun++;
    509
    510#ifdef CONFIG_SERIAL_OMAP_CONSOLE
    511	if (up->port.line == up->port.cons->index) {
    512		/* Recover the break flag from console xmit */
    513		lsr |= up->lsr_break_flag;
    514	}
    515#endif
    516	uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
    517}
    518
    519static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
    520{
    521	unsigned char ch = 0;
    522	unsigned int flag;
    523
    524	if (!(lsr & UART_LSR_DR))
    525		return;
    526
    527	ch = serial_in(up, UART_RX);
    528	if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
    529	    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
    530	    up->rs485_tx_filter_count) {
    531		up->rs485_tx_filter_count--;
    532		return;
    533	}
    534
    535	flag = TTY_NORMAL;
    536	up->port.icount.rx++;
    537
    538	if (uart_handle_sysrq_char(&up->port, ch))
    539		return;
    540
    541	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
    542}
    543
    544/**
    545 * serial_omap_irq() - This handles the interrupt from one port
    546 * @irq: uart port irq number
    547 * @dev_id: uart port info
    548 */
    549static irqreturn_t serial_omap_irq(int irq, void *dev_id)
    550{
    551	struct uart_omap_port *up = dev_id;
    552	unsigned int iir, lsr;
    553	unsigned int type;
    554	irqreturn_t ret = IRQ_NONE;
    555	int max_count = 256;
    556
    557	spin_lock(&up->port.lock);
    558
    559	do {
    560		iir = serial_in(up, UART_IIR);
    561		if (iir & UART_IIR_NO_INT)
    562			break;
    563
    564		ret = IRQ_HANDLED;
    565		lsr = serial_in(up, UART_LSR);
    566
    567		/* extract IRQ type from IIR register */
    568		type = iir & 0x3e;
    569
    570		switch (type) {
    571		case UART_IIR_MSI:
    572			check_modem_status(up);
    573			break;
    574		case UART_IIR_THRI:
    575			transmit_chars(up, lsr);
    576			break;
    577		case UART_IIR_RX_TIMEOUT:
    578		case UART_IIR_RDI:
    579			serial_omap_rdi(up, lsr);
    580			break;
    581		case UART_IIR_RLSI:
    582			serial_omap_rlsi(up, lsr);
    583			break;
    584		case UART_IIR_CTS_RTS_DSR:
    585			/* simply try again */
    586			break;
    587		case UART_IIR_XOFF:
    588		default:
    589			break;
    590		}
    591	} while (max_count--);
    592
    593	spin_unlock(&up->port.lock);
    594
    595	tty_flip_buffer_push(&up->port.state->port);
    596
    597	up->port_activity = jiffies;
    598
    599	return ret;
    600}
    601
    602static unsigned int serial_omap_tx_empty(struct uart_port *port)
    603{
    604	struct uart_omap_port *up = to_uart_omap_port(port);
    605	unsigned long flags;
    606	unsigned int ret = 0;
    607
    608	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
    609	spin_lock_irqsave(&up->port.lock, flags);
    610	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
    611	spin_unlock_irqrestore(&up->port.lock, flags);
    612
    613	return ret;
    614}
    615
    616static unsigned int serial_omap_get_mctrl(struct uart_port *port)
    617{
    618	struct uart_omap_port *up = to_uart_omap_port(port);
    619	unsigned int status;
    620	unsigned int ret = 0;
    621
    622	status = check_modem_status(up);
    623
    624	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
    625
    626	if (status & UART_MSR_DCD)
    627		ret |= TIOCM_CAR;
    628	if (status & UART_MSR_RI)
    629		ret |= TIOCM_RNG;
    630	if (status & UART_MSR_DSR)
    631		ret |= TIOCM_DSR;
    632	if (status & UART_MSR_CTS)
    633		ret |= TIOCM_CTS;
    634	return ret;
    635}
    636
    637static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
    638{
    639	struct uart_omap_port *up = to_uart_omap_port(port);
    640	unsigned char mcr = 0, old_mcr, lcr;
    641
    642	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
    643	if (mctrl & TIOCM_RTS)
    644		mcr |= UART_MCR_RTS;
    645	if (mctrl & TIOCM_DTR)
    646		mcr |= UART_MCR_DTR;
    647	if (mctrl & TIOCM_OUT1)
    648		mcr |= UART_MCR_OUT1;
    649	if (mctrl & TIOCM_OUT2)
    650		mcr |= UART_MCR_OUT2;
    651	if (mctrl & TIOCM_LOOP)
    652		mcr |= UART_MCR_LOOP;
    653
    654	old_mcr = serial_in(up, UART_MCR);
    655	old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
    656		     UART_MCR_DTR | UART_MCR_RTS);
    657	up->mcr = old_mcr | mcr;
    658	serial_out(up, UART_MCR, up->mcr);
    659
    660	/* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
    661	lcr = serial_in(up, UART_LCR);
    662	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    663	if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
    664		up->efr |= UART_EFR_RTS;
    665	else
    666		up->efr &= ~UART_EFR_RTS;
    667	serial_out(up, UART_EFR, up->efr);
    668	serial_out(up, UART_LCR, lcr);
    669}
    670
    671static void serial_omap_break_ctl(struct uart_port *port, int break_state)
    672{
    673	struct uart_omap_port *up = to_uart_omap_port(port);
    674	unsigned long flags;
    675
    676	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
    677	spin_lock_irqsave(&up->port.lock, flags);
    678	if (break_state == -1)
    679		up->lcr |= UART_LCR_SBC;
    680	else
    681		up->lcr &= ~UART_LCR_SBC;
    682	serial_out(up, UART_LCR, up->lcr);
    683	spin_unlock_irqrestore(&up->port.lock, flags);
    684}
    685
    686static int serial_omap_startup(struct uart_port *port)
    687{
    688	struct uart_omap_port *up = to_uart_omap_port(port);
    689	unsigned long flags;
    690	int retval;
    691
    692	/*
    693	 * Allocate the IRQ
    694	 */
    695	retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
    696				up->name, up);
    697	if (retval)
    698		return retval;
    699
    700	/* Optional wake-up IRQ */
    701	if (up->wakeirq) {
    702		retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
    703		if (retval) {
    704			free_irq(up->port.irq, up);
    705			return retval;
    706		}
    707	}
    708
    709	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
    710
    711	pm_runtime_get_sync(up->dev);
    712	/*
    713	 * Clear the FIFO buffers and disable them.
    714	 * (they will be reenabled in set_termios())
    715	 */
    716	serial_omap_clear_fifos(up);
    717
    718	/*
    719	 * Clear the interrupt registers.
    720	 */
    721	(void) serial_in(up, UART_LSR);
    722	if (serial_in(up, UART_LSR) & UART_LSR_DR)
    723		(void) serial_in(up, UART_RX);
    724	(void) serial_in(up, UART_IIR);
    725	(void) serial_in(up, UART_MSR);
    726
    727	/*
    728	 * Now, initialize the UART
    729	 */
    730	serial_out(up, UART_LCR, UART_LCR_WLEN8);
    731	spin_lock_irqsave(&up->port.lock, flags);
    732	/*
    733	 * Most PC uarts need OUT2 raised to enable interrupts.
    734	 */
    735	up->port.mctrl |= TIOCM_OUT2;
    736	serial_omap_set_mctrl(&up->port, up->port.mctrl);
    737	spin_unlock_irqrestore(&up->port.lock, flags);
    738
    739	up->msr_saved_flags = 0;
    740	/*
    741	 * Finally, enable interrupts. Note: Modem status interrupts
    742	 * are set via set_termios(), which will be occurring imminently
    743	 * anyway, so we don't enable them here.
    744	 */
    745	up->ier = UART_IER_RLSI | UART_IER_RDI;
    746	serial_out(up, UART_IER, up->ier);
    747
    748	/* Enable module level wake up */
    749	up->wer = OMAP_UART_WER_MOD_WKUP;
    750	if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
    751		up->wer |= OMAP_UART_TX_WAKEUP_EN;
    752
    753	serial_out(up, UART_OMAP_WER, up->wer);
    754
    755	up->port_activity = jiffies;
    756	return 0;
    757}
    758
    759static void serial_omap_shutdown(struct uart_port *port)
    760{
    761	struct uart_omap_port *up = to_uart_omap_port(port);
    762	unsigned long flags;
    763
    764	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
    765
    766	/*
    767	 * Disable interrupts from this port
    768	 */
    769	up->ier = 0;
    770	serial_out(up, UART_IER, 0);
    771
    772	spin_lock_irqsave(&up->port.lock, flags);
    773	up->port.mctrl &= ~TIOCM_OUT2;
    774	serial_omap_set_mctrl(&up->port, up->port.mctrl);
    775	spin_unlock_irqrestore(&up->port.lock, flags);
    776
    777	/*
    778	 * Disable break condition and FIFOs
    779	 */
    780	serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
    781	serial_omap_clear_fifos(up);
    782
    783	/*
    784	 * Read data port to reset things, and then free the irq
    785	 */
    786	if (serial_in(up, UART_LSR) & UART_LSR_DR)
    787		(void) serial_in(up, UART_RX);
    788
    789	pm_runtime_put_sync(up->dev);
    790	free_irq(up->port.irq, up);
    791	dev_pm_clear_wake_irq(up->dev);
    792}
    793
    794static void serial_omap_uart_qos_work(struct work_struct *work)
    795{
    796	struct uart_omap_port *up = container_of(work, struct uart_omap_port,
    797						qos_work);
    798
    799	cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
    800}
    801
    802static void
    803serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
    804			struct ktermios *old)
    805{
    806	struct uart_omap_port *up = to_uart_omap_port(port);
    807	unsigned char cval = 0;
    808	unsigned long flags;
    809	unsigned int baud, quot;
    810
    811	cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
    812
    813	if (termios->c_cflag & CSTOPB)
    814		cval |= UART_LCR_STOP;
    815	if (termios->c_cflag & PARENB)
    816		cval |= UART_LCR_PARITY;
    817	if (!(termios->c_cflag & PARODD))
    818		cval |= UART_LCR_EPAR;
    819	if (termios->c_cflag & CMSPAR)
    820		cval |= UART_LCR_SPAR;
    821
    822	/*
    823	 * Ask the core to calculate the divisor for us.
    824	 */
    825
    826	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
    827	quot = serial_omap_get_divisor(port, baud);
    828
    829	/* calculate wakeup latency constraint */
    830	up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
    831	up->latency = up->calc_latency;
    832	schedule_work(&up->qos_work);
    833
    834	up->dll = quot & 0xff;
    835	up->dlh = quot >> 8;
    836	up->mdr1 = UART_OMAP_MDR1_DISABLE;
    837
    838	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
    839			UART_FCR_ENABLE_FIFO;
    840
    841	/*
    842	 * Ok, we're now changing the port state. Do it with
    843	 * interrupts disabled.
    844	 */
    845	spin_lock_irqsave(&up->port.lock, flags);
    846
    847	/*
    848	 * Update the per-port timeout.
    849	 */
    850	uart_update_timeout(port, termios->c_cflag, baud);
    851
    852	up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
    853	if (termios->c_iflag & INPCK)
    854		up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
    855	if (termios->c_iflag & (BRKINT | PARMRK))
    856		up->port.read_status_mask |= UART_LSR_BI;
    857
    858	/*
    859	 * Characters to ignore
    860	 */
    861	up->port.ignore_status_mask = 0;
    862	if (termios->c_iflag & IGNPAR)
    863		up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
    864	if (termios->c_iflag & IGNBRK) {
    865		up->port.ignore_status_mask |= UART_LSR_BI;
    866		/*
    867		 * If we're ignoring parity and break indicators,
    868		 * ignore overruns too (for real raw support).
    869		 */
    870		if (termios->c_iflag & IGNPAR)
    871			up->port.ignore_status_mask |= UART_LSR_OE;
    872	}
    873
    874	/*
    875	 * ignore all characters if CREAD is not set
    876	 */
    877	if ((termios->c_cflag & CREAD) == 0)
    878		up->port.ignore_status_mask |= UART_LSR_DR;
    879
    880	/*
    881	 * Modem status interrupts
    882	 */
    883	up->ier &= ~UART_IER_MSI;
    884	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
    885		up->ier |= UART_IER_MSI;
    886	serial_out(up, UART_IER, up->ier);
    887	serial_out(up, UART_LCR, cval);		/* reset DLAB */
    888	up->lcr = cval;
    889	up->scr = 0;
    890
    891	/* FIFOs and DMA Settings */
    892
    893	/* FCR can be changed only when the
    894	 * baud clock is not running
    895	 * DLL_REG and DLH_REG set to 0.
    896	 */
    897	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
    898	serial_out(up, UART_DLL, 0);
    899	serial_out(up, UART_DLM, 0);
    900	serial_out(up, UART_LCR, 0);
    901
    902	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    903
    904	up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
    905	up->efr &= ~UART_EFR_SCD;
    906	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
    907
    908	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
    909	up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
    910	serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
    911	/* FIFO ENABLE, DMA MODE */
    912
    913	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
    914	/*
    915	 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
    916	 * sets Enables the granularity of 1 for TRIGGER RX
    917	 * level. Along with setting RX FIFO trigger level
    918	 * to 1 (as noted below, 16 characters) and TLR[3:0]
    919	 * to zero this will result RX FIFO threshold level
    920	 * to 1 character, instead of 16 as noted in comment
    921	 * below.
    922	 */
    923
    924	/* Set receive FIFO threshold to 16 characters and
    925	 * transmit FIFO threshold to 32 spaces
    926	 */
    927	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
    928	up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
    929	up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
    930		UART_FCR_ENABLE_FIFO;
    931
    932	serial_out(up, UART_FCR, up->fcr);
    933	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    934
    935	serial_out(up, UART_OMAP_SCR, up->scr);
    936
    937	/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
    938	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
    939	serial_out(up, UART_MCR, up->mcr);
    940	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    941	serial_out(up, UART_EFR, up->efr);
    942	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
    943
    944	/* Protocol, Baud Rate, and Interrupt Settings */
    945
    946	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
    947		serial_omap_mdr1_errataset(up, up->mdr1);
    948	else
    949		serial_out(up, UART_OMAP_MDR1, up->mdr1);
    950
    951	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    952	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
    953
    954	serial_out(up, UART_LCR, 0);
    955	serial_out(up, UART_IER, 0);
    956	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    957
    958	serial_out(up, UART_DLL, up->dll);	/* LS of divisor */
    959	serial_out(up, UART_DLM, up->dlh);	/* MS of divisor */
    960
    961	serial_out(up, UART_LCR, 0);
    962	serial_out(up, UART_IER, up->ier);
    963	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    964
    965	serial_out(up, UART_EFR, up->efr);
    966	serial_out(up, UART_LCR, cval);
    967
    968	if (!serial_omap_baud_is_mode16(port, baud))
    969		up->mdr1 = UART_OMAP_MDR1_13X_MODE;
    970	else
    971		up->mdr1 = UART_OMAP_MDR1_16X_MODE;
    972
    973	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
    974		serial_omap_mdr1_errataset(up, up->mdr1);
    975	else
    976		serial_out(up, UART_OMAP_MDR1, up->mdr1);
    977
    978	/* Configure flow control */
    979	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
    980
    981	/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
    982	serial_out(up, UART_XON1, termios->c_cc[VSTART]);
    983	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
    984
    985	/* Enable access to TCR/TLR */
    986	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
    987	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
    988	serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
    989
    990	serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
    991
    992	up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
    993
    994	if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
    995		/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
    996		up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
    997		up->efr |= UART_EFR_CTS;
    998	} else {
    999		/* Disable AUTORTS and AUTOCTS */
   1000		up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
   1001	}
   1002
   1003	if (up->port.flags & UPF_SOFT_FLOW) {
   1004		/* clear SW control mode bits */
   1005		up->efr &= OMAP_UART_SW_CLR;
   1006
   1007		/*
   1008		 * IXON Flag:
   1009		 * Enable XON/XOFF flow control on input.
   1010		 * Receiver compares XON1, XOFF1.
   1011		 */
   1012		if (termios->c_iflag & IXON)
   1013			up->efr |= OMAP_UART_SW_RX;
   1014
   1015		/*
   1016		 * IXOFF Flag:
   1017		 * Enable XON/XOFF flow control on output.
   1018		 * Transmit XON1, XOFF1
   1019		 */
   1020		if (termios->c_iflag & IXOFF) {
   1021			up->port.status |= UPSTAT_AUTOXOFF;
   1022			up->efr |= OMAP_UART_SW_TX;
   1023		}
   1024
   1025		/*
   1026		 * IXANY Flag:
   1027		 * Enable any character to restart output.
   1028		 * Operation resumes after receiving any
   1029		 * character after recognition of the XOFF character
   1030		 */
   1031		if (termios->c_iflag & IXANY)
   1032			up->mcr |= UART_MCR_XONANY;
   1033		else
   1034			up->mcr &= ~UART_MCR_XONANY;
   1035	}
   1036	serial_out(up, UART_MCR, up->mcr);
   1037	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
   1038	serial_out(up, UART_EFR, up->efr);
   1039	serial_out(up, UART_LCR, up->lcr);
   1040
   1041	serial_omap_set_mctrl(&up->port, up->port.mctrl);
   1042
   1043	spin_unlock_irqrestore(&up->port.lock, flags);
   1044	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
   1045}
   1046
   1047static void
   1048serial_omap_pm(struct uart_port *port, unsigned int state,
   1049	       unsigned int oldstate)
   1050{
   1051	struct uart_omap_port *up = to_uart_omap_port(port);
   1052	unsigned char efr;
   1053
   1054	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
   1055
   1056	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
   1057	efr = serial_in(up, UART_EFR);
   1058	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
   1059	serial_out(up, UART_LCR, 0);
   1060
   1061	serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
   1062	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
   1063	serial_out(up, UART_EFR, efr);
   1064	serial_out(up, UART_LCR, 0);
   1065}
   1066
   1067static void serial_omap_release_port(struct uart_port *port)
   1068{
   1069	dev_dbg(port->dev, "serial_omap_release_port+\n");
   1070}
   1071
   1072static int serial_omap_request_port(struct uart_port *port)
   1073{
   1074	dev_dbg(port->dev, "serial_omap_request_port+\n");
   1075	return 0;
   1076}
   1077
   1078static void serial_omap_config_port(struct uart_port *port, int flags)
   1079{
   1080	struct uart_omap_port *up = to_uart_omap_port(port);
   1081
   1082	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
   1083							up->port.line);
   1084	up->port.type = PORT_OMAP;
   1085	up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
   1086}
   1087
   1088static int
   1089serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
   1090{
   1091	/* we don't want the core code to modify any port params */
   1092	dev_dbg(port->dev, "serial_omap_verify_port+\n");
   1093	return -EINVAL;
   1094}
   1095
   1096static const char *
   1097serial_omap_type(struct uart_port *port)
   1098{
   1099	struct uart_omap_port *up = to_uart_omap_port(port);
   1100
   1101	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
   1102	return up->name;
   1103}
   1104
   1105#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
   1106
   1107static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
   1108{
   1109	unsigned int status, tmout = 10000;
   1110
   1111	/* Wait up to 10ms for the character(s) to be sent. */
   1112	do {
   1113		status = serial_in(up, UART_LSR);
   1114
   1115		if (status & UART_LSR_BI)
   1116			up->lsr_break_flag = UART_LSR_BI;
   1117
   1118		if (--tmout == 0)
   1119			break;
   1120		udelay(1);
   1121	} while ((status & BOTH_EMPTY) != BOTH_EMPTY);
   1122
   1123	/* Wait up to 1s for flow control if necessary */
   1124	if (up->port.flags & UPF_CONS_FLOW) {
   1125		tmout = 1000000;
   1126		for (tmout = 1000000; tmout; tmout--) {
   1127			unsigned int msr = serial_in(up, UART_MSR);
   1128
   1129			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
   1130			if (msr & UART_MSR_CTS)
   1131				break;
   1132
   1133			udelay(1);
   1134		}
   1135	}
   1136}
   1137
   1138#ifdef CONFIG_CONSOLE_POLL
   1139
   1140static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
   1141{
   1142	struct uart_omap_port *up = to_uart_omap_port(port);
   1143
   1144	wait_for_xmitr(up);
   1145	serial_out(up, UART_TX, ch);
   1146}
   1147
   1148static int serial_omap_poll_get_char(struct uart_port *port)
   1149{
   1150	struct uart_omap_port *up = to_uart_omap_port(port);
   1151	unsigned int status;
   1152
   1153	status = serial_in(up, UART_LSR);
   1154	if (!(status & UART_LSR_DR)) {
   1155		status = NO_POLL_CHAR;
   1156		goto out;
   1157	}
   1158
   1159	status = serial_in(up, UART_RX);
   1160
   1161out:
   1162	return status;
   1163}
   1164
   1165#endif /* CONFIG_CONSOLE_POLL */
   1166
   1167#ifdef CONFIG_SERIAL_OMAP_CONSOLE
   1168
   1169#ifdef CONFIG_SERIAL_EARLYCON
   1170static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
   1171{
   1172	offset <<= port->regshift;
   1173	return readw(port->membase + offset);
   1174}
   1175
   1176static void omap_serial_early_out(struct uart_port *port, int offset,
   1177				  int value)
   1178{
   1179	offset <<= port->regshift;
   1180	writew(value, port->membase + offset);
   1181}
   1182
   1183static void omap_serial_early_putc(struct uart_port *port, unsigned char c)
   1184{
   1185	unsigned int status;
   1186
   1187	for (;;) {
   1188		status = omap_serial_early_in(port, UART_LSR);
   1189		if ((status & BOTH_EMPTY) == BOTH_EMPTY)
   1190			break;
   1191		cpu_relax();
   1192	}
   1193	omap_serial_early_out(port, UART_TX, c);
   1194}
   1195
   1196static void early_omap_serial_write(struct console *console, const char *s,
   1197				    unsigned int count)
   1198{
   1199	struct earlycon_device *device = console->data;
   1200	struct uart_port *port = &device->port;
   1201
   1202	uart_console_write(port, s, count, omap_serial_early_putc);
   1203}
   1204
   1205static int __init early_omap_serial_setup(struct earlycon_device *device,
   1206					  const char *options)
   1207{
   1208	struct uart_port *port = &device->port;
   1209
   1210	if (!(device->port.membase || device->port.iobase))
   1211		return -ENODEV;
   1212
   1213	port->regshift = 2;
   1214	device->con->write = early_omap_serial_write;
   1215	return 0;
   1216}
   1217
   1218OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
   1219OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
   1220OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
   1221#endif /* CONFIG_SERIAL_EARLYCON */
   1222
   1223static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
   1224
   1225static struct uart_driver serial_omap_reg;
   1226
   1227static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch)
   1228{
   1229	struct uart_omap_port *up = to_uart_omap_port(port);
   1230
   1231	wait_for_xmitr(up);
   1232	serial_out(up, UART_TX, ch);
   1233}
   1234
   1235static void
   1236serial_omap_console_write(struct console *co, const char *s,
   1237		unsigned int count)
   1238{
   1239	struct uart_omap_port *up = serial_omap_console_ports[co->index];
   1240	unsigned long flags;
   1241	unsigned int ier;
   1242	int locked = 1;
   1243
   1244	local_irq_save(flags);
   1245	if (up->port.sysrq)
   1246		locked = 0;
   1247	else if (oops_in_progress)
   1248		locked = spin_trylock(&up->port.lock);
   1249	else
   1250		spin_lock(&up->port.lock);
   1251
   1252	/*
   1253	 * First save the IER then disable the interrupts
   1254	 */
   1255	ier = serial_in(up, UART_IER);
   1256	serial_out(up, UART_IER, 0);
   1257
   1258	uart_console_write(&up->port, s, count, serial_omap_console_putchar);
   1259
   1260	/*
   1261	 * Finally, wait for transmitter to become empty
   1262	 * and restore the IER
   1263	 */
   1264	wait_for_xmitr(up);
   1265	serial_out(up, UART_IER, ier);
   1266	/*
   1267	 * The receive handling will happen properly because the
   1268	 * receive ready bit will still be set; it is not cleared
   1269	 * on read.  However, modem control will not, we must
   1270	 * call it if we have saved something in the saved flags
   1271	 * while processing with interrupts off.
   1272	 */
   1273	if (up->msr_saved_flags)
   1274		check_modem_status(up);
   1275
   1276	if (locked)
   1277		spin_unlock(&up->port.lock);
   1278	local_irq_restore(flags);
   1279}
   1280
   1281static int __init
   1282serial_omap_console_setup(struct console *co, char *options)
   1283{
   1284	struct uart_omap_port *up;
   1285	int baud = 115200;
   1286	int bits = 8;
   1287	int parity = 'n';
   1288	int flow = 'n';
   1289
   1290	if (serial_omap_console_ports[co->index] == NULL)
   1291		return -ENODEV;
   1292	up = serial_omap_console_ports[co->index];
   1293
   1294	if (options)
   1295		uart_parse_options(options, &baud, &parity, &bits, &flow);
   1296
   1297	return uart_set_options(&up->port, co, baud, parity, bits, flow);
   1298}
   1299
   1300static struct console serial_omap_console = {
   1301	.name		= OMAP_SERIAL_NAME,
   1302	.write		= serial_omap_console_write,
   1303	.device		= uart_console_device,
   1304	.setup		= serial_omap_console_setup,
   1305	.flags		= CON_PRINTBUFFER,
   1306	.index		= -1,
   1307	.data		= &serial_omap_reg,
   1308};
   1309
   1310static void serial_omap_add_console_port(struct uart_omap_port *up)
   1311{
   1312	serial_omap_console_ports[up->port.line] = up;
   1313}
   1314
   1315#define OMAP_CONSOLE	(&serial_omap_console)
   1316
   1317#else
   1318
   1319#define OMAP_CONSOLE	NULL
   1320
   1321static inline void serial_omap_add_console_port(struct uart_omap_port *up)
   1322{}
   1323
   1324#endif
   1325
   1326/* Enable or disable the rs485 support */
   1327static int
   1328serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
   1329{
   1330	struct uart_omap_port *up = to_uart_omap_port(port);
   1331	unsigned int mode;
   1332	int val;
   1333
   1334	/* Disable interrupts from this port */
   1335	mode = up->ier;
   1336	up->ier = 0;
   1337	serial_out(up, UART_IER, 0);
   1338
   1339	if (up->rts_gpiod) {
   1340		/* enable / disable rts */
   1341		val = (rs485->flags & SER_RS485_ENABLED) ?
   1342			SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
   1343		val = (rs485->flags & val) ? 1 : 0;
   1344		gpiod_set_value(up->rts_gpiod, val);
   1345	}
   1346
   1347	/* Enable interrupts */
   1348	up->ier = mode;
   1349	serial_out(up, UART_IER, up->ier);
   1350
   1351	/* If RS-485 is disabled, make sure the THR interrupt is fired when
   1352	 * TX FIFO is below the trigger level.
   1353	 */
   1354	if (!(rs485->flags & SER_RS485_ENABLED) &&
   1355	    (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
   1356		up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
   1357		serial_out(up, UART_OMAP_SCR, up->scr);
   1358	}
   1359
   1360	return 0;
   1361}
   1362
   1363static const struct uart_ops serial_omap_pops = {
   1364	.tx_empty	= serial_omap_tx_empty,
   1365	.set_mctrl	= serial_omap_set_mctrl,
   1366	.get_mctrl	= serial_omap_get_mctrl,
   1367	.stop_tx	= serial_omap_stop_tx,
   1368	.start_tx	= serial_omap_start_tx,
   1369	.throttle	= serial_omap_throttle,
   1370	.unthrottle	= serial_omap_unthrottle,
   1371	.stop_rx	= serial_omap_stop_rx,
   1372	.enable_ms	= serial_omap_enable_ms,
   1373	.break_ctl	= serial_omap_break_ctl,
   1374	.startup	= serial_omap_startup,
   1375	.shutdown	= serial_omap_shutdown,
   1376	.set_termios	= serial_omap_set_termios,
   1377	.pm		= serial_omap_pm,
   1378	.type		= serial_omap_type,
   1379	.release_port	= serial_omap_release_port,
   1380	.request_port	= serial_omap_request_port,
   1381	.config_port	= serial_omap_config_port,
   1382	.verify_port	= serial_omap_verify_port,
   1383#ifdef CONFIG_CONSOLE_POLL
   1384	.poll_put_char  = serial_omap_poll_put_char,
   1385	.poll_get_char  = serial_omap_poll_get_char,
   1386#endif
   1387};
   1388
   1389static struct uart_driver serial_omap_reg = {
   1390	.owner		= THIS_MODULE,
   1391	.driver_name	= "OMAP-SERIAL",
   1392	.dev_name	= OMAP_SERIAL_NAME,
   1393	.nr		= OMAP_MAX_HSUART_PORTS,
   1394	.cons		= OMAP_CONSOLE,
   1395};
   1396
   1397#ifdef CONFIG_PM_SLEEP
   1398static int serial_omap_prepare(struct device *dev)
   1399{
   1400	struct uart_omap_port *up = dev_get_drvdata(dev);
   1401
   1402	up->is_suspending = true;
   1403
   1404	return 0;
   1405}
   1406
   1407static void serial_omap_complete(struct device *dev)
   1408{
   1409	struct uart_omap_port *up = dev_get_drvdata(dev);
   1410
   1411	up->is_suspending = false;
   1412}
   1413
   1414static int serial_omap_suspend(struct device *dev)
   1415{
   1416	struct uart_omap_port *up = dev_get_drvdata(dev);
   1417
   1418	uart_suspend_port(&serial_omap_reg, &up->port);
   1419	flush_work(&up->qos_work);
   1420
   1421	if (device_may_wakeup(dev))
   1422		serial_omap_enable_wakeup(up, true);
   1423	else
   1424		serial_omap_enable_wakeup(up, false);
   1425
   1426	return 0;
   1427}
   1428
   1429static int serial_omap_resume(struct device *dev)
   1430{
   1431	struct uart_omap_port *up = dev_get_drvdata(dev);
   1432
   1433	if (device_may_wakeup(dev))
   1434		serial_omap_enable_wakeup(up, false);
   1435
   1436	uart_resume_port(&serial_omap_reg, &up->port);
   1437
   1438	return 0;
   1439}
   1440#else
   1441#define serial_omap_prepare NULL
   1442#define serial_omap_complete NULL
   1443#endif /* CONFIG_PM_SLEEP */
   1444
   1445static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
   1446{
   1447	u32 mvr, scheme;
   1448	u16 revision, major, minor;
   1449
   1450	mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
   1451
   1452	/* Check revision register scheme */
   1453	scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
   1454
   1455	switch (scheme) {
   1456	case 0: /* Legacy Scheme: OMAP2/3 */
   1457		/* MINOR_REV[0:4], MAJOR_REV[4:7] */
   1458		major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
   1459					OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
   1460		minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
   1461		break;
   1462	case 1:
   1463		/* New Scheme: OMAP4+ */
   1464		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
   1465		major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
   1466					OMAP_UART_MVR_MAJ_SHIFT;
   1467		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
   1468		break;
   1469	default:
   1470		dev_warn(up->dev,
   1471			"Unknown %s revision, defaulting to highest\n",
   1472			up->name);
   1473		/* highest possible revision */
   1474		major = 0xff;
   1475		minor = 0xff;
   1476	}
   1477
   1478	/* normalize revision for the driver */
   1479	revision = UART_BUILD_REVISION(major, minor);
   1480
   1481	switch (revision) {
   1482	case OMAP_UART_REV_46:
   1483		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
   1484				UART_ERRATA_i291_DMA_FORCEIDLE);
   1485		break;
   1486	case OMAP_UART_REV_52:
   1487		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
   1488				UART_ERRATA_i291_DMA_FORCEIDLE);
   1489		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
   1490		break;
   1491	case OMAP_UART_REV_63:
   1492		up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
   1493		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
   1494		break;
   1495	default:
   1496		break;
   1497	}
   1498}
   1499
   1500static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
   1501{
   1502	struct omap_uart_port_info *omap_up_info;
   1503
   1504	omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
   1505	if (!omap_up_info)
   1506		return NULL; /* out of memory */
   1507
   1508	of_property_read_u32(dev->of_node, "clock-frequency",
   1509					 &omap_up_info->uartclk);
   1510
   1511	omap_up_info->flags = UPF_BOOT_AUTOCONF;
   1512
   1513	return omap_up_info;
   1514}
   1515
   1516static int serial_omap_probe_rs485(struct uart_omap_port *up,
   1517				   struct device *dev)
   1518{
   1519	struct serial_rs485 *rs485conf = &up->port.rs485;
   1520	struct device_node *np = dev->of_node;
   1521	enum gpiod_flags gflags;
   1522	int ret;
   1523
   1524	rs485conf->flags = 0;
   1525	up->rts_gpiod = NULL;
   1526
   1527	if (!np)
   1528		return 0;
   1529
   1530	ret = uart_get_rs485_mode(&up->port);
   1531	if (ret)
   1532		return ret;
   1533
   1534	if (of_property_read_bool(np, "rs485-rts-active-high")) {
   1535		rs485conf->flags |= SER_RS485_RTS_ON_SEND;
   1536		rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
   1537	} else {
   1538		rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
   1539		rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
   1540	}
   1541
   1542	/* check for tx enable gpio */
   1543	gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
   1544		GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
   1545	up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
   1546	if (IS_ERR(up->rts_gpiod)) {
   1547		ret = PTR_ERR(up->rts_gpiod);
   1548	        if (ret == -EPROBE_DEFER)
   1549			return ret;
   1550		/*
   1551		 * FIXME: the code historically ignored any other error than
   1552		 * -EPROBE_DEFER and just went on without GPIO.
   1553		 */
   1554		up->rts_gpiod = NULL;
   1555	} else {
   1556		gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
   1557	}
   1558
   1559	return 0;
   1560}
   1561
   1562static int serial_omap_probe(struct platform_device *pdev)
   1563{
   1564	struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
   1565	struct uart_omap_port *up;
   1566	struct resource *mem;
   1567	void __iomem *base;
   1568	int uartirq = 0;
   1569	int wakeirq = 0;
   1570	int ret;
   1571
   1572	/* The optional wakeirq may be specified in the board dts file */
   1573	if (pdev->dev.of_node) {
   1574		uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
   1575		if (!uartirq)
   1576			return -EPROBE_DEFER;
   1577		wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
   1578		omap_up_info = of_get_uart_port_info(&pdev->dev);
   1579		pdev->dev.platform_data = omap_up_info;
   1580	} else {
   1581		uartirq = platform_get_irq(pdev, 0);
   1582		if (uartirq < 0)
   1583			return -EPROBE_DEFER;
   1584	}
   1585
   1586	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
   1587	if (!up)
   1588		return -ENOMEM;
   1589
   1590	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   1591	base = devm_ioremap_resource(&pdev->dev, mem);
   1592	if (IS_ERR(base))
   1593		return PTR_ERR(base);
   1594
   1595	up->dev = &pdev->dev;
   1596	up->port.dev = &pdev->dev;
   1597	up->port.type = PORT_OMAP;
   1598	up->port.iotype = UPIO_MEM;
   1599	up->port.irq = uartirq;
   1600	up->port.regshift = 2;
   1601	up->port.fifosize = 64;
   1602	up->port.ops = &serial_omap_pops;
   1603	up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
   1604
   1605	if (pdev->dev.of_node)
   1606		ret = of_alias_get_id(pdev->dev.of_node, "serial");
   1607	else
   1608		ret = pdev->id;
   1609
   1610	if (ret < 0) {
   1611		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
   1612			ret);
   1613		goto err_port_line;
   1614	}
   1615	up->port.line = ret;
   1616
   1617	if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
   1618		dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
   1619			OMAP_MAX_HSUART_PORTS);
   1620		ret = -ENXIO;
   1621		goto err_port_line;
   1622	}
   1623
   1624	up->wakeirq = wakeirq;
   1625	if (!up->wakeirq)
   1626		dev_info(up->port.dev, "no wakeirq for uart%d\n",
   1627			 up->port.line);
   1628
   1629	ret = serial_omap_probe_rs485(up, &pdev->dev);
   1630	if (ret < 0)
   1631		goto err_rs485;
   1632
   1633	sprintf(up->name, "OMAP UART%d", up->port.line);
   1634	up->port.mapbase = mem->start;
   1635	up->port.membase = base;
   1636	up->port.flags = omap_up_info->flags;
   1637	up->port.uartclk = omap_up_info->uartclk;
   1638	up->port.rs485_config = serial_omap_config_rs485;
   1639	if (!up->port.uartclk) {
   1640		up->port.uartclk = DEFAULT_CLK_SPEED;
   1641		dev_warn(&pdev->dev,
   1642			 "No clock speed specified: using default: %d\n",
   1643			 DEFAULT_CLK_SPEED);
   1644	}
   1645
   1646	up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
   1647	up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
   1648	cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
   1649	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
   1650
   1651	platform_set_drvdata(pdev, up);
   1652	if (omap_up_info->autosuspend_timeout == 0)
   1653		omap_up_info->autosuspend_timeout = -1;
   1654
   1655	device_init_wakeup(up->dev, true);
   1656
   1657	pm_runtime_enable(&pdev->dev);
   1658
   1659	pm_runtime_get_sync(&pdev->dev);
   1660
   1661	omap_serial_fill_features_erratas(up);
   1662
   1663	ui[up->port.line] = up;
   1664	serial_omap_add_console_port(up);
   1665
   1666	ret = uart_add_one_port(&serial_omap_reg, &up->port);
   1667	if (ret != 0)
   1668		goto err_add_port;
   1669
   1670	return 0;
   1671
   1672err_add_port:
   1673	pm_runtime_put_sync(&pdev->dev);
   1674	pm_runtime_disable(&pdev->dev);
   1675	cpu_latency_qos_remove_request(&up->pm_qos_request);
   1676	device_init_wakeup(up->dev, false);
   1677err_rs485:
   1678err_port_line:
   1679	return ret;
   1680}
   1681
   1682static int serial_omap_remove(struct platform_device *dev)
   1683{
   1684	struct uart_omap_port *up = platform_get_drvdata(dev);
   1685
   1686	pm_runtime_get_sync(up->dev);
   1687
   1688	uart_remove_one_port(&serial_omap_reg, &up->port);
   1689
   1690	pm_runtime_put_sync(up->dev);
   1691	pm_runtime_disable(up->dev);
   1692	cpu_latency_qos_remove_request(&up->pm_qos_request);
   1693	device_init_wakeup(&dev->dev, false);
   1694
   1695	return 0;
   1696}
   1697
   1698/*
   1699 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
   1700 * The access to uart register after MDR1 Access
   1701 * causes UART to corrupt data.
   1702 *
   1703 * Need a delay =
   1704 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
   1705 * give 10 times as much
   1706 */
   1707static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
   1708{
   1709	u8 timeout = 255;
   1710
   1711	serial_out(up, UART_OMAP_MDR1, mdr1);
   1712	udelay(2);
   1713	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
   1714			UART_FCR_CLEAR_RCVR);
   1715	/*
   1716	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
   1717	 * TX_FIFO_E bit is 1.
   1718	 */
   1719	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
   1720				(UART_LSR_THRE | UART_LSR_DR))) {
   1721		timeout--;
   1722		if (!timeout) {
   1723			/* Should *never* happen. we warn and carry on */
   1724			dev_crit(up->dev, "Errata i202: timedout %x\n",
   1725						serial_in(up, UART_LSR));
   1726			break;
   1727		}
   1728		udelay(1);
   1729	}
   1730}
   1731
   1732#ifdef CONFIG_PM
   1733static void serial_omap_restore_context(struct uart_omap_port *up)
   1734{
   1735	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
   1736		serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
   1737	else
   1738		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
   1739
   1740	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
   1741	serial_out(up, UART_EFR, UART_EFR_ECB);
   1742	serial_out(up, UART_LCR, 0x0); /* Operational mode */
   1743	serial_out(up, UART_IER, 0x0);
   1744	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
   1745	serial_out(up, UART_DLL, up->dll);
   1746	serial_out(up, UART_DLM, up->dlh);
   1747	serial_out(up, UART_LCR, 0x0); /* Operational mode */
   1748	serial_out(up, UART_IER, up->ier);
   1749	serial_out(up, UART_FCR, up->fcr);
   1750	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
   1751	serial_out(up, UART_MCR, up->mcr);
   1752	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
   1753	serial_out(up, UART_OMAP_SCR, up->scr);
   1754	serial_out(up, UART_EFR, up->efr);
   1755	serial_out(up, UART_LCR, up->lcr);
   1756	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
   1757		serial_omap_mdr1_errataset(up, up->mdr1);
   1758	else
   1759		serial_out(up, UART_OMAP_MDR1, up->mdr1);
   1760	serial_out(up, UART_OMAP_WER, up->wer);
   1761}
   1762
   1763static int serial_omap_runtime_suspend(struct device *dev)
   1764{
   1765	struct uart_omap_port *up = dev_get_drvdata(dev);
   1766
   1767	if (!up)
   1768		return -EINVAL;
   1769
   1770	/*
   1771	* When using 'no_console_suspend', the console UART must not be
   1772	* suspended. Since driver suspend is managed by runtime suspend,
   1773	* preventing runtime suspend (by returning error) will keep device
   1774	* active during suspend.
   1775	*/
   1776	if (up->is_suspending && !console_suspend_enabled &&
   1777	    uart_console(&up->port))
   1778		return -EBUSY;
   1779
   1780	up->context_loss_cnt = serial_omap_get_context_loss_count(up);
   1781
   1782	serial_omap_enable_wakeup(up, true);
   1783
   1784	up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
   1785	schedule_work(&up->qos_work);
   1786
   1787	return 0;
   1788}
   1789
   1790static int serial_omap_runtime_resume(struct device *dev)
   1791{
   1792	struct uart_omap_port *up = dev_get_drvdata(dev);
   1793
   1794	int loss_cnt = serial_omap_get_context_loss_count(up);
   1795
   1796	serial_omap_enable_wakeup(up, false);
   1797
   1798	if (loss_cnt < 0) {
   1799		dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
   1800			loss_cnt);
   1801		serial_omap_restore_context(up);
   1802	} else if (up->context_loss_cnt != loss_cnt) {
   1803		serial_omap_restore_context(up);
   1804	}
   1805	up->latency = up->calc_latency;
   1806	schedule_work(&up->qos_work);
   1807
   1808	return 0;
   1809}
   1810#endif
   1811
   1812static const struct dev_pm_ops serial_omap_dev_pm_ops = {
   1813	SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
   1814	SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
   1815				serial_omap_runtime_resume, NULL)
   1816	.prepare        = serial_omap_prepare,
   1817	.complete       = serial_omap_complete,
   1818};
   1819
   1820#if defined(CONFIG_OF)
   1821static const struct of_device_id omap_serial_of_match[] = {
   1822	{ .compatible = "ti,omap2-uart" },
   1823	{ .compatible = "ti,omap3-uart" },
   1824	{ .compatible = "ti,omap4-uart" },
   1825	{},
   1826};
   1827MODULE_DEVICE_TABLE(of, omap_serial_of_match);
   1828#endif
   1829
   1830static struct platform_driver serial_omap_driver = {
   1831	.probe          = serial_omap_probe,
   1832	.remove         = serial_omap_remove,
   1833	.driver		= {
   1834		.name	= OMAP_SERIAL_DRIVER_NAME,
   1835		.pm	= &serial_omap_dev_pm_ops,
   1836		.of_match_table = of_match_ptr(omap_serial_of_match),
   1837	},
   1838};
   1839
   1840static int __init serial_omap_init(void)
   1841{
   1842	int ret;
   1843
   1844	ret = uart_register_driver(&serial_omap_reg);
   1845	if (ret != 0)
   1846		return ret;
   1847	ret = platform_driver_register(&serial_omap_driver);
   1848	if (ret != 0)
   1849		uart_unregister_driver(&serial_omap_reg);
   1850	return ret;
   1851}
   1852
   1853static void __exit serial_omap_exit(void)
   1854{
   1855	platform_driver_unregister(&serial_omap_driver);
   1856	uart_unregister_driver(&serial_omap_reg);
   1857}
   1858
   1859module_init(serial_omap_init);
   1860module_exit(serial_omap_exit);
   1861
   1862MODULE_DESCRIPTION("OMAP High Speed UART driver");
   1863MODULE_LICENSE("GPL");
   1864MODULE_AUTHOR("Texas Instruments Inc");