cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bits.h (4390B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * bits.h - register bits of the ChipIdea USB IP core
      4 *
      5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
      6 *
      7 * Author: David Lopo
      8 */
      9
     10#ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
     11#define __DRIVERS_USB_CHIPIDEA_BITS_H
     12
     13#include <linux/usb/ehci_def.h>
     14
     15/*
     16 * ID
     17 * For 1.x revision, bit24 - bit31 are reserved
     18 * For 2.x revision, bit25 - bit28 are 0x2
     19 */
     20#define TAG		      (0x1F << 16)
     21#define REVISION	      (0xF << 21)
     22#define VERSION		      (0xF << 25)
     23#define CIVERSION	      (0x7 << 29)
     24
     25/* SBUSCFG */
     26#define AHBBRST_MASK		0x7
     27
     28/* HCCPARAMS */
     29#define HCCPARAMS_LEN         BIT(17)
     30
     31/* DCCPARAMS */
     32#define DCCPARAMS_DEN         (0x1F << 0)
     33#define DCCPARAMS_DC          BIT(7)
     34#define DCCPARAMS_HC          BIT(8)
     35
     36/* TESTMODE */
     37#define TESTMODE_FORCE        BIT(0)
     38
     39/* USBCMD */
     40#define USBCMD_RS             BIT(0)
     41#define USBCMD_RST            BIT(1)
     42#define USBCMD_SUTW           BIT(13)
     43#define USBCMD_ATDTW          BIT(14)
     44
     45/* USBSTS & USBINTR */
     46#define USBi_UI               BIT(0)
     47#define USBi_UEI              BIT(1)
     48#define USBi_PCI              BIT(2)
     49#define USBi_URI              BIT(6)
     50#define USBi_SLI              BIT(8)
     51
     52/* DEVICEADDR */
     53#define DEVICEADDR_USBADRA    BIT(24)
     54#define DEVICEADDR_USBADR     (0x7FUL << 25)
     55
     56/* TTCTRL */
     57#define TTCTRL_TTHA_MASK	(0x7fUL << 24)
     58/* Set non-zero value for internal TT Hub address representation */
     59#define TTCTRL_TTHA		(0x7fUL << 24)
     60
     61/* BURSTSIZE */
     62#define RX_BURST_MASK		0xff
     63#define TX_BURST_MASK		0xff00
     64
     65/* PORTSC */
     66#define PORTSC_CCS            BIT(0)
     67#define PORTSC_CSC            BIT(1)
     68#define PORTSC_PEC            BIT(3)
     69#define PORTSC_OCC            BIT(5)
     70#define PORTSC_FPR            BIT(6)
     71#define PORTSC_SUSP           BIT(7)
     72#define PORTSC_HSP            BIT(9)
     73#define PORTSC_PP             BIT(12)
     74#define PORTSC_PTC            (0x0FUL << 16)
     75#define PORTSC_WKCN           BIT(20)
     76#define PORTSC_PHCD(d)	      ((d) ? BIT(22) : BIT(23))
     77/* PTS and PTW for non lpm version only */
     78#define PORTSC_PFSC           BIT(24)
     79#define PORTSC_PTS(d)						\
     80	(u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
     81#define PORTSC_PTW            BIT(28)
     82#define PORTSC_STS            BIT(29)
     83
     84#define PORTSC_W1C_BITS						\
     85	(PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
     86
     87/* DEVLC */
     88#define DEVLC_PFSC            BIT(23)
     89#define DEVLC_PSPD            (0x03UL << 25)
     90#define DEVLC_PSPD_HS         (0x02UL << 25)
     91#define DEVLC_PTW             BIT(27)
     92#define DEVLC_STS             BIT(28)
     93#define DEVLC_PTS(d)          (u32)(((d) & 0x7) << 29)
     94
     95/* Encoding for DEVLC_PTS and PORTSC_PTS */
     96#define PTS_UTMI              0
     97#define PTS_ULPI              2
     98#define PTS_SERIAL            3
     99#define PTS_HSIC              4
    100
    101/* OTGSC */
    102#define OTGSC_IDPU	      BIT(5)
    103#define OTGSC_HADP	      BIT(6)
    104#define OTGSC_HABA	      BIT(7)
    105#define OTGSC_ID	      BIT(8)
    106#define OTGSC_AVV	      BIT(9)
    107#define OTGSC_ASV	      BIT(10)
    108#define OTGSC_BSV	      BIT(11)
    109#define OTGSC_BSE	      BIT(12)
    110#define OTGSC_IDIS	      BIT(16)
    111#define OTGSC_AVVIS	      BIT(17)
    112#define OTGSC_ASVIS	      BIT(18)
    113#define OTGSC_BSVIS	      BIT(19)
    114#define OTGSC_BSEIS	      BIT(20)
    115#define OTGSC_1MSIS	      BIT(21)
    116#define OTGSC_DPIS	      BIT(22)
    117#define OTGSC_IDIE	      BIT(24)
    118#define OTGSC_AVVIE	      BIT(25)
    119#define OTGSC_ASVIE	      BIT(26)
    120#define OTGSC_BSVIE	      BIT(27)
    121#define OTGSC_BSEIE	      BIT(28)
    122#define OTGSC_1MSIE	      BIT(29)
    123#define OTGSC_DPIE	      BIT(30)
    124#define OTGSC_INT_EN_BITS	(OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
    125				| OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
    126				| OTGSC_DPIE)
    127#define OTGSC_INT_STATUS_BITS	(OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS	\
    128				| OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
    129				| OTGSC_DPIS)
    130
    131/* USBMODE */
    132#define USBMODE_CM            (0x03UL <<  0)
    133#define USBMODE_CM_DC         (0x02UL <<  0)
    134#define USBMODE_SLOM          BIT(3)
    135#define USBMODE_CI_SDIS       BIT(4)
    136
    137/* ENDPTCTRL */
    138#define ENDPTCTRL_RXS         BIT(0)
    139#define ENDPTCTRL_RXT         (0x03UL <<  2)
    140#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
    141#define ENDPTCTRL_RXE         BIT(7)
    142#define ENDPTCTRL_TXS         BIT(16)
    143#define ENDPTCTRL_TXT         (0x03UL << 18)
    144#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
    145#define ENDPTCTRL_TXE         BIT(23)
    146
    147#endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */