cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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core.c (34427B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * core.c - ChipIdea USB IP core family device controller
      4 *
      5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
      6 * Copyright (C) 2020 NXP
      7 *
      8 * Author: David Lopo
      9 *	   Peter Chen <peter.chen@nxp.com>
     10 *
     11 * Main Features:
     12 * - Four transfers are supported, usbtest is passed
     13 * - USB Certification for gadget: CH9 and Mass Storage are passed
     14 * - Low power mode
     15 * - USB wakeup
     16 */
     17#include <linux/delay.h>
     18#include <linux/device.h>
     19#include <linux/dma-mapping.h>
     20#include <linux/extcon.h>
     21#include <linux/phy/phy.h>
     22#include <linux/platform_device.h>
     23#include <linux/module.h>
     24#include <linux/idr.h>
     25#include <linux/interrupt.h>
     26#include <linux/io.h>
     27#include <linux/kernel.h>
     28#include <linux/slab.h>
     29#include <linux/pm_runtime.h>
     30#include <linux/pinctrl/consumer.h>
     31#include <linux/usb/ch9.h>
     32#include <linux/usb/gadget.h>
     33#include <linux/usb/otg.h>
     34#include <linux/usb/chipidea.h>
     35#include <linux/usb/of.h>
     36#include <linux/of.h>
     37#include <linux/regulator/consumer.h>
     38#include <linux/usb/ehci_def.h>
     39
     40#include "ci.h"
     41#include "udc.h"
     42#include "bits.h"
     43#include "host.h"
     44#include "otg.h"
     45#include "otg_fsm.h"
     46
     47/* Controller register map */
     48static const u8 ci_regs_nolpm[] = {
     49	[CAP_CAPLENGTH]		= 0x00U,
     50	[CAP_HCCPARAMS]		= 0x08U,
     51	[CAP_DCCPARAMS]		= 0x24U,
     52	[CAP_TESTMODE]		= 0x38U,
     53	[OP_USBCMD]		= 0x00U,
     54	[OP_USBSTS]		= 0x04U,
     55	[OP_USBINTR]		= 0x08U,
     56	[OP_DEVICEADDR]		= 0x14U,
     57	[OP_ENDPTLISTADDR]	= 0x18U,
     58	[OP_TTCTRL]		= 0x1CU,
     59	[OP_BURSTSIZE]		= 0x20U,
     60	[OP_ULPI_VIEWPORT]	= 0x30U,
     61	[OP_PORTSC]		= 0x44U,
     62	[OP_DEVLC]		= 0x84U,
     63	[OP_OTGSC]		= 0x64U,
     64	[OP_USBMODE]		= 0x68U,
     65	[OP_ENDPTSETUPSTAT]	= 0x6CU,
     66	[OP_ENDPTPRIME]		= 0x70U,
     67	[OP_ENDPTFLUSH]		= 0x74U,
     68	[OP_ENDPTSTAT]		= 0x78U,
     69	[OP_ENDPTCOMPLETE]	= 0x7CU,
     70	[OP_ENDPTCTRL]		= 0x80U,
     71};
     72
     73static const u8 ci_regs_lpm[] = {
     74	[CAP_CAPLENGTH]		= 0x00U,
     75	[CAP_HCCPARAMS]		= 0x08U,
     76	[CAP_DCCPARAMS]		= 0x24U,
     77	[CAP_TESTMODE]		= 0xFCU,
     78	[OP_USBCMD]		= 0x00U,
     79	[OP_USBSTS]		= 0x04U,
     80	[OP_USBINTR]		= 0x08U,
     81	[OP_DEVICEADDR]		= 0x14U,
     82	[OP_ENDPTLISTADDR]	= 0x18U,
     83	[OP_TTCTRL]		= 0x1CU,
     84	[OP_BURSTSIZE]		= 0x20U,
     85	[OP_ULPI_VIEWPORT]	= 0x30U,
     86	[OP_PORTSC]		= 0x44U,
     87	[OP_DEVLC]		= 0x84U,
     88	[OP_OTGSC]		= 0xC4U,
     89	[OP_USBMODE]		= 0xC8U,
     90	[OP_ENDPTSETUPSTAT]	= 0xD8U,
     91	[OP_ENDPTPRIME]		= 0xDCU,
     92	[OP_ENDPTFLUSH]		= 0xE0U,
     93	[OP_ENDPTSTAT]		= 0xE4U,
     94	[OP_ENDPTCOMPLETE]	= 0xE8U,
     95	[OP_ENDPTCTRL]		= 0xECU,
     96};
     97
     98static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
     99{
    100	int i;
    101
    102	for (i = 0; i < OP_ENDPTCTRL; i++)
    103		ci->hw_bank.regmap[i] =
    104			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
    105			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
    106
    107	for (; i <= OP_LAST; i++)
    108		ci->hw_bank.regmap[i] = ci->hw_bank.op +
    109			4 * (i - OP_ENDPTCTRL) +
    110			(is_lpm
    111			 ? ci_regs_lpm[OP_ENDPTCTRL]
    112			 : ci_regs_nolpm[OP_ENDPTCTRL]);
    113
    114}
    115
    116static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
    117{
    118	int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
    119	enum ci_revision rev = CI_REVISION_UNKNOWN;
    120
    121	if (ver == 0x2) {
    122		rev = hw_read_id_reg(ci, ID_ID, REVISION)
    123			>> __ffs(REVISION);
    124		rev += CI_REVISION_20;
    125	} else if (ver == 0x0) {
    126		rev = CI_REVISION_1X;
    127	}
    128
    129	return rev;
    130}
    131
    132/**
    133 * hw_read_intr_enable: returns interrupt enable register
    134 *
    135 * @ci: the controller
    136 *
    137 * This function returns register data
    138 */
    139u32 hw_read_intr_enable(struct ci_hdrc *ci)
    140{
    141	return hw_read(ci, OP_USBINTR, ~0);
    142}
    143
    144/**
    145 * hw_read_intr_status: returns interrupt status register
    146 *
    147 * @ci: the controller
    148 *
    149 * This function returns register data
    150 */
    151u32 hw_read_intr_status(struct ci_hdrc *ci)
    152{
    153	return hw_read(ci, OP_USBSTS, ~0);
    154}
    155
    156/**
    157 * hw_port_test_set: writes port test mode (execute without interruption)
    158 * @ci: the controller
    159 * @mode: new value
    160 *
    161 * This function returns an error code
    162 */
    163int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
    164{
    165	const u8 TEST_MODE_MAX = 7;
    166
    167	if (mode > TEST_MODE_MAX)
    168		return -EINVAL;
    169
    170	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
    171	return 0;
    172}
    173
    174/**
    175 * hw_port_test_get: reads port test mode value
    176 *
    177 * @ci: the controller
    178 *
    179 * This function returns port test mode value
    180 */
    181u8 hw_port_test_get(struct ci_hdrc *ci)
    182{
    183	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
    184}
    185
    186static void hw_wait_phy_stable(void)
    187{
    188	/*
    189	 * The phy needs some delay to output the stable status from low
    190	 * power mode. And for OTGSC, the status inputs are debounced
    191	 * using a 1 ms time constant, so, delay 2ms for controller to get
    192	 * the stable status, like vbus and id when the phy leaves low power.
    193	 */
    194	usleep_range(2000, 2500);
    195}
    196
    197/* The PHY enters/leaves low power mode */
    198static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
    199{
    200	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
    201	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
    202
    203	if (enable && !lpm)
    204		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
    205				PORTSC_PHCD(ci->hw_bank.lpm));
    206	else if (!enable && lpm)
    207		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
    208				0);
    209}
    210
    211static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
    212{
    213	return ci->platdata->enter_lpm(ci, enable);
    214}
    215
    216static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
    217{
    218	u32 reg;
    219
    220	/* bank is a module variable */
    221	ci->hw_bank.abs = base;
    222
    223	ci->hw_bank.cap = ci->hw_bank.abs;
    224	ci->hw_bank.cap += ci->platdata->capoffset;
    225	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
    226
    227	hw_alloc_regmap(ci, false);
    228	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
    229		__ffs(HCCPARAMS_LEN);
    230	ci->hw_bank.lpm  = reg;
    231	if (reg)
    232		hw_alloc_regmap(ci, !!reg);
    233	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
    234	ci->hw_bank.size += OP_LAST;
    235	ci->hw_bank.size /= sizeof(u32);
    236
    237	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
    238		__ffs(DCCPARAMS_DEN);
    239	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
    240
    241	if (ci->hw_ep_max > ENDPT_MAX)
    242		return -ENODEV;
    243
    244	ci_hdrc_enter_lpm(ci, false);
    245
    246	/* Disable all interrupts bits */
    247	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
    248
    249	/* Clear all interrupts status bits*/
    250	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
    251
    252	ci->rev = ci_get_revision(ci);
    253
    254	dev_dbg(ci->dev,
    255		"revision: %d, lpm: %d; cap: %px op: %px\n",
    256		ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
    257
    258	/* setup lock mode ? */
    259
    260	/* ENDPTSETUPSTAT is '0' by default */
    261
    262	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
    263
    264	return 0;
    265}
    266
    267void hw_phymode_configure(struct ci_hdrc *ci)
    268{
    269	u32 portsc, lpm, sts = 0;
    270
    271	switch (ci->platdata->phy_mode) {
    272	case USBPHY_INTERFACE_MODE_UTMI:
    273		portsc = PORTSC_PTS(PTS_UTMI);
    274		lpm = DEVLC_PTS(PTS_UTMI);
    275		break;
    276	case USBPHY_INTERFACE_MODE_UTMIW:
    277		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
    278		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
    279		break;
    280	case USBPHY_INTERFACE_MODE_ULPI:
    281		portsc = PORTSC_PTS(PTS_ULPI);
    282		lpm = DEVLC_PTS(PTS_ULPI);
    283		break;
    284	case USBPHY_INTERFACE_MODE_SERIAL:
    285		portsc = PORTSC_PTS(PTS_SERIAL);
    286		lpm = DEVLC_PTS(PTS_SERIAL);
    287		sts = 1;
    288		break;
    289	case USBPHY_INTERFACE_MODE_HSIC:
    290		portsc = PORTSC_PTS(PTS_HSIC);
    291		lpm = DEVLC_PTS(PTS_HSIC);
    292		break;
    293	default:
    294		return;
    295	}
    296
    297	if (ci->hw_bank.lpm) {
    298		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
    299		if (sts)
    300			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
    301	} else {
    302		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
    303		if (sts)
    304			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
    305	}
    306}
    307EXPORT_SYMBOL_GPL(hw_phymode_configure);
    308
    309/**
    310 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
    311 * interfaces
    312 * @ci: the controller
    313 *
    314 * This function returns an error code if the phy failed to init
    315 */
    316static int _ci_usb_phy_init(struct ci_hdrc *ci)
    317{
    318	int ret;
    319
    320	if (ci->phy) {
    321		ret = phy_init(ci->phy);
    322		if (ret)
    323			return ret;
    324
    325		ret = phy_power_on(ci->phy);
    326		if (ret) {
    327			phy_exit(ci->phy);
    328			return ret;
    329		}
    330	} else {
    331		ret = usb_phy_init(ci->usb_phy);
    332	}
    333
    334	return ret;
    335}
    336
    337/**
    338 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
    339 * interfaces
    340 * @ci: the controller
    341 */
    342static void ci_usb_phy_exit(struct ci_hdrc *ci)
    343{
    344	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
    345		return;
    346
    347	if (ci->phy) {
    348		phy_power_off(ci->phy);
    349		phy_exit(ci->phy);
    350	} else {
    351		usb_phy_shutdown(ci->usb_phy);
    352	}
    353}
    354
    355/**
    356 * ci_usb_phy_init: initialize phy according to different phy type
    357 * @ci: the controller
    358 *
    359 * This function returns an error code if usb_phy_init has failed
    360 */
    361static int ci_usb_phy_init(struct ci_hdrc *ci)
    362{
    363	int ret;
    364
    365	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
    366		return 0;
    367
    368	switch (ci->platdata->phy_mode) {
    369	case USBPHY_INTERFACE_MODE_UTMI:
    370	case USBPHY_INTERFACE_MODE_UTMIW:
    371	case USBPHY_INTERFACE_MODE_HSIC:
    372		ret = _ci_usb_phy_init(ci);
    373		if (!ret)
    374			hw_wait_phy_stable();
    375		else
    376			return ret;
    377		hw_phymode_configure(ci);
    378		break;
    379	case USBPHY_INTERFACE_MODE_ULPI:
    380	case USBPHY_INTERFACE_MODE_SERIAL:
    381		hw_phymode_configure(ci);
    382		ret = _ci_usb_phy_init(ci);
    383		if (ret)
    384			return ret;
    385		break;
    386	default:
    387		ret = _ci_usb_phy_init(ci);
    388		if (!ret)
    389			hw_wait_phy_stable();
    390	}
    391
    392	return ret;
    393}
    394
    395
    396/**
    397 * ci_platform_configure: do controller configure
    398 * @ci: the controller
    399 *
    400 */
    401void ci_platform_configure(struct ci_hdrc *ci)
    402{
    403	bool is_device_mode, is_host_mode;
    404
    405	is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
    406	is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
    407
    408	if (is_device_mode) {
    409		phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
    410
    411		if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
    412			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
    413				 USBMODE_CI_SDIS);
    414	}
    415
    416	if (is_host_mode) {
    417		phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
    418
    419		if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
    420			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
    421				 USBMODE_CI_SDIS);
    422	}
    423
    424	if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
    425		if (ci->hw_bank.lpm)
    426			hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
    427		else
    428			hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
    429	}
    430
    431	if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
    432		hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
    433
    434	hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
    435
    436	if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
    437		hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
    438			ci->platdata->ahb_burst_config);
    439
    440	/* override burst size, take effect only when ahb_burst_config is 0 */
    441	if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
    442		if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
    443			hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
    444			ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
    445
    446		if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
    447			hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
    448				ci->platdata->rx_burst_size);
    449	}
    450}
    451
    452/**
    453 * hw_controller_reset: do controller reset
    454 * @ci: the controller
    455  *
    456 * This function returns an error code
    457 */
    458static int hw_controller_reset(struct ci_hdrc *ci)
    459{
    460	int count = 0;
    461
    462	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
    463	while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
    464		udelay(10);
    465		if (count++ > 1000)
    466			return -ETIMEDOUT;
    467	}
    468
    469	return 0;
    470}
    471
    472/**
    473 * hw_device_reset: resets chip (execute without interruption)
    474 * @ci: the controller
    475 *
    476 * This function returns an error code
    477 */
    478int hw_device_reset(struct ci_hdrc *ci)
    479{
    480	int ret;
    481
    482	/* should flush & stop before reset */
    483	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
    484	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
    485
    486	ret = hw_controller_reset(ci);
    487	if (ret) {
    488		dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
    489		return ret;
    490	}
    491
    492	if (ci->platdata->notify_event) {
    493		ret = ci->platdata->notify_event(ci,
    494			CI_HDRC_CONTROLLER_RESET_EVENT);
    495		if (ret)
    496			return ret;
    497	}
    498
    499	/* USBMODE should be configured step by step */
    500	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
    501	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
    502	/* HW >= 2.3 */
    503	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
    504
    505	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
    506		dev_err(ci->dev, "cannot enter in %s device mode\n",
    507			ci_role(ci)->name);
    508		dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
    509		return -ENODEV;
    510	}
    511
    512	ci_platform_configure(ci);
    513
    514	return 0;
    515}
    516
    517static irqreturn_t ci_irq_handler(int irq, void *data)
    518{
    519	struct ci_hdrc *ci = data;
    520	irqreturn_t ret = IRQ_NONE;
    521	u32 otgsc = 0;
    522
    523	if (ci->in_lpm) {
    524		disable_irq_nosync(irq);
    525		ci->wakeup_int = true;
    526		pm_runtime_get(ci->dev);
    527		return IRQ_HANDLED;
    528	}
    529
    530	if (ci->is_otg) {
    531		otgsc = hw_read_otgsc(ci, ~0);
    532		if (ci_otg_is_fsm_mode(ci)) {
    533			ret = ci_otg_fsm_irq(ci);
    534			if (ret == IRQ_HANDLED)
    535				return ret;
    536		}
    537	}
    538
    539	/*
    540	 * Handle id change interrupt, it indicates device/host function
    541	 * switch.
    542	 */
    543	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
    544		ci->id_event = true;
    545		/* Clear ID change irq status */
    546		hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
    547		ci_otg_queue_work(ci);
    548		return IRQ_HANDLED;
    549	}
    550
    551	/*
    552	 * Handle vbus change interrupt, it indicates device connection
    553	 * and disconnection events.
    554	 */
    555	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
    556		ci->b_sess_valid_event = true;
    557		/* Clear BSV irq */
    558		hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
    559		ci_otg_queue_work(ci);
    560		return IRQ_HANDLED;
    561	}
    562
    563	/* Handle device/host interrupt */
    564	if (ci->role != CI_ROLE_END)
    565		ret = ci_role(ci)->irq(ci);
    566
    567	return ret;
    568}
    569
    570static void ci_irq(struct ci_hdrc *ci)
    571{
    572	unsigned long flags;
    573
    574	local_irq_save(flags);
    575	ci_irq_handler(ci->irq, ci);
    576	local_irq_restore(flags);
    577}
    578
    579static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
    580			     void *ptr)
    581{
    582	struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
    583	struct ci_hdrc *ci = cbl->ci;
    584
    585	cbl->connected = event;
    586	cbl->changed = true;
    587
    588	ci_irq(ci);
    589	return NOTIFY_DONE;
    590}
    591
    592static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
    593{
    594	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
    595	enum usb_role role;
    596	unsigned long flags;
    597
    598	spin_lock_irqsave(&ci->lock, flags);
    599	role = ci_role_to_usb_role(ci);
    600	spin_unlock_irqrestore(&ci->lock, flags);
    601
    602	return role;
    603}
    604
    605static int ci_usb_role_switch_set(struct usb_role_switch *sw,
    606				  enum usb_role role)
    607{
    608	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
    609	struct ci_hdrc_cable *cable = NULL;
    610	enum usb_role current_role = ci_role_to_usb_role(ci);
    611	enum ci_role ci_role = usb_role_to_ci_role(role);
    612	unsigned long flags;
    613
    614	if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
    615	    (current_role == role))
    616		return 0;
    617
    618	pm_runtime_get_sync(ci->dev);
    619	/* Stop current role */
    620	spin_lock_irqsave(&ci->lock, flags);
    621	if (current_role == USB_ROLE_DEVICE)
    622		cable = &ci->platdata->vbus_extcon;
    623	else if (current_role == USB_ROLE_HOST)
    624		cable = &ci->platdata->id_extcon;
    625
    626	if (cable) {
    627		cable->changed = true;
    628		cable->connected = false;
    629		ci_irq(ci);
    630		spin_unlock_irqrestore(&ci->lock, flags);
    631		if (ci->wq && role != USB_ROLE_NONE)
    632			flush_workqueue(ci->wq);
    633		spin_lock_irqsave(&ci->lock, flags);
    634	}
    635
    636	cable = NULL;
    637
    638	/* Start target role */
    639	if (role == USB_ROLE_DEVICE)
    640		cable = &ci->platdata->vbus_extcon;
    641	else if (role == USB_ROLE_HOST)
    642		cable = &ci->platdata->id_extcon;
    643
    644	if (cable) {
    645		cable->changed = true;
    646		cable->connected = true;
    647		ci_irq(ci);
    648	}
    649	spin_unlock_irqrestore(&ci->lock, flags);
    650	pm_runtime_put_sync(ci->dev);
    651
    652	return 0;
    653}
    654
    655static struct usb_role_switch_desc ci_role_switch = {
    656	.set = ci_usb_role_switch_set,
    657	.get = ci_usb_role_switch_get,
    658	.allow_userspace_control = true,
    659};
    660
    661static int ci_get_platdata(struct device *dev,
    662		struct ci_hdrc_platform_data *platdata)
    663{
    664	struct extcon_dev *ext_vbus, *ext_id;
    665	struct ci_hdrc_cable *cable;
    666	int ret;
    667
    668	if (!platdata->phy_mode)
    669		platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
    670
    671	if (!platdata->dr_mode)
    672		platdata->dr_mode = usb_get_dr_mode(dev);
    673
    674	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
    675		platdata->dr_mode = USB_DR_MODE_OTG;
    676
    677	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
    678		/* Get the vbus regulator */
    679		platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
    680		if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
    681			return -EPROBE_DEFER;
    682		} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
    683			/* no vbus regulator is needed */
    684			platdata->reg_vbus = NULL;
    685		} else if (IS_ERR(platdata->reg_vbus)) {
    686			dev_err(dev, "Getting regulator error: %ld\n",
    687				PTR_ERR(platdata->reg_vbus));
    688			return PTR_ERR(platdata->reg_vbus);
    689		}
    690		/* Get TPL support */
    691		if (!platdata->tpl_support)
    692			platdata->tpl_support =
    693				of_usb_host_tpl_support(dev->of_node);
    694	}
    695
    696	if (platdata->dr_mode == USB_DR_MODE_OTG) {
    697		/* We can support HNP and SRP of OTG 2.0 */
    698		platdata->ci_otg_caps.otg_rev = 0x0200;
    699		platdata->ci_otg_caps.hnp_support = true;
    700		platdata->ci_otg_caps.srp_support = true;
    701
    702		/* Update otg capabilities by DT properties */
    703		ret = of_usb_update_otg_caps(dev->of_node,
    704					&platdata->ci_otg_caps);
    705		if (ret)
    706			return ret;
    707	}
    708
    709	if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
    710		platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
    711
    712	of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
    713				     &platdata->phy_clkgate_delay_us);
    714
    715	platdata->itc_setting = 1;
    716
    717	of_property_read_u32(dev->of_node, "itc-setting",
    718					&platdata->itc_setting);
    719
    720	ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
    721				&platdata->ahb_burst_config);
    722	if (!ret) {
    723		platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
    724	} else if (ret != -EINVAL) {
    725		dev_err(dev, "failed to get ahb-burst-config\n");
    726		return ret;
    727	}
    728
    729	ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
    730				&platdata->tx_burst_size);
    731	if (!ret) {
    732		platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
    733	} else if (ret != -EINVAL) {
    734		dev_err(dev, "failed to get tx-burst-size-dword\n");
    735		return ret;
    736	}
    737
    738	ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
    739				&platdata->rx_burst_size);
    740	if (!ret) {
    741		platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
    742	} else if (ret != -EINVAL) {
    743		dev_err(dev, "failed to get rx-burst-size-dword\n");
    744		return ret;
    745	}
    746
    747	if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
    748		platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
    749
    750	ext_id = ERR_PTR(-ENODEV);
    751	ext_vbus = ERR_PTR(-ENODEV);
    752	if (of_property_read_bool(dev->of_node, "extcon")) {
    753		/* Each one of them is not mandatory */
    754		ext_vbus = extcon_get_edev_by_phandle(dev, 0);
    755		if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
    756			return PTR_ERR(ext_vbus);
    757
    758		ext_id = extcon_get_edev_by_phandle(dev, 1);
    759		if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
    760			return PTR_ERR(ext_id);
    761	}
    762
    763	cable = &platdata->vbus_extcon;
    764	cable->nb.notifier_call = ci_cable_notifier;
    765	cable->edev = ext_vbus;
    766
    767	if (!IS_ERR(ext_vbus)) {
    768		ret = extcon_get_state(cable->edev, EXTCON_USB);
    769		if (ret)
    770			cable->connected = true;
    771		else
    772			cable->connected = false;
    773	}
    774
    775	cable = &platdata->id_extcon;
    776	cable->nb.notifier_call = ci_cable_notifier;
    777	cable->edev = ext_id;
    778
    779	if (!IS_ERR(ext_id)) {
    780		ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
    781		if (ret)
    782			cable->connected = true;
    783		else
    784			cable->connected = false;
    785	}
    786
    787	if (device_property_read_bool(dev, "usb-role-switch"))
    788		ci_role_switch.fwnode = dev->fwnode;
    789
    790	platdata->pctl = devm_pinctrl_get(dev);
    791	if (!IS_ERR(platdata->pctl)) {
    792		struct pinctrl_state *p;
    793
    794		p = pinctrl_lookup_state(platdata->pctl, "default");
    795		if (!IS_ERR(p))
    796			platdata->pins_default = p;
    797
    798		p = pinctrl_lookup_state(platdata->pctl, "host");
    799		if (!IS_ERR(p))
    800			platdata->pins_host = p;
    801
    802		p = pinctrl_lookup_state(platdata->pctl, "device");
    803		if (!IS_ERR(p))
    804			platdata->pins_device = p;
    805	}
    806
    807	if (!platdata->enter_lpm)
    808		platdata->enter_lpm = ci_hdrc_enter_lpm_common;
    809
    810	return 0;
    811}
    812
    813static int ci_extcon_register(struct ci_hdrc *ci)
    814{
    815	struct ci_hdrc_cable *id, *vbus;
    816	int ret;
    817
    818	id = &ci->platdata->id_extcon;
    819	id->ci = ci;
    820	if (!IS_ERR_OR_NULL(id->edev)) {
    821		ret = devm_extcon_register_notifier(ci->dev, id->edev,
    822						EXTCON_USB_HOST, &id->nb);
    823		if (ret < 0) {
    824			dev_err(ci->dev, "register ID failed\n");
    825			return ret;
    826		}
    827	}
    828
    829	vbus = &ci->platdata->vbus_extcon;
    830	vbus->ci = ci;
    831	if (!IS_ERR_OR_NULL(vbus->edev)) {
    832		ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
    833						EXTCON_USB, &vbus->nb);
    834		if (ret < 0) {
    835			dev_err(ci->dev, "register VBUS failed\n");
    836			return ret;
    837		}
    838	}
    839
    840	return 0;
    841}
    842
    843static DEFINE_IDA(ci_ida);
    844
    845struct platform_device *ci_hdrc_add_device(struct device *dev,
    846			struct resource *res, int nres,
    847			struct ci_hdrc_platform_data *platdata)
    848{
    849	struct platform_device *pdev;
    850	int id, ret;
    851
    852	ret = ci_get_platdata(dev, platdata);
    853	if (ret)
    854		return ERR_PTR(ret);
    855
    856	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
    857	if (id < 0)
    858		return ERR_PTR(id);
    859
    860	pdev = platform_device_alloc("ci_hdrc", id);
    861	if (!pdev) {
    862		ret = -ENOMEM;
    863		goto put_id;
    864	}
    865
    866	pdev->dev.parent = dev;
    867	device_set_of_node_from_dev(&pdev->dev, dev);
    868
    869	ret = platform_device_add_resources(pdev, res, nres);
    870	if (ret)
    871		goto err;
    872
    873	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
    874	if (ret)
    875		goto err;
    876
    877	ret = platform_device_add(pdev);
    878	if (ret)
    879		goto err;
    880
    881	return pdev;
    882
    883err:
    884	platform_device_put(pdev);
    885put_id:
    886	ida_simple_remove(&ci_ida, id);
    887	return ERR_PTR(ret);
    888}
    889EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
    890
    891void ci_hdrc_remove_device(struct platform_device *pdev)
    892{
    893	int id = pdev->id;
    894	platform_device_unregister(pdev);
    895	ida_simple_remove(&ci_ida, id);
    896}
    897EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
    898
    899/**
    900 * ci_hdrc_query_available_role: get runtime available operation mode
    901 *
    902 * The glue layer can get current operation mode (host/peripheral/otg)
    903 * This function should be called after ci core device has created.
    904 *
    905 * @pdev: the platform device of ci core.
    906 *
    907 * Return runtime usb_dr_mode.
    908 */
    909enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
    910{
    911	struct ci_hdrc *ci = platform_get_drvdata(pdev);
    912
    913	if (!ci)
    914		return USB_DR_MODE_UNKNOWN;
    915	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
    916		return USB_DR_MODE_OTG;
    917	else if (ci->roles[CI_ROLE_HOST])
    918		return USB_DR_MODE_HOST;
    919	else if (ci->roles[CI_ROLE_GADGET])
    920		return USB_DR_MODE_PERIPHERAL;
    921	else
    922		return USB_DR_MODE_UNKNOWN;
    923}
    924EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
    925
    926static inline void ci_role_destroy(struct ci_hdrc *ci)
    927{
    928	ci_hdrc_gadget_destroy(ci);
    929	ci_hdrc_host_destroy(ci);
    930	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
    931		ci_hdrc_otg_destroy(ci);
    932}
    933
    934static void ci_get_otg_capable(struct ci_hdrc *ci)
    935{
    936	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
    937		ci->is_otg = false;
    938	else
    939		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
    940				DCCPARAMS_DC | DCCPARAMS_HC)
    941					== (DCCPARAMS_DC | DCCPARAMS_HC));
    942	if (ci->is_otg) {
    943		dev_dbg(ci->dev, "It is OTG capable controller\n");
    944		/* Disable and clear all OTG irq */
    945		hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
    946							OTGSC_INT_STATUS_BITS);
    947	}
    948}
    949
    950static ssize_t role_show(struct device *dev, struct device_attribute *attr,
    951			  char *buf)
    952{
    953	struct ci_hdrc *ci = dev_get_drvdata(dev);
    954
    955	if (ci->role != CI_ROLE_END)
    956		return sprintf(buf, "%s\n", ci_role(ci)->name);
    957
    958	return 0;
    959}
    960
    961static ssize_t role_store(struct device *dev,
    962		struct device_attribute *attr, const char *buf, size_t n)
    963{
    964	struct ci_hdrc *ci = dev_get_drvdata(dev);
    965	enum ci_role role;
    966	int ret;
    967
    968	if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
    969		dev_warn(dev, "Current configuration is not dual-role, quit\n");
    970		return -EPERM;
    971	}
    972
    973	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
    974		if (!strncmp(buf, ci->roles[role]->name,
    975			     strlen(ci->roles[role]->name)))
    976			break;
    977
    978	if (role == CI_ROLE_END || role == ci->role)
    979		return -EINVAL;
    980
    981	pm_runtime_get_sync(dev);
    982	disable_irq(ci->irq);
    983	ci_role_stop(ci);
    984	ret = ci_role_start(ci, role);
    985	if (!ret && ci->role == CI_ROLE_GADGET)
    986		ci_handle_vbus_change(ci);
    987	enable_irq(ci->irq);
    988	pm_runtime_put_sync(dev);
    989
    990	return (ret == 0) ? n : ret;
    991}
    992static DEVICE_ATTR_RW(role);
    993
    994static struct attribute *ci_attrs[] = {
    995	&dev_attr_role.attr,
    996	NULL,
    997};
    998ATTRIBUTE_GROUPS(ci);
    999
   1000static int ci_hdrc_probe(struct platform_device *pdev)
   1001{
   1002	struct device	*dev = &pdev->dev;
   1003	struct ci_hdrc	*ci;
   1004	struct resource	*res;
   1005	void __iomem	*base;
   1006	int		ret;
   1007	enum usb_dr_mode dr_mode;
   1008
   1009	if (!dev_get_platdata(dev)) {
   1010		dev_err(dev, "platform data missing\n");
   1011		return -ENODEV;
   1012	}
   1013
   1014	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   1015	base = devm_ioremap_resource(dev, res);
   1016	if (IS_ERR(base))
   1017		return PTR_ERR(base);
   1018
   1019	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
   1020	if (!ci)
   1021		return -ENOMEM;
   1022
   1023	spin_lock_init(&ci->lock);
   1024	ci->dev = dev;
   1025	ci->platdata = dev_get_platdata(dev);
   1026	ci->imx28_write_fix = !!(ci->platdata->flags &
   1027		CI_HDRC_IMX28_WRITE_FIX);
   1028	ci->supports_runtime_pm = !!(ci->platdata->flags &
   1029		CI_HDRC_SUPPORTS_RUNTIME_PM);
   1030	platform_set_drvdata(pdev, ci);
   1031
   1032	ret = hw_device_init(ci, base);
   1033	if (ret < 0) {
   1034		dev_err(dev, "can't initialize hardware\n");
   1035		return -ENODEV;
   1036	}
   1037
   1038	ret = ci_ulpi_init(ci);
   1039	if (ret)
   1040		return ret;
   1041
   1042	if (ci->platdata->phy) {
   1043		ci->phy = ci->platdata->phy;
   1044	} else if (ci->platdata->usb_phy) {
   1045		ci->usb_phy = ci->platdata->usb_phy;
   1046	} else {
   1047		/* Look for a generic PHY first */
   1048		ci->phy = devm_phy_get(dev->parent, "usb-phy");
   1049
   1050		if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
   1051			ret = -EPROBE_DEFER;
   1052			goto ulpi_exit;
   1053		} else if (IS_ERR(ci->phy)) {
   1054			ci->phy = NULL;
   1055		}
   1056
   1057		/* Look for a legacy USB PHY from device-tree next */
   1058		if (!ci->phy) {
   1059			ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
   1060								  "phys", 0);
   1061
   1062			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
   1063				ret = -EPROBE_DEFER;
   1064				goto ulpi_exit;
   1065			} else if (IS_ERR(ci->usb_phy)) {
   1066				ci->usb_phy = NULL;
   1067			}
   1068		}
   1069
   1070		/* Look for any registered legacy USB PHY as last resort */
   1071		if (!ci->phy && !ci->usb_phy) {
   1072			ci->usb_phy = devm_usb_get_phy(dev->parent,
   1073						       USB_PHY_TYPE_USB2);
   1074
   1075			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
   1076				ret = -EPROBE_DEFER;
   1077				goto ulpi_exit;
   1078			} else if (IS_ERR(ci->usb_phy)) {
   1079				ci->usb_phy = NULL;
   1080			}
   1081		}
   1082
   1083		/* No USB PHY was found in the end */
   1084		if (!ci->phy && !ci->usb_phy) {
   1085			ret = -ENXIO;
   1086			goto ulpi_exit;
   1087		}
   1088	}
   1089
   1090	ret = ci_usb_phy_init(ci);
   1091	if (ret) {
   1092		dev_err(dev, "unable to init phy: %d\n", ret);
   1093		return ret;
   1094	}
   1095
   1096	ci->hw_bank.phys = res->start;
   1097
   1098	ci->irq = platform_get_irq(pdev, 0);
   1099	if (ci->irq < 0) {
   1100		ret = ci->irq;
   1101		goto deinit_phy;
   1102	}
   1103
   1104	ci_get_otg_capable(ci);
   1105
   1106	dr_mode = ci->platdata->dr_mode;
   1107	/* initialize role(s) before the interrupt is requested */
   1108	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
   1109		ret = ci_hdrc_host_init(ci);
   1110		if (ret) {
   1111			if (ret == -ENXIO)
   1112				dev_info(dev, "doesn't support host\n");
   1113			else
   1114				goto deinit_phy;
   1115		}
   1116	}
   1117
   1118	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
   1119		ret = ci_hdrc_gadget_init(ci);
   1120		if (ret) {
   1121			if (ret == -ENXIO)
   1122				dev_info(dev, "doesn't support gadget\n");
   1123			else
   1124				goto deinit_host;
   1125		}
   1126	}
   1127
   1128	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
   1129		dev_err(dev, "no supported roles\n");
   1130		ret = -ENODEV;
   1131		goto deinit_gadget;
   1132	}
   1133
   1134	if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
   1135		ret = ci_hdrc_otg_init(ci);
   1136		if (ret) {
   1137			dev_err(dev, "init otg fails, ret = %d\n", ret);
   1138			goto deinit_gadget;
   1139		}
   1140	}
   1141
   1142	if (ci_role_switch.fwnode) {
   1143		ci_role_switch.driver_data = ci;
   1144		ci->role_switch = usb_role_switch_register(dev,
   1145					&ci_role_switch);
   1146		if (IS_ERR(ci->role_switch)) {
   1147			ret = PTR_ERR(ci->role_switch);
   1148			goto deinit_otg;
   1149		}
   1150	}
   1151
   1152	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
   1153		if (ci->is_otg) {
   1154			ci->role = ci_otg_role(ci);
   1155			/* Enable ID change irq */
   1156			hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
   1157		} else {
   1158			/*
   1159			 * If the controller is not OTG capable, but support
   1160			 * role switch, the defalt role is gadget, and the
   1161			 * user can switch it through debugfs.
   1162			 */
   1163			ci->role = CI_ROLE_GADGET;
   1164		}
   1165	} else {
   1166		ci->role = ci->roles[CI_ROLE_HOST]
   1167			? CI_ROLE_HOST
   1168			: CI_ROLE_GADGET;
   1169	}
   1170
   1171	if (!ci_otg_is_fsm_mode(ci)) {
   1172		/* only update vbus status for peripheral */
   1173		if (ci->role == CI_ROLE_GADGET) {
   1174			/* Pull down DP for possible charger detection */
   1175			hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
   1176			ci_handle_vbus_change(ci);
   1177		}
   1178
   1179		ret = ci_role_start(ci, ci->role);
   1180		if (ret) {
   1181			dev_err(dev, "can't start %s role\n",
   1182						ci_role(ci)->name);
   1183			goto stop;
   1184		}
   1185	}
   1186
   1187	ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
   1188			ci->platdata->name, ci);
   1189	if (ret)
   1190		goto stop;
   1191
   1192	ret = ci_extcon_register(ci);
   1193	if (ret)
   1194		goto stop;
   1195
   1196	if (ci->supports_runtime_pm) {
   1197		pm_runtime_set_active(&pdev->dev);
   1198		pm_runtime_enable(&pdev->dev);
   1199		pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
   1200		pm_runtime_mark_last_busy(ci->dev);
   1201		pm_runtime_use_autosuspend(&pdev->dev);
   1202	}
   1203
   1204	if (ci_otg_is_fsm_mode(ci))
   1205		ci_hdrc_otg_fsm_start(ci);
   1206
   1207	device_set_wakeup_capable(&pdev->dev, true);
   1208	dbg_create_files(ci);
   1209
   1210	return 0;
   1211
   1212stop:
   1213	if (ci->role_switch)
   1214		usb_role_switch_unregister(ci->role_switch);
   1215deinit_otg:
   1216	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
   1217		ci_hdrc_otg_destroy(ci);
   1218deinit_gadget:
   1219	ci_hdrc_gadget_destroy(ci);
   1220deinit_host:
   1221	ci_hdrc_host_destroy(ci);
   1222deinit_phy:
   1223	ci_usb_phy_exit(ci);
   1224ulpi_exit:
   1225	ci_ulpi_exit(ci);
   1226
   1227	return ret;
   1228}
   1229
   1230static int ci_hdrc_remove(struct platform_device *pdev)
   1231{
   1232	struct ci_hdrc *ci = platform_get_drvdata(pdev);
   1233
   1234	if (ci->role_switch)
   1235		usb_role_switch_unregister(ci->role_switch);
   1236
   1237	if (ci->supports_runtime_pm) {
   1238		pm_runtime_get_sync(&pdev->dev);
   1239		pm_runtime_disable(&pdev->dev);
   1240		pm_runtime_put_noidle(&pdev->dev);
   1241	}
   1242
   1243	dbg_remove_files(ci);
   1244	ci_role_destroy(ci);
   1245	ci_hdrc_enter_lpm(ci, true);
   1246	ci_usb_phy_exit(ci);
   1247	ci_ulpi_exit(ci);
   1248
   1249	return 0;
   1250}
   1251
   1252#ifdef CONFIG_PM
   1253/* Prepare wakeup by SRP before suspend */
   1254static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
   1255{
   1256	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
   1257				!hw_read_otgsc(ci, OTGSC_ID)) {
   1258		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
   1259								PORTSC_PP);
   1260		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
   1261								PORTSC_WKCN);
   1262	}
   1263}
   1264
   1265/* Handle SRP when wakeup by data pulse */
   1266static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
   1267{
   1268	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
   1269		(ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
   1270		if (!hw_read_otgsc(ci, OTGSC_ID)) {
   1271			ci->fsm.a_srp_det = 1;
   1272			ci->fsm.a_bus_drop = 0;
   1273		} else {
   1274			ci->fsm.id = 1;
   1275		}
   1276		ci_otg_queue_work(ci);
   1277	}
   1278}
   1279
   1280static void ci_controller_suspend(struct ci_hdrc *ci)
   1281{
   1282	disable_irq(ci->irq);
   1283	ci_hdrc_enter_lpm(ci, true);
   1284	if (ci->platdata->phy_clkgate_delay_us)
   1285		usleep_range(ci->platdata->phy_clkgate_delay_us,
   1286			     ci->platdata->phy_clkgate_delay_us + 50);
   1287	usb_phy_set_suspend(ci->usb_phy, 1);
   1288	ci->in_lpm = true;
   1289	enable_irq(ci->irq);
   1290}
   1291
   1292/*
   1293 * Handle the wakeup interrupt triggered by extcon connector
   1294 * We need to call ci_irq again for extcon since the first
   1295 * interrupt (wakeup int) only let the controller be out of
   1296 * low power mode, but not handle any interrupts.
   1297 */
   1298static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
   1299{
   1300	struct ci_hdrc_cable *cable_id, *cable_vbus;
   1301	u32 otgsc = hw_read_otgsc(ci, ~0);
   1302
   1303	cable_id = &ci->platdata->id_extcon;
   1304	cable_vbus = &ci->platdata->vbus_extcon;
   1305
   1306	if (!IS_ERR(cable_id->edev) && ci->is_otg &&
   1307		(otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
   1308		ci_irq(ci);
   1309
   1310	if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
   1311		(otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
   1312		ci_irq(ci);
   1313}
   1314
   1315static int ci_controller_resume(struct device *dev)
   1316{
   1317	struct ci_hdrc *ci = dev_get_drvdata(dev);
   1318	int ret;
   1319
   1320	dev_dbg(dev, "at %s\n", __func__);
   1321
   1322	if (!ci->in_lpm) {
   1323		WARN_ON(1);
   1324		return 0;
   1325	}
   1326
   1327	ci_hdrc_enter_lpm(ci, false);
   1328
   1329	ret = ci_ulpi_resume(ci);
   1330	if (ret)
   1331		return ret;
   1332
   1333	if (ci->usb_phy) {
   1334		usb_phy_set_suspend(ci->usb_phy, 0);
   1335		usb_phy_set_wakeup(ci->usb_phy, false);
   1336		hw_wait_phy_stable();
   1337	}
   1338
   1339	ci->in_lpm = false;
   1340	if (ci->wakeup_int) {
   1341		ci->wakeup_int = false;
   1342		pm_runtime_mark_last_busy(ci->dev);
   1343		pm_runtime_put_autosuspend(ci->dev);
   1344		enable_irq(ci->irq);
   1345		if (ci_otg_is_fsm_mode(ci))
   1346			ci_otg_fsm_wakeup_by_srp(ci);
   1347		ci_extcon_wakeup_int(ci);
   1348	}
   1349
   1350	return 0;
   1351}
   1352
   1353#ifdef CONFIG_PM_SLEEP
   1354static int ci_suspend(struct device *dev)
   1355{
   1356	struct ci_hdrc *ci = dev_get_drvdata(dev);
   1357
   1358	if (ci->wq)
   1359		flush_workqueue(ci->wq);
   1360	/*
   1361	 * Controller needs to be active during suspend, otherwise the core
   1362	 * may run resume when the parent is at suspend if other driver's
   1363	 * suspend fails, it occurs before parent's suspend has not started,
   1364	 * but the core suspend has finished.
   1365	 */
   1366	if (ci->in_lpm)
   1367		pm_runtime_resume(dev);
   1368
   1369	if (ci->in_lpm) {
   1370		WARN_ON(1);
   1371		return 0;
   1372	}
   1373
   1374	if (device_may_wakeup(dev)) {
   1375		if (ci_otg_is_fsm_mode(ci))
   1376			ci_otg_fsm_suspend_for_srp(ci);
   1377
   1378		usb_phy_set_wakeup(ci->usb_phy, true);
   1379		enable_irq_wake(ci->irq);
   1380	}
   1381
   1382	ci_controller_suspend(ci);
   1383
   1384	return 0;
   1385}
   1386
   1387static int ci_resume(struct device *dev)
   1388{
   1389	struct ci_hdrc *ci = dev_get_drvdata(dev);
   1390	int ret;
   1391
   1392	if (device_may_wakeup(dev))
   1393		disable_irq_wake(ci->irq);
   1394
   1395	ret = ci_controller_resume(dev);
   1396	if (ret)
   1397		return ret;
   1398
   1399	if (ci->supports_runtime_pm) {
   1400		pm_runtime_disable(dev);
   1401		pm_runtime_set_active(dev);
   1402		pm_runtime_enable(dev);
   1403	}
   1404
   1405	return ret;
   1406}
   1407#endif /* CONFIG_PM_SLEEP */
   1408
   1409static int ci_runtime_suspend(struct device *dev)
   1410{
   1411	struct ci_hdrc *ci = dev_get_drvdata(dev);
   1412
   1413	dev_dbg(dev, "at %s\n", __func__);
   1414
   1415	if (ci->in_lpm) {
   1416		WARN_ON(1);
   1417		return 0;
   1418	}
   1419
   1420	if (ci_otg_is_fsm_mode(ci))
   1421		ci_otg_fsm_suspend_for_srp(ci);
   1422
   1423	usb_phy_set_wakeup(ci->usb_phy, true);
   1424	ci_controller_suspend(ci);
   1425
   1426	return 0;
   1427}
   1428
   1429static int ci_runtime_resume(struct device *dev)
   1430{
   1431	return ci_controller_resume(dev);
   1432}
   1433
   1434#endif /* CONFIG_PM */
   1435static const struct dev_pm_ops ci_pm_ops = {
   1436	SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
   1437	SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
   1438};
   1439
   1440static struct platform_driver ci_hdrc_driver = {
   1441	.probe	= ci_hdrc_probe,
   1442	.remove	= ci_hdrc_remove,
   1443	.driver	= {
   1444		.name	= "ci_hdrc",
   1445		.pm	= &ci_pm_ops,
   1446		.dev_groups = ci_groups,
   1447	},
   1448};
   1449
   1450static int __init ci_hdrc_platform_register(void)
   1451{
   1452	ci_hdrc_host_driver_init();
   1453	return platform_driver_register(&ci_hdrc_driver);
   1454}
   1455module_init(ci_hdrc_platform_register);
   1456
   1457static void __exit ci_hdrc_platform_unregister(void)
   1458{
   1459	platform_driver_unregister(&ci_hdrc_driver);
   1460}
   1461module_exit(ci_hdrc_platform_unregister);
   1462
   1463MODULE_ALIAS("platform:ci_hdrc");
   1464MODULE_LICENSE("GPL v2");
   1465MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
   1466MODULE_DESCRIPTION("ChipIdea HDRC Driver");