cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

Kconfig (3266B)


      1# SPDX-License-Identifier: GPL-2.0
      2
      3config USB_DWC2
      4	tristate "DesignWare USB2 DRD Core Support"
      5	depends on HAS_DMA
      6	depends on USB || USB_GADGET
      7	depends on HAS_IOMEM
      8	select USB_ROLE_SWITCH
      9	help
     10	  Say Y here if your system has a Dual Role Hi-Speed USB
     11	  controller based on the DesignWare HSOTG IP Core.
     12
     13	  For host mode, if you choose to build the driver as dynamically
     14	  linked modules, the core module will be called dwc2.ko, the PCI
     15	  bus interface module (if you have a PCI bus system) will be
     16	  called dwc2_pci.ko, and the platform interface module (for
     17	  controllers directly connected to the CPU) will be called
     18	  dwc2_platform.ko. For all modes(host, gadget and dual-role), there
     19	  will be an additional module named dwc2.ko.
     20
     21if USB_DWC2
     22
     23choice
     24	bool "DWC2 Mode Selection"
     25	default USB_DWC2_DUAL_ROLE if (USB && USB_GADGET)
     26	default USB_DWC2_HOST if (USB && !USB_GADGET)
     27	default USB_DWC2_PERIPHERAL if (!USB && USB_GADGET)
     28
     29config USB_DWC2_HOST
     30	bool "Host only mode"
     31	depends on USB=y || (USB_DWC2=m && USB)
     32	help
     33	  The Designware USB2.0 high-speed host controller
     34	  integrated into many SoCs. Select this option if you want the
     35	  driver to operate in Host-only mode.
     36
     37comment "Gadget/Dual-role mode requires USB Gadget support to be enabled"
     38
     39config USB_DWC2_PERIPHERAL
     40	bool "Gadget only mode"
     41	depends on USB_GADGET=y || USB_GADGET=USB_DWC2
     42	help
     43	  The Designware USB2.0 high-speed gadget controller
     44	  integrated into many SoCs. Select this option if you want the
     45	  driver to operate in Peripheral-only mode. This option requires
     46	  USB_GADGET to be enabled.
     47
     48config USB_DWC2_DUAL_ROLE
     49	bool "Dual Role mode"
     50	depends on (USB=y && USB_GADGET=y) || (USB_DWC2=m && USB && USB_GADGET)
     51	help
     52	  Select this option if you want the driver to work in a dual-role
     53	  mode. In this mode both host and gadget features are enabled, and
     54	  the role will be determined by the cable that gets plugged-in. This
     55	  option requires USB_GADGET to be enabled.
     56endchoice
     57
     58config USB_DWC2_PCI
     59	tristate "DWC2 PCI"
     60	depends on USB_PCI
     61	depends on USB_GADGET || !USB_GADGET
     62	select NOP_USB_XCEIV
     63	help
     64	  The Designware USB2.0 PCI interface module for controllers
     65	  connected to a PCI bus.
     66
     67config USB_DWC2_DEBUG
     68	bool "Enable Debugging Messages"
     69	help
     70	  Say Y here to enable debugging messages in the DWC2 Driver.
     71
     72config USB_DWC2_VERBOSE
     73	bool "Enable Verbose Debugging Messages"
     74	depends on USB_DWC2_DEBUG
     75	help
     76	  Say Y here to enable verbose debugging messages in the DWC2 Driver.
     77	  WARNING: Enabling this will quickly fill your message log.
     78	  If in doubt, say N.
     79
     80config USB_DWC2_TRACK_MISSED_SOFS
     81	bool "Enable Missed SOF Tracking"
     82	help
     83	  Say Y here to enable logging of missed SOF events to the dmesg log.
     84	  WARNING: This feature is still experimental.
     85	  If in doubt, say N.
     86
     87config USB_DWC2_DEBUG_PERIODIC
     88	bool "Enable Debugging Messages For Periodic Transfers"
     89	depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE
     90	default y
     91	help
     92	  Say N here to disable (verbose) debugging messages to be
     93	  logged for periodic transfers. This allows better debugging of
     94	  non-periodic transfers, but of course the debug logs will be
     95	  incomplete. Note that this also disables some debug messages
     96	  for which the transfer type cannot be deduced.
     97endif