cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xhci-ext-caps.c (2601B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * XHCI extended capability handling
      4 *
      5 * Copyright (c) 2017 Hans de Goede <hdegoede@redhat.com>
      6 */
      7
      8#include <linux/platform_device.h>
      9#include <linux/property.h>
     10#include <linux/pci.h>
     11#include "xhci.h"
     12
     13#define USB_SW_DRV_NAME		"intel_xhci_usb_sw"
     14#define USB_SW_RESOURCE_SIZE	0x400
     15
     16#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI	0x22b5
     17
     18static const struct property_entry role_switch_props[] = {
     19	PROPERTY_ENTRY_BOOL("sw_switch_disable"),
     20	{},
     21};
     22
     23static void xhci_intel_unregister_pdev(void *arg)
     24{
     25	platform_device_unregister(arg);
     26}
     27
     28static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset)
     29{
     30	struct usb_hcd *hcd = xhci_to_hcd(xhci);
     31	struct device *dev = hcd->self.controller;
     32	struct platform_device *pdev;
     33	struct pci_dev *pci = to_pci_dev(dev);
     34	struct resource	res = { 0, };
     35	int ret;
     36
     37	pdev = platform_device_alloc(USB_SW_DRV_NAME, PLATFORM_DEVID_NONE);
     38	if (!pdev) {
     39		xhci_err(xhci, "couldn't allocate %s platform device\n",
     40			 USB_SW_DRV_NAME);
     41		return -ENOMEM;
     42	}
     43
     44	res.start = hcd->rsrc_start + cap_offset;
     45	res.end	  = res.start + USB_SW_RESOURCE_SIZE - 1;
     46	res.name  = USB_SW_DRV_NAME;
     47	res.flags = IORESOURCE_MEM;
     48
     49	ret = platform_device_add_resources(pdev, &res, 1);
     50	if (ret) {
     51		dev_err(dev, "couldn't add resources to intel_xhci_usb_sw pdev\n");
     52		platform_device_put(pdev);
     53		return ret;
     54	}
     55
     56	if (pci->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
     57		ret = device_create_managed_software_node(&pdev->dev, role_switch_props,
     58							  NULL);
     59		if (ret) {
     60			dev_err(dev, "failed to register device properties\n");
     61			platform_device_put(pdev);
     62			return ret;
     63		}
     64	}
     65
     66	pdev->dev.parent = dev;
     67
     68	ret = platform_device_add(pdev);
     69	if (ret) {
     70		dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n");
     71		platform_device_put(pdev);
     72		return ret;
     73	}
     74
     75	ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev);
     76	if (ret) {
     77		dev_err(dev, "couldn't add unregister action for intel_xhci_usb_sw pdev\n");
     78		return ret;
     79	}
     80
     81	return 0;
     82}
     83
     84int xhci_ext_cap_init(struct xhci_hcd *xhci)
     85{
     86	void __iomem *base = &xhci->cap_regs->hc_capbase;
     87	u32 offset, val;
     88	int ret;
     89
     90	offset = xhci_find_next_ext_cap(base, 0, 0);
     91
     92	while (offset) {
     93		val = readl(base + offset);
     94
     95		switch (XHCI_EXT_CAPS_ID(val)) {
     96		case XHCI_EXT_CAPS_VENDOR_INTEL:
     97			if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) {
     98				ret = xhci_create_intel_xhci_sw_pdev(xhci,
     99								     offset);
    100				if (ret)
    101					return ret;
    102			}
    103			break;
    104		}
    105		offset = xhci_find_next_ext_cap(base, offset, 0);
    106	}
    107
    108	return 0;
    109}
    110EXPORT_SYMBOL_GPL(xhci_ext_cap_init);