cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tps6598x.h (9099B)


      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Driver for TI TPS6598x USB Power Delivery controller family
      4 *
      5 * Copyright (C) 2017, Intel Corporation
      6 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
      7 */
      8
      9#include <linux/bits.h>
     10#include <linux/bitfield.h>
     11
     12#ifndef __TPS6598X_H__
     13#define __TPS6598X_H__
     14
     15#define TPS_FIELD_GET(_mask, _reg) ((typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)))
     16
     17/* TPS_REG_STATUS bits */
     18#define TPS_STATUS_PLUG_PRESENT		BIT(0)
     19#define TPS_STATUS_PLUG_UPSIDE_DOWN	BIT(4)
     20#define TPS_STATUS_TO_UPSIDE_DOWN(s)	(!!((s) & TPS_STATUS_PLUG_UPSIDE_DOWN))
     21#define TPS_STATUS_PORTROLE		BIT(5)
     22#define TPS_STATUS_TO_TYPEC_PORTROLE(s) (!!((s) & TPS_STATUS_PORTROLE))
     23#define TPS_STATUS_DATAROLE		BIT(6)
     24#define TPS_STATUS_TO_TYPEC_DATAROLE(s)	(!!((s) & TPS_STATUS_DATAROLE))
     25#define TPS_STATUS_VCONN		BIT(7)
     26#define TPS_STATUS_TO_TYPEC_VCONN(s)	(!!((s) & TPS_STATUS_VCONN))
     27#define TPS_STATUS_OVERCURRENT		BIT(16)
     28#define TPS_STATUS_GOTO_MIN_ACTIVE	BIT(26)
     29#define TPS_STATUS_BIST			BIT(27)
     30#define TPS_STATUS_HIGH_VOLAGE_WARNING	BIT(28)
     31#define TPS_STATUS_HIGH_LOW_VOLTAGE_WARNING BIT(29)
     32
     33#define TPS_STATUS_CONN_STATE_MASK		GENMASK(3, 1)
     34#define TPS_STATUS_CONN_STATE(x)		TPS_FIELD_GET(TPS_STATUS_CONN_STATE_MASK, (x))
     35#define TPS_STATUS_PP_5V0_SWITCH_MASK		GENMASK(9, 8)
     36#define TPS_STATUS_PP_5V0_SWITCH(x)		TPS_FIELD_GET(TPS_STATUS_PP_5V0_SWITCH_MASK, (x))
     37#define TPS_STATUS_PP_HV_SWITCH_MASK		GENMASK(11, 10)
     38#define TPS_STATUS_PP_HV_SWITCH(x)		TPS_FIELD_GET(TPS_STATUS_PP_HV_SWITCH_MASK, (x))
     39#define TPS_STATUS_PP_EXT_SWITCH_MASK		GENMASK(13, 12)
     40#define TPS_STATUS_PP_EXT_SWITCH(x)		TPS_FIELD_GET(TPS_STATUS_PP_EXT_SWITCH_MASK, (x))
     41#define TPS_STATUS_PP_CABLE_SWITCH_MASK		GENMASK(15, 14)
     42#define TPS_STATUS_PP_CABLE_SWITCH(x)		TPS_FIELD_GET(TPS_STATUS_PP_CABLE_SWITCH_MASK, (x))
     43#define TPS_STATUS_POWER_SOURCE_MASK		GENMASK(19, 18)
     44#define TPS_STATUS_POWER_SOURCE(x)		TPS_FIELD_GET(TPS_STATUS_POWER_SOURCE_MASK, (x))
     45#define TPS_STATUS_VBUS_STATUS_MASK		GENMASK(21, 20)
     46#define TPS_STATUS_VBUS_STATUS(x)		TPS_FIELD_GET(TPS_STATUS_VBUS_STATUS_MASK, (x))
     47#define TPS_STATUS_USB_HOST_PRESENT_MASK	GENMASK(23, 22)
     48#define TPS_STATUS_USB_HOST_PRESENT(x)		TPS_FIELD_GET(TPS_STATUS_USB_HOST_PRESENT_MASK, (x))
     49#define TPS_STATUS_LEGACY_MASK			GENMASK(25, 24)
     50#define TPS_STATUS_LEGACY(x)			TPS_FIELD_GET(TPS_STATUS_LEGACY_MASK, (x))
     51
     52#define TPS_STATUS_CONN_STATE_NO_CONN		0
     53#define TPS_STATUS_CONN_STATE_DISABLED		1
     54#define TPS_STATUS_CONN_STATE_AUDIO_CONN	2
     55#define TPS_STATUS_CONN_STATE_DEBUG_CONN	3
     56#define TPS_STATUS_CONN_STATE_NO_CONN_R_A	4
     57#define TPS_STATUS_CONN_STATE_RESERVED		5
     58#define TPS_STATUS_CONN_STATE_CONN_NO_R_A	6
     59#define TPS_STATUS_CONN_STATE_CONN_WITH_R_A	7
     60
     61#define TPS_STATUS_PP_SWITCH_STATE_DISABLED	0
     62#define TPS_STATUS_PP_SWITCH_STATE_FAULT	1
     63#define TPS_STATUS_PP_SWITCH_STATE_OUT		2
     64#define TPS_STATUS_PP_SWITCH_STATE_IN		3
     65
     66#define TPS_STATUS_POWER_SOURCE_UNKNOWN		0
     67#define TPS_STATUS_POWER_SOURCE_VIN_3P3		1
     68#define TPS_STATUS_POWER_SOURCE_DEAD_BAT	2
     69#define TPS_STATUS_POWER_SOURCE_VBUS		3
     70
     71#define TPS_STATUS_VBUS_STATUS_VSAFE0V		0
     72#define TPS_STATUS_VBUS_STATUS_VSAFE5V		1
     73#define TPS_STATUS_VBUS_STATUS_PD		2
     74#define TPS_STATUS_VBUS_STATUS_FAULT		3
     75
     76#define TPS_STATUS_USB_HOST_PRESENT_NO		0
     77#define TPS_STATUS_USB_HOST_PRESENT_PD_NO_USB	1
     78#define TPS_STATUS_USB_HOST_PRESENT_NO_PD	2
     79#define TPS_STATUS_USB_HOST_PRESENT_PD_USB	3
     80
     81#define TPS_STATUS_LEGACY_NO			0
     82#define TPS_STATUS_LEGACY_SINK			1
     83#define TPS_STATUS_LEGACY_SOURCE		2
     84
     85/* TPS_REG_INT_* bits */
     86#define TPS_REG_INT_USER_VID_ALT_MODE_OTHER_VDM		BIT_ULL(27+32)
     87#define TPS_REG_INT_USER_VID_ALT_MODE_ATTN_VDM		BIT_ULL(26+32)
     88#define TPS_REG_INT_USER_VID_ALT_MODE_EXIT		BIT_ULL(25+32)
     89#define TPS_REG_INT_USER_VID_ALT_MODE_ENTERED		BIT_ULL(24+32)
     90#define TPS_REG_INT_EXIT_MODES_COMPLETE			BIT_ULL(20+32)
     91#define TPS_REG_INT_DISCOVER_MODES_COMPLETE		BIT_ULL(19+32)
     92#define TPS_REG_INT_VDM_MSG_SENT			BIT_ULL(18+32)
     93#define TPS_REG_INT_VDM_ENTERED_MODE			BIT_ULL(17+32)
     94#define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE		BIT_ULL(14+32)
     95#define TPS_REG_INT_SRC_TRANSITION			BIT_ULL(10+32)
     96#define TPS_REG_INT_ERROR_DISCHARGE_FAILED		BIT_ULL(9+32)
     97#define TPS_REG_INT_ERROR_MESSAGE_DATA			BIT_ULL(7+32)
     98#define TPS_REG_INT_ERROR_PROTOCOL_ERROR		BIT_ULL(6+32)
     99#define TPS_REG_INT_ERROR_MISSING_GET_CAP_MESSAGE	BIT_ULL(4+32)
    100#define TPS_REG_INT_ERROR_POWER_EVENT_OCCURRED		BIT_ULL(3+32)
    101#define TPS_REG_INT_ERROR_CAN_PROVIDE_PWR_LATER		BIT_ULL(2+32)
    102#define TPS_REG_INT_ERROR_CANNOT_PROVIDE_PWR		BIT_ULL(1+32)
    103#define TPS_REG_INT_ERROR_DEVICE_INCOMPATIBLE		BIT_ULL(0+32)
    104#define TPS_REG_INT_CMD2_COMPLETE			BIT(31)
    105#define TPS_REG_INT_CMD1_COMPLETE			BIT(30)
    106#define TPS_REG_INT_ADC_HIGH_THRESHOLD			BIT(29)
    107#define TPS_REG_INT_ADC_LOW_THRESHOLD			BIT(28)
    108#define TPS_REG_INT_PD_STATUS_UPDATE			BIT(27)
    109#define TPS_REG_INT_STATUS_UPDATE			BIT(26)
    110#define TPS_REG_INT_DATA_STATUS_UPDATE			BIT(25)
    111#define TPS_REG_INT_POWER_STATUS_UPDATE			BIT(24)
    112#define TPS_REG_INT_PP_SWITCH_CHANGED			BIT(23)
    113#define TPS_REG_INT_HIGH_VOLTAGE_WARNING		BIT(22)
    114#define TPS_REG_INT_USB_HOST_PRESENT_NO_LONGER		BIT(21)
    115#define TPS_REG_INT_USB_HOST_PRESENT			BIT(20)
    116#define TPS_REG_INT_GOTO_MIN_RECEIVED			BIT(19)
    117#define TPS_REG_INT_PR_SWAP_REQUESTED			BIT(17)
    118#define TPS_REG_INT_SINK_CAP_MESSAGE_READY		BIT(15)
    119#define TPS_REG_INT_SOURCE_CAP_MESSAGE_READY		BIT(14)
    120#define TPS_REG_INT_NEW_CONTRACT_AS_PROVIDER		BIT(13)
    121#define TPS_REG_INT_NEW_CONTRACT_AS_CONSUMER		BIT(12)
    122#define TPS_REG_INT_VDM_RECEIVED			BIT(11)
    123#define TPS_REG_INT_ATTENTION_RECEIVED			BIT(10)
    124#define TPS_REG_INT_OVERCURRENT				BIT(9)
    125#define TPS_REG_INT_BIST				BIT(8)
    126#define TPS_REG_INT_RDO_RECEIVED_FROM_SINK		BIT(7)
    127#define TPS_REG_INT_DR_SWAP_COMPLETE			BIT(5)
    128#define TPS_REG_INT_PR_SWAP_COMPLETE			BIT(4)
    129#define TPS_REG_INT_PLUG_EVENT				BIT(3)
    130#define TPS_REG_INT_HARD_RESET				BIT(1)
    131#define TPS_REG_INT_PD_SOFT_RESET			BIT(0)
    132
    133/* Apple-specific TPS_REG_INT_* bits */
    134#define APPLE_CD_REG_INT_DATA_STATUS_UPDATE		BIT(10)
    135#define APPLE_CD_REG_INT_POWER_STATUS_UPDATE		BIT(9)
    136#define APPLE_CD_REG_INT_STATUS_UPDATE			BIT(8)
    137#define APPLE_CD_REG_INT_PLUG_EVENT			BIT(1)
    138
    139/* TPS_REG_SYSTEM_POWER_STATE states */
    140#define TPS_SYSTEM_POWER_STATE_S0	0x00
    141#define TPS_SYSTEM_POWER_STATE_S3	0x03
    142#define TPS_SYSTEM_POWER_STATE_S4	0x04
    143#define TPS_SYSTEM_POWER_STATE_S5	0x05
    144
    145/* TPS_REG_POWER_STATUS bits */
    146#define TPS_POWER_STATUS_CONNECTION(x)  TPS_FIELD_GET(BIT(0), (x))
    147#define TPS_POWER_STATUS_SOURCESINK(x)	TPS_FIELD_GET(BIT(1), (x))
    148#define TPS_POWER_STATUS_BC12_DET(x)	TPS_FIELD_GET(BIT(2), (x))
    149
    150#define TPS_POWER_STATUS_TYPEC_CURRENT_MASK GENMASK(3, 2)
    151#define TPS_POWER_STATUS_PWROPMODE(p)	    TPS_FIELD_GET(TPS_POWER_STATUS_TYPEC_CURRENT_MASK, (p))
    152#define TPS_POWER_STATUS_BC12_STATUS_MASK   GENMASK(6, 5)
    153#define TPS_POWER_STATUS_BC12_STATUS(p)	    TPS_FIELD_GET(TPS_POWER_STATUS_BC12_STATUS_MASK, (p))
    154
    155#define TPS_POWER_STATUS_TYPEC_CURRENT_USB     0
    156#define TPS_POWER_STATUS_TYPEC_CURRENT_1A5     1
    157#define TPS_POWER_STATUS_TYPEC_CURRENT_3A0     2
    158#define TPS_POWER_STATUS_TYPEC_CURRENT_PD      3
    159
    160#define TPS_POWER_STATUS_BC12_STATUS_SDP 0
    161#define TPS_POWER_STATUS_BC12_STATUS_CDP 2
    162#define TPS_POWER_STATUS_BC12_STATUS_DCP 3
    163
    164/* TPS_REG_DATA_STATUS bits */
    165#define TPS_DATA_STATUS_DATA_CONNECTION	     BIT(0)
    166#define TPS_DATA_STATUS_UPSIDE_DOWN	     BIT(1)
    167#define TPS_DATA_STATUS_ACTIVE_CABLE	     BIT(2)
    168#define TPS_DATA_STATUS_USB2_CONNECTION	     BIT(4)
    169#define TPS_DATA_STATUS_USB3_CONNECTION	     BIT(5)
    170#define TPS_DATA_STATUS_USB3_GEN2	     BIT(6)
    171#define TPS_DATA_STATUS_USB_DATA_ROLE	     BIT(7)
    172#define TPS_DATA_STATUS_DP_CONNECTION	     BIT(8)
    173#define TPS_DATA_STATUS_DP_SINK		     BIT(9)
    174#define TPS_DATA_STATUS_TBT_CONNECTION	     BIT(16)
    175#define TPS_DATA_STATUS_TBT_TYPE	     BIT(17)
    176#define TPS_DATA_STATUS_OPTICAL_CABLE	     BIT(18)
    177#define TPS_DATA_STATUS_ACTIVE_LINK_TRAIN    BIT(20)
    178#define TPS_DATA_STATUS_FORCE_LSX	     BIT(23)
    179#define TPS_DATA_STATUS_POWER_MISMATCH	     BIT(24)
    180
    181#define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK GENMASK(11, 10)
    182#define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT(x) \
    183	TPS_FIELD_GET(TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK, (x))
    184#define TPS_DATA_STATUS_TBT_CABLE_SPEED_MASK   GENMASK(27, 25)
    185#define TPS_DATA_STATUS_TBT_CABLE_SPEED \
    186	TPS_FIELD_GET(TPS_DATA_STATUS_TBT_CABLE_SPEED_MASK, (x))
    187#define TPS_DATA_STATUS_TBT_CABLE_GEN_MASK     GENMASK(29, 28)
    188#define TPS_DATA_STATUS_TBT_CABLE_GEN \
    189	TPS_FIELD_GET(TPS_DATA_STATUS_TBT_CABLE_GEN_MASK, (x))
    190
    191/* Map data status to DP spec assignments */
    192#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT(x) \
    193	((TPS_DATA_STATUS_DP_PIN_ASSIGNMENT(x) << 1) | \
    194		TPS_FIELD_GET(TPS_DATA_STATUS_USB3_CONNECTION, (x)))
    195#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_E    0
    196#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_F    BIT(0)
    197#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_C    BIT(1)
    198#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_D    (BIT(1) | BIT(0))
    199#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_A    BIT(2)
    200#define TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_B    (BIT(2) | BIT(1))
    201
    202#endif /* __TPS6598X_H__ */