video_cs5530.c (5587B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * drivers/video/geode/video_cs5530.c 4 * -- CS5530 video device 5 * 6 * Copyright (C) 2005 Arcom Control Systems Ltd. 7 * 8 * Based on AMD's original 2.4 driver: 9 * Copyright (C) 2004 Advanced Micro Devices, Inc. 10 */ 11#include <linux/fb.h> 12#include <linux/delay.h> 13#include <asm/io.h> 14#include <asm/delay.h> 15 16#include "geodefb.h" 17#include "video_cs5530.h" 18 19/* 20 * CS5530 PLL table. This maps pixclocks to the appropriate PLL register 21 * value. 22 */ 23struct cs5530_pll_entry { 24 long pixclock; /* ps */ 25 u32 pll_value; 26}; 27 28static const struct cs5530_pll_entry cs5530_pll_table[] = { 29 { 39721, 0x31C45801, }, /* 25.1750 MHz */ 30 { 35308, 0x20E36802, }, /* 28.3220 */ 31 { 31746, 0x33915801, }, /* 31.5000 */ 32 { 27777, 0x31EC4801, }, /* 36.0000 */ 33 { 26666, 0x21E22801, }, /* 37.5000 */ 34 { 25000, 0x33088801, }, /* 40.0000 */ 35 { 22271, 0x33E22801, }, /* 44.9000 */ 36 { 20202, 0x336C4801, }, /* 49.5000 */ 37 { 20000, 0x23088801, }, /* 50.0000 */ 38 { 19860, 0x23088801, }, /* 50.3500 */ 39 { 18518, 0x3708A801, }, /* 54.0000 */ 40 { 17777, 0x23E36802, }, /* 56.2500 */ 41 { 17733, 0x23E36802, }, /* 56.3916 */ 42 { 17653, 0x23E36802, }, /* 56.6444 */ 43 { 16949, 0x37C45801, }, /* 59.0000 */ 44 { 15873, 0x23EC4801, }, /* 63.0000 */ 45 { 15384, 0x37911801, }, /* 65.0000 */ 46 { 14814, 0x37963803, }, /* 67.5000 */ 47 { 14124, 0x37058803, }, /* 70.8000 */ 48 { 13888, 0x3710C805, }, /* 72.0000 */ 49 { 13333, 0x37E22801, }, /* 75.0000 */ 50 { 12698, 0x27915801, }, /* 78.7500 */ 51 { 12500, 0x37D8D802, }, /* 80.0000 */ 52 { 11135, 0x27588802, }, /* 89.8000 */ 53 { 10582, 0x27EC4802, }, /* 94.5000 */ 54 { 10101, 0x27AC6803, }, /* 99.0000 */ 55 { 10000, 0x27088801, }, /* 100.0000 */ 56 { 9259, 0x2710C805, }, /* 108.0000 */ 57 { 8888, 0x27E36802, }, /* 112.5000 */ 58 { 7692, 0x27C58803, }, /* 130.0000 */ 59 { 7407, 0x27316803, }, /* 135.0000 */ 60 { 6349, 0x2F915801, }, /* 157.5000 */ 61 { 6172, 0x2F08A801, }, /* 162.0000 */ 62 { 5714, 0x2FB11802, }, /* 175.0000 */ 63 { 5291, 0x2FEC4802, }, /* 189.0000 */ 64 { 4950, 0x2F963803, }, /* 202.0000 */ 65 { 4310, 0x2FB1B802, }, /* 232.0000 */ 66}; 67 68static void cs5530_set_dclk_frequency(struct fb_info *info) 69{ 70 struct geodefb_par *par = info->par; 71 int i; 72 u32 value; 73 long min, diff; 74 75 /* Search the table for the closest pixclock. */ 76 value = cs5530_pll_table[0].pll_value; 77 min = cs5530_pll_table[0].pixclock - info->var.pixclock; 78 if (min < 0) min = -min; 79 for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) { 80 diff = cs5530_pll_table[i].pixclock - info->var.pixclock; 81 if (diff < 0L) diff = -diff; 82 if (diff < min) { 83 min = diff; 84 value = cs5530_pll_table[i].pll_value; 85 } 86 } 87 88 writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG); 89 writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */ 90 udelay(500); /* wait for PLL to settle */ 91 writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */ 92 writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */ 93} 94 95static void cs5530_configure_display(struct fb_info *info) 96{ 97 struct geodefb_par *par = info->par; 98 u32 dcfg; 99 100 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); 101 102 /* Clear bits from existing mode. */ 103 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK 104 | CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL 105 | CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN 106 | CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN 107 | CS5530_DCFG_HSYNC_EN); 108 109 /* Set default sync skew and power sequence delays. */ 110 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT 111 | CS5530_DCFG_GV_PAL_BYP); 112 113 /* Enable DACs, hsync and vsync for CRTs */ 114 if (par->enable_crt) { 115 dcfg |= CS5530_DCFG_DAC_PWR_EN; 116 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; 117 } 118 /* Enable panel power and data if using a flat panel. */ 119 if (par->panel_x > 0) { 120 dcfg |= CS5530_DCFG_FP_PWR_EN; 121 dcfg |= CS5530_DCFG_FP_DATA_EN; 122 } 123 124 /* Sync polarities. */ 125 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 126 dcfg |= CS5530_DCFG_CRT_HSYNC_POL; 127 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 128 dcfg |= CS5530_DCFG_CRT_VSYNC_POL; 129 130 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); 131} 132 133static int cs5530_blank_display(struct fb_info *info, int blank_mode) 134{ 135 struct geodefb_par *par = info->par; 136 u32 dcfg; 137 int blank, hsync, vsync; 138 139 switch (blank_mode) { 140 case FB_BLANK_UNBLANK: 141 blank = 0; hsync = 1; vsync = 1; 142 break; 143 case FB_BLANK_NORMAL: 144 blank = 1; hsync = 1; vsync = 1; 145 break; 146 case FB_BLANK_VSYNC_SUSPEND: 147 blank = 1; hsync = 1; vsync = 0; 148 break; 149 case FB_BLANK_HSYNC_SUSPEND: 150 blank = 1; hsync = 0; vsync = 1; 151 break; 152 case FB_BLANK_POWERDOWN: 153 blank = 1; hsync = 0; vsync = 0; 154 break; 155 default: 156 return -EINVAL; 157 } 158 159 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); 160 161 dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN 162 | CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN 163 | CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN); 164 165 if (par->enable_crt) { 166 if (!blank) 167 dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN; 168 if (hsync) 169 dcfg |= CS5530_DCFG_HSYNC_EN; 170 if (vsync) 171 dcfg |= CS5530_DCFG_VSYNC_EN; 172 } 173 if (par->panel_x > 0) { 174 if (!blank) 175 dcfg |= CS5530_DCFG_FP_DATA_EN; 176 if (hsync && vsync) 177 dcfg |= CS5530_DCFG_FP_PWR_EN; 178 } 179 180 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); 181 182 return 0; 183} 184 185const struct geode_vid_ops cs5530_vid_ops = { 186 .set_dclk = cs5530_set_dclk_frequency, 187 .configure_display = cs5530_configure_display, 188 .blank_display = cs5530_blank_display, 189};