STG4000Reg.h (9201B)
1/* 2 * linux/drivers/video/kyro/STG4000Reg.h 3 * 4 * Copyright (C) 2002 STMicroelectronics 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 */ 10 11#ifndef _STG4000REG_H 12#define _STG4000REG_H 13 14#define DWFILL unsigned long :32 15#define WFILL unsigned short :16 16 17/* 18 * Macros that access memory mapped card registers in PCI space 19 * Add an appropriate section for your OS or processor architecture. 20 */ 21#if defined(__KERNEL__) 22#include <asm/page.h> 23#include <asm/io.h> 24#define STG_WRITE_REG(reg,data) (writel(data,&pSTGReg->reg)) 25#define STG_READ_REG(reg) (readl(&pSTGReg->reg)) 26#else 27#define STG_WRITE_REG(reg,data) (pSTGReg->reg = data) 28#define STG_READ_REG(reg) (pSTGReg->reg) 29#endif /* __KERNEL__ */ 30 31#define SET_BIT(n) (1<<(n)) 32#define CLEAR_BIT(n) (tmp &= ~(1<<n)) 33#define CLEAR_BITS_FRM_TO(frm, to) \ 34{\ 35int i; \ 36 for(i = frm; i<= to; i++) \ 37 { \ 38 tmp &= ~(1<<i); \ 39 } \ 40} 41 42#define CLEAR_BIT_2(n) (usTemp &= ~(1<<n)) 43#define CLEAR_BITS_FRM_TO_2(frm, to) \ 44{\ 45int i; \ 46 for(i = frm; i<= to; i++) \ 47 { \ 48 usTemp &= ~(1<<i); \ 49 } \ 50} 51 52/* LUT select */ 53typedef enum _LUT_USES { 54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY 55} LUT_USES; 56 57/* Primary surface pixel format select */ 58typedef enum _PIXEL_FORMAT { 59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP 60} PIXEL_FORMAT; 61 62/* Overlay blending mode select */ 63typedef enum _BLEND_MODE { 64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA, 65 CK_PIXEL_ALPHA, CK_GLOBAL_ALPHA 66} OVRL_BLEND_MODE; 67 68/* Overlay Pixel format select */ 69typedef enum _OVRL_PIX_FORMAT { 70 UYVY, VYUY, YUYV, YVYU 71} OVRL_PIX_FORMAT; 72 73/* Register Table */ 74typedef struct { 75 /* 0h */ 76 volatile u32 Thread0Enable; /* 0x0000 */ 77 volatile u32 Thread1Enable; /* 0x0004 */ 78 volatile u32 Thread0Recover; /* 0x0008 */ 79 volatile u32 Thread1Recover; /* 0x000C */ 80 volatile u32 Thread0Step; /* 0x0010 */ 81 volatile u32 Thread1Step; /* 0x0014 */ 82 volatile u32 VideoInStatus; /* 0x0018 */ 83 volatile u32 Core2InSignStart; /* 0x001C */ 84 volatile u32 Core1ResetVector; /* 0x0020 */ 85 volatile u32 Core1ROMOffset; /* 0x0024 */ 86 volatile u32 Core1ArbiterPriority; /* 0x0028 */ 87 volatile u32 VideoInControl; /* 0x002C */ 88 volatile u32 VideoInReg0CtrlA; /* 0x0030 */ 89 volatile u32 VideoInReg0CtrlB; /* 0x0034 */ 90 volatile u32 VideoInReg1CtrlA; /* 0x0038 */ 91 volatile u32 VideoInReg1CtrlB; /* 0x003C */ 92 volatile u32 Thread0Kicker; /* 0x0040 */ 93 volatile u32 Core2InputSign; /* 0x0044 */ 94 volatile u32 Thread0ProgCtr; /* 0x0048 */ 95 volatile u32 Thread1ProgCtr; /* 0x004C */ 96 volatile u32 Thread1Kicker; /* 0x0050 */ 97 volatile u32 GPRegister1; /* 0x0054 */ 98 volatile u32 GPRegister2; /* 0x0058 */ 99 volatile u32 GPRegister3; /* 0x005C */ 100 volatile u32 GPRegister4; /* 0x0060 */ 101 volatile u32 SerialIntA; /* 0x0064 */ 102 103 volatile u32 Fill0[6]; /* GAP 0x0068 - 0x007C */ 104 105 volatile u32 SoftwareReset; /* 0x0080 */ 106 volatile u32 SerialIntB; /* 0x0084 */ 107 108 volatile u32 Fill1[37]; /* GAP 0x0088 - 0x011C */ 109 110 volatile u32 ROMELQV; /* 0x011C */ 111 volatile u32 WLWH; /* 0x0120 */ 112 volatile u32 ROMELWL; /* 0x0124 */ 113 114 volatile u32 dwFill_1; /* GAP 0x0128 */ 115 116 volatile u32 IntStatus; /* 0x012C */ 117 volatile u32 IntMask; /* 0x0130 */ 118 volatile u32 IntClear; /* 0x0134 */ 119 120 volatile u32 Fill2[6]; /* GAP 0x0138 - 0x014C */ 121 122 volatile u32 ROMGPIOA; /* 0x0150 */ 123 volatile u32 ROMGPIOB; /* 0x0154 */ 124 volatile u32 ROMGPIOC; /* 0x0158 */ 125 volatile u32 ROMGPIOD; /* 0x015C */ 126 127 volatile u32 Fill3[2]; /* GAP 0x0160 - 0x0168 */ 128 129 volatile u32 AGPIntID; /* 0x0168 */ 130 volatile u32 AGPIntClassCode; /* 0x016C */ 131 volatile u32 AGPIntBIST; /* 0x0170 */ 132 volatile u32 AGPIntSSID; /* 0x0174 */ 133 volatile u32 AGPIntPMCSR; /* 0x0178 */ 134 volatile u32 VGAFrameBufBase; /* 0x017C */ 135 volatile u32 VGANotify; /* 0x0180 */ 136 volatile u32 DACPLLMode; /* 0x0184 */ 137 volatile u32 Core1VideoClockDiv; /* 0x0188 */ 138 volatile u32 AGPIntStat; /* 0x018C */ 139 140 /* 141 volatile u32 Fill4[0x0400/4 - 0x0190/4]; //GAP 0x0190 - 0x0400 142 volatile u32 Fill5[0x05FC/4 - 0x0400/4]; //GAP 0x0400 - 0x05FC Fog Table 143 volatile u32 Fill6[0x0604/4 - 0x0600/4]; //GAP 0x0600 - 0x0604 144 volatile u32 Fill7[0x0680/4 - 0x0608/4]; //GAP 0x0608 - 0x0680 145 volatile u32 Fill8[0x07FC/4 - 0x0684/4]; //GAP 0x0684 - 0x07FC 146 */ 147 volatile u32 Fill4[412]; /* 0x0190 - 0x07FC */ 148 149 volatile u32 TACtrlStreamBase; /* 0x0800 */ 150 volatile u32 TAObjDataBase; /* 0x0804 */ 151 volatile u32 TAPtrDataBase; /* 0x0808 */ 152 volatile u32 TARegionDataBase; /* 0x080C */ 153 volatile u32 TATailPtrBase; /* 0x0810 */ 154 volatile u32 TAPtrRegionSize; /* 0x0814 */ 155 volatile u32 TAConfiguration; /* 0x0818 */ 156 volatile u32 TAObjDataStartAddr; /* 0x081C */ 157 volatile u32 TAObjDataEndAddr; /* 0x0820 */ 158 volatile u32 TAXScreenClip; /* 0x0824 */ 159 volatile u32 TAYScreenClip; /* 0x0828 */ 160 volatile u32 TARHWClamp; /* 0x082C */ 161 volatile u32 TARHWCompare; /* 0x0830 */ 162 volatile u32 TAStart; /* 0x0834 */ 163 volatile u32 TAObjReStart; /* 0x0838 */ 164 volatile u32 TAPtrReStart; /* 0x083C */ 165 volatile u32 TAStatus1; /* 0x0840 */ 166 volatile u32 TAStatus2; /* 0x0844 */ 167 volatile u32 TAIntStatus; /* 0x0848 */ 168 volatile u32 TAIntMask; /* 0x084C */ 169 170 volatile u32 Fill5[235]; /* GAP 0x0850 - 0x0BF8 */ 171 172 volatile u32 TextureAddrThresh; /* 0x0BFC */ 173 volatile u32 Core1Translation; /* 0x0C00 */ 174 volatile u32 TextureAddrReMap; /* 0x0C04 */ 175 volatile u32 RenderOutAGPRemap; /* 0x0C08 */ 176 volatile u32 _3DRegionReadTrans; /* 0x0C0C */ 177 volatile u32 _3DPtrReadTrans; /* 0x0C10 */ 178 volatile u32 _3DParamReadTrans; /* 0x0C14 */ 179 volatile u32 _3DRegionReadThresh; /* 0x0C18 */ 180 volatile u32 _3DPtrReadThresh; /* 0x0C1C */ 181 volatile u32 _3DParamReadThresh; /* 0x0C20 */ 182 volatile u32 _3DRegionReadAGPRemap; /* 0x0C24 */ 183 volatile u32 _3DPtrReadAGPRemap; /* 0x0C28 */ 184 volatile u32 _3DParamReadAGPRemap; /* 0x0C2C */ 185 volatile u32 ZBufferAGPRemap; /* 0x0C30 */ 186 volatile u32 TAIndexAGPRemap; /* 0x0C34 */ 187 volatile u32 TAVertexAGPRemap; /* 0x0C38 */ 188 volatile u32 TAUVAddrTrans; /* 0x0C3C */ 189 volatile u32 TATailPtrCacheTrans; /* 0x0C40 */ 190 volatile u32 TAParamWriteTrans; /* 0x0C44 */ 191 volatile u32 TAPtrWriteTrans; /* 0x0C48 */ 192 volatile u32 TAParamWriteThresh; /* 0x0C4C */ 193 volatile u32 TAPtrWriteThresh; /* 0x0C50 */ 194 volatile u32 TATailPtrCacheAGPRe; /* 0x0C54 */ 195 volatile u32 TAParamWriteAGPRe; /* 0x0C58 */ 196 volatile u32 TAPtrWriteAGPRe; /* 0x0C5C */ 197 volatile u32 SDRAMArbiterConf; /* 0x0C60 */ 198 volatile u32 SDRAMConf0; /* 0x0C64 */ 199 volatile u32 SDRAMConf1; /* 0x0C68 */ 200 volatile u32 SDRAMConf2; /* 0x0C6C */ 201 volatile u32 SDRAMRefresh; /* 0x0C70 */ 202 volatile u32 SDRAMPowerStat; /* 0x0C74 */ 203 204 volatile u32 Fill6[2]; /* GAP 0x0C78 - 0x0C7C */ 205 206 volatile u32 RAMBistData; /* 0x0C80 */ 207 volatile u32 RAMBistCtrl; /* 0x0C84 */ 208 volatile u32 FIFOBistKey; /* 0x0C88 */ 209 volatile u32 RAMBistResult; /* 0x0C8C */ 210 volatile u32 FIFOBistResult; /* 0x0C90 */ 211 212 /* 213 volatile u32 Fill11[0x0CBC/4 - 0x0C94/4]; //GAP 0x0C94 - 0x0CBC 214 volatile u32 Fill12[0x0CD0/4 - 0x0CC0/4]; //GAP 0x0CC0 - 0x0CD0 3DRegisters 215 */ 216 217 volatile u32 Fill7[16]; /* 0x0c94 - 0x0cd0 */ 218 219 volatile u32 SDRAMAddrSign; /* 0x0CD4 */ 220 volatile u32 SDRAMDataSign; /* 0x0CD8 */ 221 volatile u32 SDRAMSignConf; /* 0x0CDC */ 222 223 /* DWFILL; //GAP 0x0CE0 */ 224 volatile u32 dwFill_2; 225 226 volatile u32 ISPSignature; /* 0x0CE4 */ 227 228 volatile u32 Fill8[454]; /*GAP 0x0CE8 - 0x13FC */ 229 230 volatile u32 DACPrimAddress; /* 0x1400 */ 231 volatile u32 DACPrimSize; /* 0x1404 */ 232 volatile u32 DACCursorAddr; /* 0x1408 */ 233 volatile u32 DACCursorCtrl; /* 0x140C */ 234 volatile u32 DACOverlayAddr; /* 0x1410 */ 235 volatile u32 DACOverlayUAddr; /* 0x1414 */ 236 volatile u32 DACOverlayVAddr; /* 0x1418 */ 237 volatile u32 DACOverlaySize; /* 0x141C */ 238 volatile u32 DACOverlayVtDec; /* 0x1420 */ 239 240 volatile u32 Fill9[9]; /* GAP 0x1424 - 0x1444 */ 241 242 volatile u32 DACVerticalScal; /* 0x1448 */ 243 volatile u32 DACPixelFormat; /* 0x144C */ 244 volatile u32 DACHorizontalScal; /* 0x1450 */ 245 volatile u32 DACVidWinStart; /* 0x1454 */ 246 volatile u32 DACVidWinEnd; /* 0x1458 */ 247 volatile u32 DACBlendCtrl; /* 0x145C */ 248 volatile u32 DACHorTim1; /* 0x1460 */ 249 volatile u32 DACHorTim2; /* 0x1464 */ 250 volatile u32 DACHorTim3; /* 0x1468 */ 251 volatile u32 DACVerTim1; /* 0x146C */ 252 volatile u32 DACVerTim2; /* 0x1470 */ 253 volatile u32 DACVerTim3; /* 0x1474 */ 254 volatile u32 DACBorderColor; /* 0x1478 */ 255 volatile u32 DACSyncCtrl; /* 0x147C */ 256 volatile u32 DACStreamCtrl; /* 0x1480 */ 257 volatile u32 DACLUTAddress; /* 0x1484 */ 258 volatile u32 DACLUTData; /* 0x1488 */ 259 volatile u32 DACBurstCtrl; /* 0x148C */ 260 volatile u32 DACCrcTrigger; /* 0x1490 */ 261 volatile u32 DACCrcDone; /* 0x1494 */ 262 volatile u32 DACCrcResult1; /* 0x1498 */ 263 volatile u32 DACCrcResult2; /* 0x149C */ 264 volatile u32 DACLinecount; /* 0x14A0 */ 265 266 volatile u32 Fill10[151]; /*GAP 0x14A4 - 0x16FC */ 267 268 volatile u32 DigVidPortCtrl; /* 0x1700 */ 269 volatile u32 DigVidPortStat; /* 0x1704 */ 270 271 /* 272 volatile u32 Fill11[0x1FFC/4 - 0x1708/4]; //GAP 0x1708 - 0x1FFC 273 volatile u32 Fill17[0x3000/4 - 0x2FFC/4]; //GAP 0x2000 - 0x2FFC ALUT 274 */ 275 276 volatile u32 Fill11[1598]; 277 278 /* DWFILL; //GAP 0x3000 ALUT 256MB offset */ 279 volatile u32 Fill_3; 280 281} STG4000REG; 282 283#endif /* _STG4000REG_H */