cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sa1100fb.h (2565B)

      1/*
      2 * linux/drivers/video/sa1100fb.h
      3 *    -- StrongARM 1100 LCD Controller Frame Buffer Device
      4 *
      5 *  Copyright (C) 1999 Eric A. Thomas
      6 *   Based on acornfb.c Copyright (C) Russell King.
      7 *  
      8 * This file is subject to the terms and conditions of the GNU General Public
      9 * License.  See the file COPYING in the main directory of this archive
     10 * for more details.
     11 */
     12
     13struct gpio_desc;
     14
     15#define LCCR0           0x0000          /* LCD Control Reg. 0 */
     16#define LCSR            0x0004          /* LCD Status Reg. */
     17#define DBAR1           0x0010          /* LCD DMA Base Address Reg. channel 1 */
     18#define DCAR1           0x0014          /* LCD DMA Current Address Reg. channel 1 */
     19#define DBAR2           0x0018          /* LCD DMA Base Address Reg.  channel 2 */
     20#define DCAR2           0x001C          /* LCD DMA Current Address Reg. channel 2 */
     21#define LCCR1           0x0020          /* LCD Control Reg. 1 */
     22#define LCCR2           0x0024          /* LCD Control Reg. 2 */
     23#define LCCR3           0x0028          /* LCD Control Reg. 3 */
     24
     25/* Shadows for LCD controller registers */
     26struct sa1100fb_lcd_reg {
     27	unsigned long lccr0;
     28	unsigned long lccr1;
     29	unsigned long lccr2;
     30	unsigned long lccr3;
     31};
     32
     33struct sa1100fb_info {
     34	struct fb_info		fb;
     35	struct device		*dev;
     36	const struct sa1100fb_rgb *rgb[NR_RGB];
     37	void __iomem		*base;
     38	struct gpio_desc	*shannon_lcden;
     39
     40	/*
     41	 * These are the addresses we mapped
     42	 * the framebuffer memory region to.
     43	 */
     44	dma_addr_t		map_dma;
     45	u_char *		map_cpu;
     46	u_int			map_size;
     47
     48	u_char *		screen_cpu;
     49	dma_addr_t		screen_dma;
     50	u16 *			palette_cpu;
     51	dma_addr_t		palette_dma;
     52	u_int			palette_size;
     53
     54	dma_addr_t		dbar1;
     55	dma_addr_t		dbar2;
     56
     57	u_int			reg_lccr0;
     58	u_int			reg_lccr1;
     59	u_int			reg_lccr2;
     60	u_int			reg_lccr3;
     61
     62	volatile u_char		state;
     63	volatile u_char		task_state;
     64	struct mutex		ctrlr_lock;
     65	wait_queue_head_t	ctrlr_wait;
     66	struct work_struct	task;
     67
     68#ifdef CONFIG_CPU_FREQ
     69	struct notifier_block	freq_transition;
     70#endif
     71
     72	const struct sa1100fb_mach_info *inf;
     73	struct clk *clk;
     74
     75	u32 pseudo_palette[16];
     76};
     77
     78#define TO_INF(ptr,member)	container_of(ptr,struct sa1100fb_info,member)
     79
     80#define SA1100_PALETTE_MODE_VAL(bpp)    (((bpp) & 0x018) << 9)
     81
     82/*
     83 * These are the actions for set_ctrlr_state
     84 */
     85#define C_DISABLE		(0)
     86#define C_ENABLE		(1)
     87#define C_DISABLE_CLKCHANGE	(2)
     88#define C_ENABLE_CLKCHANGE	(3)
     89#define C_REENABLE		(4)
     90#define C_DISABLE_PM		(5)
     91#define C_ENABLE_PM		(6)
     92#define C_STARTUP		(7)
     93
     94#define SA1100_NAME	"SA1100"
     95
     96/*
     97 * Minimum X and Y resolutions
     98 */
     99#define MIN_XRES	64
    100#define MIN_YRES	64
    101