cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tblDPASetting.c (3343B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
      4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
      5
      6 */
      7
      8#include "global.h"
      9
     10struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
     11/*  ClkRange, DVP0, DVP0DataDriving,  DVP0ClockDriving, DVP1,
     12					DVP1Driving, DFPHigh, DFPLow */
     13/*  CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
     14					SR65,        CR97,    CR99   */
     15	/* LCK/VCK < 30000000 will use this value */
     16	{DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
     17	 0x00},
     18	/* 30000000 < LCK/VCK < 50000000 will use this value */
     19	{DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
     20	 0x00},
     21	/* 50000000 < LCK/VCK < 70000000 will use this value */
     22	{DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
     23	 0x00},
     24	/* 70000000 < LCK/VCK < 100000000 will use this value */
     25	{DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
     26	 0x00},
     27	/* 100000000 < LCK/VCK < 15000000 will use this value */
     28	{DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
     29	 0x00},
     30	/* 15000000 < LCK/VCK will use this value */
     31	{DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
     32	 0x00},
     33};
     34
     35struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
     36/*  ClkRange,DVP0, DVP0DataDriving,  DVP0ClockDriving, DVP1,
     37					DVP1Driving, DFPHigh,   DFPLow */
     38/*   CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
     39					SR65,        CR97,      CR99   */
     40/* LCK/VCK < 30000000 will use this value */
     41{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
     42/* 30000000 < LCK/VCK < 50000000 will use this value */
     43{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
     44/* 50000000 < LCK/VCK < 70000000 will use this value */
     45{DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
     46/* 70000000 < LCK/VCK < 100000000 will use this value */
     47{DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
     48/* 100000000 < LCK/VCK < 15000000 will use this value */
     49{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
     50/* 15000000 < LCK/VCK will use this value */
     51{DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
     52};
     53
     54/* For VT3364: */
     55struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
     56/*  ClkRange,DVP0, DVP0DataDriving,  DVP0ClockDriving, DVP1,
     57					DVP1Driving, DFPHigh,   DFPLow */
     58/*   CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
     59					SR65,        CR97,      CR99   */
     60/* LCK/VCK < 30000000 will use this value */
     61{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
     62/* 30000000 < LCK/VCK < 50000000 will use this value */
     63{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
     64/* 50000000 < LCK/VCK < 70000000 will use this value */
     65{DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
     66/* 70000000 < LCK/VCK < 100000000 will use this value */
     67{DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
     68/* 100000000 < LCK/VCK < 15000000 will use this value */
     69{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
     70/* 15000000 < LCK/VCK will use this value */
     71{DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
     72};