cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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instrumented-lock.h (2687B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2
      3/*
      4 * This file provides wrappers with sanitizer instrumentation for bit
      5 * locking operations.
      6 *
      7 * To use this functionality, an arch's bitops.h file needs to define each of
      8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
      9 * arch___set_bit(), etc.).
     10 */
     11#ifndef _ASM_GENERIC_BITOPS_INSTRUMENTED_LOCK_H
     12#define _ASM_GENERIC_BITOPS_INSTRUMENTED_LOCK_H
     13
     14#include <linux/instrumented.h>
     15
     16/**
     17 * clear_bit_unlock - Clear a bit in memory, for unlock
     18 * @nr: the bit to set
     19 * @addr: the address to start counting from
     20 *
     21 * This operation is atomic and provides release barrier semantics.
     22 */
     23static inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
     24{
     25	kcsan_release();
     26	instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
     27	arch_clear_bit_unlock(nr, addr);
     28}
     29
     30/**
     31 * __clear_bit_unlock - Clears a bit in memory
     32 * @nr: Bit to clear
     33 * @addr: Address to start counting from
     34 *
     35 * This is a non-atomic operation but implies a release barrier before the
     36 * memory operation. It can be used for an unlock if no other CPUs can
     37 * concurrently modify other bits in the word.
     38 */
     39static inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
     40{
     41	kcsan_release();
     42	instrument_write(addr + BIT_WORD(nr), sizeof(long));
     43	arch___clear_bit_unlock(nr, addr);
     44}
     45
     46/**
     47 * test_and_set_bit_lock - Set a bit and return its old value, for lock
     48 * @nr: Bit to set
     49 * @addr: Address to count from
     50 *
     51 * This operation is atomic and provides acquire barrier semantics if
     52 * the returned value is 0.
     53 * It can be used to implement bit locks.
     54 */
     55static inline bool test_and_set_bit_lock(long nr, volatile unsigned long *addr)
     56{
     57	instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
     58	return arch_test_and_set_bit_lock(nr, addr);
     59}
     60
     61#if defined(arch_clear_bit_unlock_is_negative_byte)
     62/**
     63 * clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom
     64 *                                     byte is negative, for unlock.
     65 * @nr: the bit to clear
     66 * @addr: the address to start counting from
     67 *
     68 * This operation is atomic and provides release barrier semantics.
     69 *
     70 * This is a bit of a one-trick-pony for the filemap code, which clears
     71 * PG_locked and tests PG_waiters,
     72 */
     73static inline bool
     74clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
     75{
     76	kcsan_release();
     77	instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
     78	return arch_clear_bit_unlock_is_negative_byte(nr, addr);
     79}
     80/* Let everybody know we have it. */
     81#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte
     82#endif
     83
     84#endif /* _ASM_GENERIC_BITOPS_INSTRUMENTED_LOCK_H */