cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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alphascale,asm9260.h (2281B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
      4 */
      5
      6#ifndef _DT_BINDINGS_CLK_ASM9260_H
      7#define _DT_BINDINGS_CLK_ASM9260_H
      8
      9/* ahb gate */
     10#define CLKID_AHB_ROM		0
     11#define CLKID_AHB_RAM		1
     12#define CLKID_AHB_GPIO		2
     13#define CLKID_AHB_MAC		3
     14#define CLKID_AHB_EMI		4
     15#define CLKID_AHB_USB0		5
     16#define CLKID_AHB_USB1		6
     17#define CLKID_AHB_DMA0		7
     18#define CLKID_AHB_DMA1		8
     19#define CLKID_AHB_UART0		9
     20#define CLKID_AHB_UART1		10
     21#define CLKID_AHB_UART2		11
     22#define CLKID_AHB_UART3		12
     23#define CLKID_AHB_UART4		13
     24#define CLKID_AHB_UART5		14
     25#define CLKID_AHB_UART6		15
     26#define CLKID_AHB_UART7		16
     27#define CLKID_AHB_UART8		17
     28#define CLKID_AHB_UART9		18
     29#define CLKID_AHB_I2S0		19
     30#define CLKID_AHB_I2C0		20
     31#define CLKID_AHB_I2C1		21
     32#define CLKID_AHB_SSP0		22
     33#define CLKID_AHB_IOCONFIG	23
     34#define CLKID_AHB_WDT		24
     35#define CLKID_AHB_CAN0		25
     36#define CLKID_AHB_CAN1		26
     37#define CLKID_AHB_MPWM		27
     38#define CLKID_AHB_SPI0		28
     39#define CLKID_AHB_SPI1		29
     40#define CLKID_AHB_QEI		30
     41#define CLKID_AHB_QUADSPI0	31
     42#define CLKID_AHB_CAMIF		32
     43#define CLKID_AHB_LCDIF		33
     44#define CLKID_AHB_TIMER0	34
     45#define CLKID_AHB_TIMER1	35
     46#define CLKID_AHB_TIMER2	36
     47#define CLKID_AHB_TIMER3	37
     48#define CLKID_AHB_IRQ		38
     49#define CLKID_AHB_RTC		39
     50#define CLKID_AHB_NAND		40
     51#define CLKID_AHB_ADC0		41
     52#define CLKID_AHB_LED		42
     53#define CLKID_AHB_DAC0		43
     54#define CLKID_AHB_LCD		44
     55#define CLKID_AHB_I2S1		45
     56#define CLKID_AHB_MAC1		46
     57
     58/* divider */
     59#define CLKID_SYS_CPU		47
     60#define CLKID_SYS_AHB		48
     61#define CLKID_SYS_I2S0M		49
     62#define CLKID_SYS_I2S0S		50
     63#define CLKID_SYS_I2S1M		51
     64#define CLKID_SYS_I2S1S		52
     65#define CLKID_SYS_UART0		53
     66#define CLKID_SYS_UART1		54
     67#define CLKID_SYS_UART2		55
     68#define CLKID_SYS_UART3		56
     69#define CLKID_SYS_UART4		56
     70#define CLKID_SYS_UART5		57
     71#define CLKID_SYS_UART6		58
     72#define CLKID_SYS_UART7		59
     73#define CLKID_SYS_UART8		60
     74#define CLKID_SYS_UART9		61
     75#define CLKID_SYS_SPI0		62
     76#define CLKID_SYS_SPI1		63
     77#define CLKID_SYS_QUADSPI	64
     78#define CLKID_SYS_SSP0		65
     79#define CLKID_SYS_NAND		66
     80#define CLKID_SYS_TRACE		67
     81#define CLKID_SYS_CAMM		68
     82#define CLKID_SYS_WDT		69
     83#define CLKID_SYS_CLKOUT	70
     84#define CLKID_SYS_MAC		71
     85#define CLKID_SYS_LCD		72
     86#define CLKID_SYS_ADCANA	73
     87
     88#define MAX_CLKS		74
     89#endif