cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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aspeed-clock.h (1663B)


      1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
      2
      3#ifndef DT_BINDINGS_ASPEED_CLOCK_H
      4#define DT_BINDINGS_ASPEED_CLOCK_H
      5
      6#define ASPEED_CLK_GATE_ECLK		0
      7#define ASPEED_CLK_GATE_GCLK		1
      8#define ASPEED_CLK_GATE_MCLK		2
      9#define ASPEED_CLK_GATE_VCLK		3
     10#define ASPEED_CLK_GATE_BCLK		4
     11#define ASPEED_CLK_GATE_DCLK		5
     12#define ASPEED_CLK_GATE_REFCLK		6
     13#define ASPEED_CLK_GATE_USBPORT2CLK	7
     14#define ASPEED_CLK_GATE_LCLK		8
     15#define ASPEED_CLK_GATE_USBUHCICLK	9
     16#define ASPEED_CLK_GATE_D1CLK		10
     17#define ASPEED_CLK_GATE_YCLK		11
     18#define ASPEED_CLK_GATE_USBPORT1CLK	12
     19#define ASPEED_CLK_GATE_UART1CLK	13
     20#define ASPEED_CLK_GATE_UART2CLK	14
     21#define ASPEED_CLK_GATE_UART5CLK	15
     22#define ASPEED_CLK_GATE_ESPICLK		16
     23#define ASPEED_CLK_GATE_MAC1CLK		17
     24#define ASPEED_CLK_GATE_MAC2CLK		18
     25#define ASPEED_CLK_GATE_RSACLK		19
     26#define ASPEED_CLK_GATE_UART3CLK	20
     27#define ASPEED_CLK_GATE_UART4CLK	21
     28#define ASPEED_CLK_GATE_SDCLK		22
     29#define ASPEED_CLK_GATE_LHCCLK		23
     30#define ASPEED_CLK_HPLL			24
     31#define ASPEED_CLK_AHB			25
     32#define ASPEED_CLK_APB			26
     33#define ASPEED_CLK_UART			27
     34#define ASPEED_CLK_SDIO			28
     35#define ASPEED_CLK_ECLK			29
     36#define ASPEED_CLK_ECLK_MUX		30
     37#define ASPEED_CLK_LHCLK		31
     38#define ASPEED_CLK_MAC			32
     39#define ASPEED_CLK_BCLK			33
     40#define ASPEED_CLK_MPLL			34
     41#define ASPEED_CLK_24M			35
     42#define ASPEED_CLK_MAC1RCLK		36
     43#define ASPEED_CLK_MAC2RCLK		37
     44
     45#define ASPEED_RESET_XDMA		0
     46#define ASPEED_RESET_MCTP		1
     47#define ASPEED_RESET_ADC		2
     48#define ASPEED_RESET_JTAG_MASTER	3
     49#define ASPEED_RESET_MIC		4
     50#define ASPEED_RESET_PWM		5
     51#define ASPEED_RESET_PECI		6
     52#define ASPEED_RESET_I2C		7
     53#define ASPEED_RESET_AHB		8
     54#define ASPEED_RESET_CRT1		9
     55
     56#endif