hi3559av100-clock.h (5702B)
1/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ 2/* 3 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. 4 * 5 * Author: Dongjiu Geng <gengdongjiu@huawei.com> 6 */ 7 8#ifndef __DTS_HI3559AV100_CLOCK_H 9#define __DTS_HI3559AV100_CLOCK_H 10 11/* fixed rate */ 12#define HI3559AV100_FIXED_1188M 1 13#define HI3559AV100_FIXED_1000M 2 14#define HI3559AV100_FIXED_842M 3 15#define HI3559AV100_FIXED_792M 4 16#define HI3559AV100_FIXED_750M 5 17#define HI3559AV100_FIXED_710M 6 18#define HI3559AV100_FIXED_680M 7 19#define HI3559AV100_FIXED_667M 8 20#define HI3559AV100_FIXED_631M 9 21#define HI3559AV100_FIXED_600M 10 22#define HI3559AV100_FIXED_568M 11 23#define HI3559AV100_FIXED_500M 12 24#define HI3559AV100_FIXED_475M 13 25#define HI3559AV100_FIXED_428M 14 26#define HI3559AV100_FIXED_400M 15 27#define HI3559AV100_FIXED_396M 16 28#define HI3559AV100_FIXED_300M 17 29#define HI3559AV100_FIXED_250M 18 30#define HI3559AV100_FIXED_198M 19 31#define HI3559AV100_FIXED_187p5M 20 32#define HI3559AV100_FIXED_150M 21 33#define HI3559AV100_FIXED_148p5M 22 34#define HI3559AV100_FIXED_125M 23 35#define HI3559AV100_FIXED_107M 24 36#define HI3559AV100_FIXED_100M 25 37#define HI3559AV100_FIXED_99M 26 38#define HI3559AV100_FIXED_74p25M 27 39#define HI3559AV100_FIXED_72M 28 40#define HI3559AV100_FIXED_60M 29 41#define HI3559AV100_FIXED_54M 30 42#define HI3559AV100_FIXED_50M 31 43#define HI3559AV100_FIXED_49p5M 32 44#define HI3559AV100_FIXED_37p125M 33 45#define HI3559AV100_FIXED_36M 34 46#define HI3559AV100_FIXED_32p4M 35 47#define HI3559AV100_FIXED_27M 36 48#define HI3559AV100_FIXED_25M 37 49#define HI3559AV100_FIXED_24M 38 50#define HI3559AV100_FIXED_12M 39 51#define HI3559AV100_FIXED_3M 40 52#define HI3559AV100_FIXED_1p6M 41 53#define HI3559AV100_FIXED_400K 42 54#define HI3559AV100_FIXED_100K 43 55#define HI3559AV100_FIXED_200M 44 56#define HI3559AV100_FIXED_75M 75 57 58#define HI3559AV100_I2C0_CLK 50 59#define HI3559AV100_I2C1_CLK 51 60#define HI3559AV100_I2C2_CLK 52 61#define HI3559AV100_I2C3_CLK 53 62#define HI3559AV100_I2C4_CLK 54 63#define HI3559AV100_I2C5_CLK 55 64#define HI3559AV100_I2C6_CLK 56 65#define HI3559AV100_I2C7_CLK 57 66#define HI3559AV100_I2C8_CLK 58 67#define HI3559AV100_I2C9_CLK 59 68#define HI3559AV100_I2C10_CLK 60 69#define HI3559AV100_I2C11_CLK 61 70 71#define HI3559AV100_SPI0_CLK 62 72#define HI3559AV100_SPI1_CLK 63 73#define HI3559AV100_SPI2_CLK 64 74#define HI3559AV100_SPI3_CLK 65 75#define HI3559AV100_SPI4_CLK 66 76#define HI3559AV100_SPI5_CLK 67 77#define HI3559AV100_SPI6_CLK 68 78 79#define HI3559AV100_EDMAC_CLK 69 80#define HI3559AV100_EDMAC_AXICLK 70 81#define HI3559AV100_EDMAC1_CLK 71 82#define HI3559AV100_EDMAC1_AXICLK 72 83#define HI3559AV100_VDMAC_CLK 73 84 85/* mux clocks */ 86#define HI3559AV100_FMC_MUX 80 87#define HI3559AV100_SYSAPB_MUX 81 88#define HI3559AV100_UART_MUX 82 89#define HI3559AV100_SYSBUS_MUX 83 90#define HI3559AV100_A73_MUX 84 91#define HI3559AV100_MMC0_MUX 85 92#define HI3559AV100_MMC1_MUX 86 93#define HI3559AV100_MMC2_MUX 87 94#define HI3559AV100_MMC3_MUX 88 95 96/* gate clocks */ 97#define HI3559AV100_FMC_CLK 90 98#define HI3559AV100_UART0_CLK 91 99#define HI3559AV100_UART1_CLK 92 100#define HI3559AV100_UART2_CLK 93 101#define HI3559AV100_UART3_CLK 94 102#define HI3559AV100_UART4_CLK 95 103#define HI3559AV100_MMC0_CLK 96 104#define HI3559AV100_MMC1_CLK 97 105#define HI3559AV100_MMC2_CLK 98 106#define HI3559AV100_MMC3_CLK 99 107 108#define HI3559AV100_ETH_CLK 100 109#define HI3559AV100_ETH_MACIF_CLK 101 110#define HI3559AV100_ETH1_CLK 102 111#define HI3559AV100_ETH1_MACIF_CLK 103 112 113/* complex */ 114#define HI3559AV100_MAC0_CLK 110 115#define HI3559AV100_MAC1_CLK 111 116#define HI3559AV100_SATA_CLK 112 117#define HI3559AV100_USB_CLK 113 118#define HI3559AV100_USB1_CLK 114 119 120/* pll clocks */ 121#define HI3559AV100_APLL_CLK 250 122#define HI3559AV100_GPLL_CLK 251 123 124#define HI3559AV100_CRG_NR_CLKS 256 125 126#define HI3559AV100_SHUB_SOURCE_SOC_24M 0 127#define HI3559AV100_SHUB_SOURCE_SOC_200M 1 128#define HI3559AV100_SHUB_SOURCE_SOC_300M 2 129#define HI3559AV100_SHUB_SOURCE_PLL 3 130#define HI3559AV100_SHUB_SOURCE_CLK 4 131 132#define HI3559AV100_SHUB_I2C0_CLK 10 133#define HI3559AV100_SHUB_I2C1_CLK 11 134#define HI3559AV100_SHUB_I2C2_CLK 12 135#define HI3559AV100_SHUB_I2C3_CLK 13 136#define HI3559AV100_SHUB_I2C4_CLK 14 137#define HI3559AV100_SHUB_I2C5_CLK 15 138#define HI3559AV100_SHUB_I2C6_CLK 16 139#define HI3559AV100_SHUB_I2C7_CLK 17 140 141#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20 142#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21 143#define HI3559AV100_SHUB_SPI0_CLK 22 144#define HI3559AV100_SHUB_SPI1_CLK 23 145#define HI3559AV100_SHUB_SPI2_CLK 24 146#define HI3559AV100_SHUB_SPI3_CLK 25 147#define HI3559AV100_SHUB_SPI4_CLK 26 148 149#define HI3559AV100_SHUB_UART_CLK_32K 30 150#define HI3559AV100_SHUB_UART_SOURCE_CLK 31 151#define HI3559AV100_SHUB_UART_DIV_CLK 32 152#define HI3559AV100_SHUB_UART0_CLK 33 153#define HI3559AV100_SHUB_UART1_CLK 34 154#define HI3559AV100_SHUB_UART2_CLK 35 155#define HI3559AV100_SHUB_UART3_CLK 36 156#define HI3559AV100_SHUB_UART4_CLK 37 157#define HI3559AV100_SHUB_UART5_CLK 38 158#define HI3559AV100_SHUB_UART6_CLK 39 159 160#define HI3559AV100_SHUB_EDMAC_CLK 40 161 162#define HI3559AV100_SHUB_NR_CLKS 50 163 164#endif /* __DTS_HI3559AV100_CLOCK_H */ 165